1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_H_ 5 #define _ICE_H_ 6 7 #include <linux/types.h> 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/compiler.h> 13 #include <linux/etherdevice.h> 14 #include <linux/skbuff.h> 15 #include <linux/cpumask.h> 16 #include <linux/rtnetlink.h> 17 #include <linux/if_vlan.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/pci.h> 20 #include <linux/workqueue.h> 21 #include <linux/aer.h> 22 #include <linux/interrupt.h> 23 #include <linux/ethtool.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/bitmap.h> 27 #include <linux/log2.h> 28 #include <linux/ip.h> 29 #include <linux/sctp.h> 30 #include <linux/ipv6.h> 31 #include <linux/if_bridge.h> 32 #include <linux/avf/virtchnl.h> 33 #include <net/ipv6.h> 34 #include "ice_devids.h" 35 #include "ice_type.h" 36 #include "ice_txrx.h" 37 #include "ice_switch.h" 38 #include "ice_common.h" 39 #include "ice_sched.h" 40 #include "ice_virtchnl_pf.h" 41 #include "ice_sriov.h" 42 43 extern const char ice_drv_ver[]; 44 #define ICE_BAR0 0 45 #define ICE_REQ_DESC_MULTIPLE 32 46 #define ICE_MIN_NUM_DESC ICE_REQ_DESC_MULTIPLE 47 #define ICE_MAX_NUM_DESC 8160 48 /* set default number of Rx/Tx descriptors to the minimum between 49 * ICE_MAX_NUM_DESC and the number of descriptors to fill up an entire page 50 */ 51 #define ICE_DFLT_NUM_RX_DESC min_t(u16, ICE_MAX_NUM_DESC, \ 52 ALIGN(PAGE_SIZE / \ 53 sizeof(union ice_32byte_rx_desc), \ 54 ICE_REQ_DESC_MULTIPLE)) 55 #define ICE_DFLT_NUM_TX_DESC min_t(u16, ICE_MAX_NUM_DESC, \ 56 ALIGN(PAGE_SIZE / \ 57 sizeof(struct ice_tx_desc), \ 58 ICE_REQ_DESC_MULTIPLE)) 59 60 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) 61 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16) 62 #define ICE_ETHTOOL_FWVER_LEN 32 63 #define ICE_AQ_LEN 64 64 #define ICE_MBXQ_LEN 64 65 #define ICE_MIN_MSIX 2 66 #define ICE_NO_VSI 0xffff 67 #define ICE_MAX_TXQS 2048 68 #define ICE_MAX_RXQS 2048 69 #define ICE_VSI_MAP_CONTIG 0 70 #define ICE_VSI_MAP_SCATTER 1 71 #define ICE_MAX_SCATTER_TXQS 16 72 #define ICE_MAX_SCATTER_RXQS 16 73 #define ICE_Q_WAIT_RETRY_LIMIT 10 74 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT) 75 #define ICE_MAX_LG_RSS_QS 256 76 #define ICE_MAX_SMALL_RSS_QS 8 77 #define ICE_RES_VALID_BIT 0x8000 78 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 79 #define ICE_INVAL_Q_INDEX 0xffff 80 #define ICE_INVAL_VFID 256 81 #define ICE_MAX_VF_COUNT 256 82 #define ICE_MAX_QS_PER_VF 256 83 #define ICE_MIN_QS_PER_VF 1 84 #define ICE_DFLT_QS_PER_VF 4 85 #define ICE_MAX_BASE_QS_PER_VF 16 86 #define ICE_MAX_INTR_PER_VF 65 87 #define ICE_MIN_INTR_PER_VF (ICE_MIN_QS_PER_VF + 1) 88 #define ICE_DFLT_INTR_PER_VF (ICE_DFLT_QS_PER_VF + 1) 89 90 #define ICE_MAX_RESET_WAIT 20 91 92 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4) 93 94 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 95 96 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \ 97 (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))) 98 99 #define ICE_UP_TABLE_TRANSLATE(val, i) \ 100 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ 101 ICE_AQ_VSI_UP_TABLE_UP##i##_M) 102 103 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 104 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 105 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 106 107 /* Macro for each VSI in a PF */ 108 #define ice_for_each_vsi(pf, i) \ 109 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 110 111 /* Macros for each Tx/Rx ring in a VSI */ 112 #define ice_for_each_txq(vsi, i) \ 113 for ((i) = 0; (i) < (vsi)->num_txq; (i)++) 114 115 #define ice_for_each_rxq(vsi, i) \ 116 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++) 117 118 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */ 119 #define ice_for_each_alloc_txq(vsi, i) \ 120 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++) 121 122 #define ice_for_each_alloc_rxq(vsi, i) \ 123 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++) 124 125 #define ice_for_each_q_vector(vsi, i) \ 126 for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++) 127 128 struct ice_tc_info { 129 u16 qoffset; 130 u16 qcount_tx; 131 u16 qcount_rx; 132 u8 netdev_tc; 133 }; 134 135 struct ice_tc_cfg { 136 u8 numtc; /* Total number of enabled TCs */ 137 u8 ena_tc; /* TX map */ 138 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; 139 }; 140 141 struct ice_res_tracker { 142 u16 num_entries; 143 u16 search_hint; 144 u16 list[1]; 145 }; 146 147 struct ice_qs_cfg { 148 struct mutex *qs_mutex; /* will be assgined to &pf->avail_q_mutex */ 149 unsigned long *pf_map; 150 unsigned long pf_map_size; 151 unsigned int q_count; 152 unsigned int scatter_count; 153 u16 *vsi_map; 154 u16 vsi_map_offset; 155 u8 mapping_mode; 156 }; 157 158 struct ice_sw { 159 struct ice_pf *pf; 160 u16 sw_id; /* switch ID for this switch */ 161 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */ 162 }; 163 164 enum ice_state { 165 __ICE_DOWN, 166 __ICE_NEEDS_RESTART, 167 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */ 168 __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */ 169 __ICE_PFR_REQ, /* set by driver and peers */ 170 __ICE_CORER_REQ, /* set by driver and peers */ 171 __ICE_GLOBR_REQ, /* set by driver and peers */ 172 __ICE_CORER_RECV, /* set by OICR handler */ 173 __ICE_GLOBR_RECV, /* set by OICR handler */ 174 __ICE_EMPR_RECV, /* set by OICR handler */ 175 __ICE_SUSPENDED, /* set on module remove path */ 176 __ICE_RESET_FAILED, /* set by reset/rebuild */ 177 /* When checking for the PF to be in a nominal operating state, the 178 * bits that are grouped at the beginning of the list need to be 179 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will 180 * be checked. If you need to add a bit into consideration for nominal 181 * operating state, it must be added before 182 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position 183 * without appropriate consideration. 184 */ 185 __ICE_STATE_NOMINAL_CHECK_BITS, 186 __ICE_ADMINQ_EVENT_PENDING, 187 __ICE_MAILBOXQ_EVENT_PENDING, 188 __ICE_MDD_EVENT_PENDING, 189 __ICE_VFLR_EVENT_PENDING, 190 __ICE_FLTR_OVERFLOW_PROMISC, 191 __ICE_VF_DIS, 192 __ICE_CFG_BUSY, 193 __ICE_SERVICE_SCHED, 194 __ICE_SERVICE_DIS, 195 __ICE_STATE_NBITS /* must be last */ 196 }; 197 198 enum ice_vsi_flags { 199 ICE_VSI_FLAG_UMAC_FLTR_CHANGED, 200 ICE_VSI_FLAG_MMAC_FLTR_CHANGED, 201 ICE_VSI_FLAG_VLAN_FLTR_CHANGED, 202 ICE_VSI_FLAG_PROMISC_CHANGED, 203 ICE_VSI_FLAG_NBITS /* must be last */ 204 }; 205 206 /* struct that defines a VSI, associated with a dev */ 207 struct ice_vsi { 208 struct net_device *netdev; 209 struct ice_sw *vsw; /* switch this VSI is on */ 210 struct ice_pf *back; /* back pointer to PF */ 211 struct ice_port_info *port_info; /* back pointer to port_info */ 212 struct ice_ring **rx_rings; /* Rx ring array */ 213 struct ice_ring **tx_rings; /* Tx ring array */ 214 struct ice_q_vector **q_vectors; /* q_vector array */ 215 216 irqreturn_t (*irq_handler)(int irq, void *data); 217 218 u64 tx_linearize; 219 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 220 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS); 221 unsigned int current_netdev_flags; 222 u32 tx_restart; 223 u32 tx_busy; 224 u32 rx_buf_failed; 225 u32 rx_page_failed; 226 int num_q_vectors; 227 int sw_base_vector; /* Irq base for OS reserved vectors */ 228 int hw_base_vector; /* HW (absolute) index of a vector */ 229 enum ice_vsi_type type; 230 u16 vsi_num; /* HW (absolute) index of this VSI */ 231 u16 idx; /* software index in pf->vsi[] */ 232 233 /* Interrupt thresholds */ 234 u16 work_lmt; 235 236 s16 vf_id; /* VF ID for SR-IOV VSIs */ 237 238 /* RSS config */ 239 u16 rss_table_size; /* HW RSS table size */ 240 u16 rss_size; /* Allocated RSS queues */ 241 u8 *rss_hkey_user; /* User configured hash keys */ 242 u8 *rss_lut_user; /* User configured lookup table entries */ 243 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */ 244 245 u16 max_frame; 246 u16 rx_buf_len; 247 248 struct ice_aqc_vsi_props info; /* VSI properties */ 249 250 /* VSI stats */ 251 struct rtnl_link_stats64 net_stats; 252 struct ice_eth_stats eth_stats; 253 struct ice_eth_stats eth_stats_prev; 254 255 struct list_head tmp_sync_list; /* MAC filters to be synced */ 256 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */ 257 258 u8 irqs_ready; 259 u8 current_isup; /* Sync 'link up' logging */ 260 u8 stat_offsets_loaded; 261 262 /* queue information */ 263 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 264 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 265 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */ 266 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */ 267 u16 alloc_txq; /* Allocated Tx queues */ 268 u16 num_txq; /* Used Tx queues */ 269 u16 alloc_rxq; /* Allocated Rx queues */ 270 u16 num_rxq; /* Used Rx queues */ 271 u16 num_rx_desc; 272 u16 num_tx_desc; 273 struct ice_tc_cfg tc_cfg; 274 } ____cacheline_internodealigned_in_smp; 275 276 /* struct that defines an interrupt vector */ 277 struct ice_q_vector { 278 struct ice_vsi *vsi; 279 cpumask_t affinity_mask; 280 struct napi_struct napi; 281 struct ice_ring_container rx; 282 struct ice_ring_container tx; 283 struct irq_affinity_notify affinity_notify; 284 u16 v_idx; /* index in the vsi->q_vector array. */ 285 u8 num_ring_tx; /* total number of Tx rings in vector */ 286 u8 num_ring_rx; /* total number of Rx rings in vector */ 287 char name[ICE_INT_NAME_STR_LEN]; 288 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this 289 * value to the device 290 */ 291 u8 intrl; 292 } ____cacheline_internodealigned_in_smp; 293 294 enum ice_pf_flags { 295 ICE_FLAG_MSIX_ENA, 296 ICE_FLAG_FLTR_SYNC, 297 ICE_FLAG_RSS_ENA, 298 ICE_FLAG_SRIOV_ENA, 299 ICE_FLAG_SRIOV_CAPABLE, 300 ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, 301 ICE_PF_FLAGS_NBITS /* must be last */ 302 }; 303 304 struct ice_pf { 305 struct pci_dev *pdev; 306 307 /* OS reserved IRQ details */ 308 struct msix_entry *msix_entries; 309 struct ice_res_tracker *sw_irq_tracker; 310 311 /* HW reserved Interrupts for this PF */ 312 struct ice_res_tracker *hw_irq_tracker; 313 314 struct ice_vsi **vsi; /* VSIs created by the driver */ 315 struct ice_sw *first_sw; /* first switch created by firmware */ 316 /* Virtchnl/SR-IOV config info */ 317 struct ice_vf *vf; 318 int num_alloc_vfs; /* actual number of VFs allocated */ 319 u16 num_vfs_supported; /* num VFs supported for this PF */ 320 u16 num_vf_qps; /* num queue pairs per VF */ 321 u16 num_vf_msix; /* num vectors per VF */ 322 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 323 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS); 324 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS); 325 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS); 326 unsigned long serv_tmr_period; 327 unsigned long serv_tmr_prev; 328 struct timer_list serv_tmr; 329 struct work_struct serv_task; 330 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */ 331 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */ 332 u32 msg_enable; 333 u32 hw_csum_rx_error; 334 u32 sw_oicr_idx; /* Other interrupt cause SW vector index */ 335 u32 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */ 336 u32 hw_oicr_idx; /* Other interrupt cause vector HW index */ 337 u32 num_avail_hw_msix; /* remaining HW MSIX vectors left unclaimed */ 338 u32 num_lan_msix; /* Total MSIX vectors for base driver */ 339 u16 num_lan_tx; /* num lan Tx queues setup */ 340 u16 num_lan_rx; /* num lan Rx queues setup */ 341 u16 q_left_tx; /* remaining num Tx queues left unclaimed */ 342 u16 q_left_rx; /* remaining num Rx queues left unclaimed */ 343 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */ 344 u16 num_alloc_vsi; 345 u16 corer_count; /* Core reset count */ 346 u16 globr_count; /* Global reset count */ 347 u16 empr_count; /* EMP reset count */ 348 u16 pfr_count; /* PF reset count */ 349 350 struct ice_hw_port_stats stats; 351 struct ice_hw_port_stats stats_prev; 352 struct ice_hw hw; 353 u8 stat_prev_loaded; /* has previous stats been loaded */ 354 u32 tx_timeout_count; 355 unsigned long tx_timeout_last_recovery; 356 u32 tx_timeout_recovery_level; 357 char int_name[ICE_INT_NAME_STR_LEN]; 358 }; 359 360 struct ice_netdev_priv { 361 struct ice_vsi *vsi; 362 }; 363 364 /** 365 * ice_irq_dynamic_ena - Enable default interrupt generation settings 366 * @hw: pointer to hw struct 367 * @vsi: pointer to vsi struct, can be NULL 368 * @q_vector: pointer to q_vector, can be NULL 369 */ 370 static inline void 371 ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi, 372 struct ice_q_vector *q_vector) 373 { 374 u32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx : 375 ((struct ice_pf *)hw->back)->hw_oicr_idx; 376 int itr = ICE_ITR_NONE; 377 u32 val; 378 379 /* clear the PBA here, as this function is meant to clean out all 380 * previous interrupts and enable the interrupt 381 */ 382 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 383 (itr << GLINT_DYN_CTL_ITR_INDX_S); 384 if (vsi) 385 if (test_bit(__ICE_DOWN, vsi->state)) 386 return; 387 wr32(hw, GLINT_DYN_CTL(vector), val); 388 } 389 390 static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi) 391 { 392 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; 393 vsi->tc_cfg.numtc = 1; 394 } 395 396 void ice_set_ethtool_ops(struct net_device *netdev); 397 int ice_up(struct ice_vsi *vsi); 398 int ice_down(struct ice_vsi *vsi); 399 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 400 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 401 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size); 402 void ice_print_link_msg(struct ice_vsi *vsi, bool isup); 403 void ice_napi_del(struct ice_vsi *vsi); 404 405 #endif /* _ICE_H_ */ 406