xref: /openbmc/linux/drivers/net/ethernet/intel/ice/ice.h (revision 8ede01785f32269ef4766cf17a535e70ee3c1541)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_H_
5 #define _ICE_H_
6 
7 #include <linux/types.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/compiler.h>
13 #include <linux/etherdevice.h>
14 #include <linux/skbuff.h>
15 #include <linux/cpumask.h>
16 #include <linux/rtnetlink.h>
17 #include <linux/if_vlan.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/pci.h>
20 #include <linux/workqueue.h>
21 #include <linux/aer.h>
22 #include <linux/interrupt.h>
23 #include <linux/ethtool.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <linux/bitmap.h>
27 #include <linux/log2.h>
28 #include <linux/ip.h>
29 #include <linux/ipv6.h>
30 #include <linux/if_bridge.h>
31 #include <linux/avf/virtchnl.h>
32 #include <net/ipv6.h>
33 #include "ice_devids.h"
34 #include "ice_type.h"
35 #include "ice_txrx.h"
36 #include "ice_switch.h"
37 #include "ice_common.h"
38 #include "ice_sched.h"
39 #include "ice_virtchnl_pf.h"
40 
41 extern const char ice_drv_ver[];
42 #define ICE_BAR0		0
43 #define ICE_DFLT_NUM_DESC	128
44 #define ICE_REQ_DESC_MULTIPLE	32
45 #define ICE_MIN_NUM_DESC	ICE_REQ_DESC_MULTIPLE
46 #define ICE_MAX_NUM_DESC	8160
47 #define ICE_DFLT_TRAFFIC_CLASS	BIT(0)
48 #define ICE_INT_NAME_STR_LEN	(IFNAMSIZ + 16)
49 #define ICE_ETHTOOL_FWVER_LEN	32
50 #define ICE_AQ_LEN		64
51 #define ICE_MBXQ_LEN		64
52 #define ICE_MIN_MSIX		2
53 #define ICE_NO_VSI		0xffff
54 #define ICE_MAX_VSI_ALLOC	130
55 #define ICE_MAX_TXQS		2048
56 #define ICE_MAX_RXQS		2048
57 #define ICE_VSI_MAP_CONTIG	0
58 #define ICE_VSI_MAP_SCATTER	1
59 #define ICE_MAX_SCATTER_TXQS	16
60 #define ICE_MAX_SCATTER_RXQS	16
61 #define ICE_Q_WAIT_RETRY_LIMIT	10
62 #define ICE_Q_WAIT_MAX_RETRY	(5 * ICE_Q_WAIT_RETRY_LIMIT)
63 #define ICE_MAX_LG_RSS_QS	256
64 #define ICE_MAX_SMALL_RSS_QS	8
65 #define ICE_RES_VALID_BIT	0x8000
66 #define ICE_RES_MISC_VEC_ID	(ICE_RES_VALID_BIT - 1)
67 #define ICE_INVAL_Q_INDEX	0xffff
68 #define ICE_INVAL_VFID		256
69 #define ICE_MAX_VF_COUNT	256
70 #define ICE_MAX_QS_PER_VF		256
71 #define ICE_MIN_QS_PER_VF		1
72 #define ICE_DFLT_QS_PER_VF		4
73 #define ICE_MAX_INTR_PER_VF		65
74 #define ICE_MIN_INTR_PER_VF		(ICE_MIN_QS_PER_VF + 1)
75 #define ICE_DFLT_INTR_PER_VF		(ICE_DFLT_QS_PER_VF + 1)
76 
77 #define ICE_VSIQF_HKEY_ARRAY_SIZE	((VSIQF_HKEY_MAX_INDEX + 1) *	4)
78 
79 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
80 
81 #define ICE_MAX_MTU	(ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
82 			 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
83 
84 #define ICE_UP_TABLE_TRANSLATE(val, i) \
85 		(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
86 		  ICE_AQ_VSI_UP_TABLE_UP##i##_M)
87 
88 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
89 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
90 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
91 
92 /* Macro for each VSI in a PF */
93 #define ice_for_each_vsi(pf, i) \
94 	for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
95 
96 /* Macros for each tx/rx ring in a VSI */
97 #define ice_for_each_txq(vsi, i) \
98 	for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
99 
100 #define ice_for_each_rxq(vsi, i) \
101 	for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
102 
103 /* Macros for each allocated tx/rx ring whether used or not in a VSI */
104 #define ice_for_each_alloc_txq(vsi, i) \
105 	for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
106 
107 #define ice_for_each_alloc_rxq(vsi, i) \
108 	for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
109 
110 struct ice_tc_info {
111 	u16 qoffset;
112 	u16 qcount;
113 };
114 
115 struct ice_tc_cfg {
116 	u8 numtc; /* Total number of enabled TCs */
117 	u8 ena_tc; /* TX map */
118 	struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
119 };
120 
121 struct ice_res_tracker {
122 	u16 num_entries;
123 	u16 search_hint;
124 	u16 list[1];
125 };
126 
127 struct ice_sw {
128 	struct ice_pf *pf;
129 	u16 sw_id;		/* switch ID for this switch */
130 	u16 bridge_mode;	/* VEB/VEPA/Port Virtualizer */
131 };
132 
133 enum ice_state {
134 	__ICE_DOWN,
135 	__ICE_NEEDS_RESTART,
136 	__ICE_PREPARED_FOR_RESET,	/* set by driver when prepared */
137 	__ICE_RESET_OICR_RECV,		/* set by driver after rcv reset OICR */
138 	__ICE_PFR_REQ,			/* set by driver and peers */
139 	__ICE_CORER_REQ,		/* set by driver and peers */
140 	__ICE_GLOBR_REQ,		/* set by driver and peers */
141 	__ICE_CORER_RECV,		/* set by OICR handler */
142 	__ICE_GLOBR_RECV,		/* set by OICR handler */
143 	__ICE_EMPR_RECV,		/* set by OICR handler */
144 	__ICE_SUSPENDED,		/* set on module remove path */
145 	__ICE_RESET_FAILED,		/* set by reset/rebuild */
146 	/* When checking for the PF to be in a nominal operating state, the
147 	 * bits that are grouped at the beginning of the list need to be
148 	 * checked.  Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will
149 	 * be checked.  If you need to add a bit into consideration for nominal
150 	 * operating state, it must be added before
151 	 * __ICE_STATE_NOMINAL_CHECK_BITS.  Do not move this entry's position
152 	 * without appropriate consideration.
153 	 */
154 	__ICE_STATE_NOMINAL_CHECK_BITS,
155 	__ICE_ADMINQ_EVENT_PENDING,
156 	__ICE_MAILBOXQ_EVENT_PENDING,
157 	__ICE_MDD_EVENT_PENDING,
158 	__ICE_FLTR_OVERFLOW_PROMISC,
159 	__ICE_VF_DIS,
160 	__ICE_CFG_BUSY,
161 	__ICE_SERVICE_SCHED,
162 	__ICE_SERVICE_DIS,
163 	__ICE_STATE_NBITS		/* must be last */
164 };
165 
166 enum ice_vsi_flags {
167 	ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
168 	ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
169 	ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
170 	ICE_VSI_FLAG_PROMISC_CHANGED,
171 	ICE_VSI_FLAG_NBITS		/* must be last */
172 };
173 
174 /* struct that defines a VSI, associated with a dev */
175 struct ice_vsi {
176 	struct net_device *netdev;
177 	struct ice_sw *vsw;		 /* switch this VSI is on */
178 	struct ice_pf *back;		 /* back pointer to PF */
179 	struct ice_port_info *port_info; /* back pointer to port_info */
180 	struct ice_ring **rx_rings;	 /* rx ring array */
181 	struct ice_ring **tx_rings;	 /* tx ring array */
182 	struct ice_q_vector **q_vectors; /* q_vector array */
183 
184 	irqreturn_t (*irq_handler)(int irq, void *data);
185 
186 	u64 tx_linearize;
187 	DECLARE_BITMAP(state, __ICE_STATE_NBITS);
188 	DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
189 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
190 	unsigned int current_netdev_flags;
191 	u32 tx_restart;
192 	u32 tx_busy;
193 	u32 rx_buf_failed;
194 	u32 rx_page_failed;
195 	int num_q_vectors;
196 	int sw_base_vector;		/* Irq base for OS reserved vectors */
197 	int hw_base_vector;		/* HW (absolute) index of a vector */
198 	enum ice_vsi_type type;
199 	u16 vsi_num;			 /* HW (absolute) index of this VSI */
200 	u16 idx;			 /* software index in pf->vsi[] */
201 
202 	/* Interrupt thresholds */
203 	u16 work_lmt;
204 
205 	s16 vf_id;			/* VF ID for SR-IOV VSIs */
206 
207 	/* RSS config */
208 	u16 rss_table_size;	/* HW RSS table size */
209 	u16 rss_size;		/* Allocated RSS queues */
210 	u8 *rss_hkey_user;	/* User configured hash keys */
211 	u8 *rss_lut_user;	/* User configured lookup table entries */
212 	u8 rss_lut_type;	/* used to configure Get/Set RSS LUT AQ call */
213 
214 	u16 max_frame;
215 	u16 rx_buf_len;
216 
217 	struct ice_aqc_vsi_props info;	 /* VSI properties */
218 
219 	/* VSI stats */
220 	struct rtnl_link_stats64 net_stats;
221 	struct ice_eth_stats eth_stats;
222 	struct ice_eth_stats eth_stats_prev;
223 
224 	struct list_head tmp_sync_list;		/* MAC filters to be synced */
225 	struct list_head tmp_unsync_list;	/* MAC filters to be unsynced */
226 
227 	u8 irqs_ready;
228 	u8 current_isup;		 /* Sync 'link up' logging */
229 	u8 stat_offsets_loaded;
230 
231 	/* queue information */
232 	u8 tx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */
233 	u8 rx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */
234 	u16 txq_map[ICE_MAX_TXQS];	 /* index in pf->avail_txqs */
235 	u16 rxq_map[ICE_MAX_RXQS];	 /* index in pf->avail_rxqs */
236 	u16 alloc_txq;			 /* Allocated Tx queues */
237 	u16 num_txq;			 /* Used Tx queues */
238 	u16 alloc_rxq;			 /* Allocated Rx queues */
239 	u16 num_rxq;			 /* Used Rx queues */
240 	u16 num_desc;
241 	struct ice_tc_cfg tc_cfg;
242 } ____cacheline_internodealigned_in_smp;
243 
244 /* struct that defines an interrupt vector */
245 struct ice_q_vector {
246 	struct ice_vsi *vsi;
247 	cpumask_t affinity_mask;
248 	struct napi_struct napi;
249 	struct ice_ring_container rx;
250 	struct ice_ring_container tx;
251 	struct irq_affinity_notify affinity_notify;
252 	u16 v_idx;			/* index in the vsi->q_vector array. */
253 	u8 num_ring_tx;			/* total number of tx rings in vector */
254 	u8 num_ring_rx;			/* total number of rx rings in vector */
255 	char name[ICE_INT_NAME_STR_LEN];
256 	/* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
257 	 * value to the device
258 	 */
259 	u8 intrl;
260 } ____cacheline_internodealigned_in_smp;
261 
262 enum ice_pf_flags {
263 	ICE_FLAG_MSIX_ENA,
264 	ICE_FLAG_FLTR_SYNC,
265 	ICE_FLAG_RSS_ENA,
266 	ICE_FLAG_SRIOV_ENA,
267 	ICE_FLAG_SRIOV_CAPABLE,
268 	ICE_PF_FLAGS_NBITS		/* must be last */
269 };
270 
271 struct ice_pf {
272 	struct pci_dev *pdev;
273 
274 	/* OS reserved IRQ details */
275 	struct msix_entry *msix_entries;
276 	struct ice_res_tracker *sw_irq_tracker;
277 
278 	/* HW reserved Interrupts for this PF */
279 	struct ice_res_tracker *hw_irq_tracker;
280 
281 	struct ice_vsi **vsi;		/* VSIs created by the driver */
282 	struct ice_sw *first_sw;	/* first switch created by firmware */
283 	/* Virtchnl/SR-IOV config info */
284 	struct ice_vf *vf;
285 	int num_alloc_vfs;		/* actual number of VFs allocated */
286 	u16 num_vfs_supported;		/* num VFs supported for this PF */
287 	u16 num_vf_qps;			/* num queue pairs per VF */
288 	u16 num_vf_msix;		/* num vectors per VF */
289 	DECLARE_BITMAP(state, __ICE_STATE_NBITS);
290 	DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
291 	DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
292 	DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
293 	unsigned long serv_tmr_period;
294 	unsigned long serv_tmr_prev;
295 	struct timer_list serv_tmr;
296 	struct work_struct serv_task;
297 	struct mutex avail_q_mutex;	/* protects access to avail_[rx|tx]qs */
298 	struct mutex sw_mutex;		/* lock for protecting VSI alloc flow */
299 	u32 msg_enable;
300 	u32 hw_csum_rx_error;
301 	u32 sw_oicr_idx;	/* Other interrupt cause SW vector index */
302 	u32 num_avail_sw_msix;	/* remaining MSIX SW vectors left unclaimed */
303 	u32 hw_oicr_idx;	/* Other interrupt cause vector HW index */
304 	u32 num_avail_hw_msix;	/* remaining HW MSIX vectors left unclaimed */
305 	u32 num_lan_msix;	/* Total MSIX vectors for base driver */
306 	u16 num_lan_tx;		/* num lan tx queues setup */
307 	u16 num_lan_rx;		/* num lan rx queues setup */
308 	u16 q_left_tx;		/* remaining num tx queues left unclaimed */
309 	u16 q_left_rx;		/* remaining num rx queues left unclaimed */
310 	u16 next_vsi;		/* Next free slot in pf->vsi[] - 0-based! */
311 	u16 num_alloc_vsi;
312 	u16 corer_count;	/* Core reset count */
313 	u16 globr_count;	/* Global reset count */
314 	u16 empr_count;		/* EMP reset count */
315 	u16 pfr_count;		/* PF reset count */
316 
317 	struct ice_hw_port_stats stats;
318 	struct ice_hw_port_stats stats_prev;
319 	struct ice_hw hw;
320 	u8 stat_prev_loaded;	/* has previous stats been loaded */
321 	u32 tx_timeout_count;
322 	unsigned long tx_timeout_last_recovery;
323 	u32 tx_timeout_recovery_level;
324 	char int_name[ICE_INT_NAME_STR_LEN];
325 };
326 
327 struct ice_netdev_priv {
328 	struct ice_vsi *vsi;
329 };
330 
331 /**
332  * ice_irq_dynamic_ena - Enable default interrupt generation settings
333  * @hw: pointer to hw struct
334  * @vsi: pointer to vsi struct, can be NULL
335  * @q_vector: pointer to q_vector, can be NULL
336  */
337 static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
338 				       struct ice_q_vector *q_vector)
339 {
340 	u32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx :
341 				((struct ice_pf *)hw->back)->hw_oicr_idx;
342 	int itr = ICE_ITR_NONE;
343 	u32 val;
344 
345 	/* clear the PBA here, as this function is meant to clean out all
346 	 * previous interrupts and enable the interrupt
347 	 */
348 	val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
349 	      (itr << GLINT_DYN_CTL_ITR_INDX_S);
350 	if (vsi)
351 		if (test_bit(__ICE_DOWN, vsi->state))
352 			return;
353 	wr32(hw, GLINT_DYN_CTL(vector), val);
354 }
355 
356 static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
357 {
358 	vsi->tc_cfg.ena_tc =  ICE_DFLT_TRAFFIC_CLASS;
359 	vsi->tc_cfg.numtc = 1;
360 }
361 
362 void ice_set_ethtool_ops(struct net_device *netdev);
363 int ice_up(struct ice_vsi *vsi);
364 int ice_down(struct ice_vsi *vsi);
365 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
366 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
367 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
368 void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
369 
370 #endif /* _ICE_H_ */
371