xref: /openbmc/linux/drivers/net/ethernet/intel/ice/ice.h (revision 8c243700ab10a56171858cc9dd17c5d6494a0ed6)
1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */
2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */
3837f08fdSAnirudh Venkataramanan 
4837f08fdSAnirudh Venkataramanan #ifndef _ICE_H_
5837f08fdSAnirudh Venkataramanan #define _ICE_H_
6837f08fdSAnirudh Venkataramanan 
7837f08fdSAnirudh Venkataramanan #include <linux/types.h>
8837f08fdSAnirudh Venkataramanan #include <linux/errno.h>
9837f08fdSAnirudh Venkataramanan #include <linux/kernel.h>
10837f08fdSAnirudh Venkataramanan #include <linux/module.h>
11837f08fdSAnirudh Venkataramanan #include <linux/netdevice.h>
12837f08fdSAnirudh Venkataramanan #include <linux/compiler.h>
13dc49c772SAnirudh Venkataramanan #include <linux/etherdevice.h>
14cdedef59SAnirudh Venkataramanan #include <linux/skbuff.h>
153a858ba3SAnirudh Venkataramanan #include <linux/cpumask.h>
16fcea6f3dSAnirudh Venkataramanan #include <linux/rtnetlink.h>
173a858ba3SAnirudh Venkataramanan #include <linux/if_vlan.h>
18cdedef59SAnirudh Venkataramanan #include <linux/dma-mapping.h>
19837f08fdSAnirudh Venkataramanan #include <linux/pci.h>
20940b61afSAnirudh Venkataramanan #include <linux/workqueue.h>
21837f08fdSAnirudh Venkataramanan #include <linux/aer.h>
22940b61afSAnirudh Venkataramanan #include <linux/interrupt.h>
23fcea6f3dSAnirudh Venkataramanan #include <linux/ethtool.h>
24940b61afSAnirudh Venkataramanan #include <linux/timer.h>
257ec59eeaSAnirudh Venkataramanan #include <linux/delay.h>
26837f08fdSAnirudh Venkataramanan #include <linux/bitmap.h>
273a858ba3SAnirudh Venkataramanan #include <linux/log2.h>
28d76a60baSAnirudh Venkataramanan #include <linux/ip.h>
29cf909e19SAnirudh Venkataramanan #include <linux/sctp.h>
30d76a60baSAnirudh Venkataramanan #include <linux/ipv6.h>
31940b61afSAnirudh Venkataramanan #include <linux/if_bridge.h>
32ddf30f7fSAnirudh Venkataramanan #include <linux/avf/virtchnl.h>
33d76a60baSAnirudh Venkataramanan #include <net/ipv6.h>
34837f08fdSAnirudh Venkataramanan #include "ice_devids.h"
35837f08fdSAnirudh Venkataramanan #include "ice_type.h"
36940b61afSAnirudh Venkataramanan #include "ice_txrx.h"
3737b6f646SAnirudh Venkataramanan #include "ice_dcb.h"
389c20346bSAnirudh Venkataramanan #include "ice_switch.h"
39f31e4b6fSAnirudh Venkataramanan #include "ice_common.h"
409c20346bSAnirudh Venkataramanan #include "ice_sched.h"
41ddf30f7fSAnirudh Venkataramanan #include "ice_virtchnl_pf.h"
42007676b4SAnirudh Venkataramanan #include "ice_sriov.h"
43837f08fdSAnirudh Venkataramanan 
44fcea6f3dSAnirudh Venkataramanan extern const char ice_drv_ver[];
45837f08fdSAnirudh Venkataramanan #define ICE_BAR0		0
463a858ba3SAnirudh Venkataramanan #define ICE_REQ_DESC_MULTIPLE	32
478be92a76SPreethi Banala #define ICE_MIN_NUM_DESC	64
483b6bf296SBruce Allan #define ICE_MAX_NUM_DESC	8160
491aec6e1bSBrett Creeley #define ICE_DFLT_MIN_RX_DESC	512
501aec6e1bSBrett Creeley /* if the default number of Rx descriptors between ICE_MAX_NUM_DESC and the
511aec6e1bSBrett Creeley  * number of descriptors to fill up an entire page is greater than or equal to
521aec6e1bSBrett Creeley  * ICE_DFLT_MIN_RX_DESC set it based on page size, otherwise set it to
531aec6e1bSBrett Creeley  * ICE_DFLT_MIN_RX_DESC
54ad71b256SBrett Creeley  */
551aec6e1bSBrett Creeley #define ICE_DFLT_NUM_RX_DESC \
561aec6e1bSBrett Creeley 	min_t(u16, ICE_MAX_NUM_DESC, \
571aec6e1bSBrett Creeley 	      max_t(u16, ALIGN(PAGE_SIZE / sizeof(union ice_32byte_rx_desc), \
581aec6e1bSBrett Creeley 			       ICE_REQ_DESC_MULTIPLE), \
591aec6e1bSBrett Creeley 		    ICE_DFLT_MIN_RX_DESC))
601aec6e1bSBrett Creeley /* set default number of Tx descriptors to the minimum between ICE_MAX_NUM_DESC
611aec6e1bSBrett Creeley  * and the number of descriptors to fill up an entire page
621aec6e1bSBrett Creeley  */
63ad71b256SBrett Creeley #define ICE_DFLT_NUM_TX_DESC	min_t(u16, ICE_MAX_NUM_DESC, \
64ad71b256SBrett Creeley 				      ALIGN(PAGE_SIZE / \
65ad71b256SBrett Creeley 					    sizeof(struct ice_tx_desc), \
66ad71b256SBrett Creeley 					    ICE_REQ_DESC_MULTIPLE))
67ad71b256SBrett Creeley 
685513b920SAnirudh Venkataramanan #define ICE_DFLT_TRAFFIC_CLASS	BIT(0)
69940b61afSAnirudh Venkataramanan #define ICE_INT_NAME_STR_LEN	(IFNAMSIZ + 16)
70fcea6f3dSAnirudh Venkataramanan #define ICE_ETHTOOL_FWVER_LEN	32
71f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_LEN		64
7211836214SBrett Creeley #define ICE_MBXSQ_LEN		64
7311836214SBrett Creeley #define ICE_MBXRQ_LEN		512
74940b61afSAnirudh Venkataramanan #define ICE_MIN_MSIX		2
753a858ba3SAnirudh Venkataramanan #define ICE_NO_VSI		0xffff
763a858ba3SAnirudh Venkataramanan #define ICE_VSI_MAP_CONTIG	0
773a858ba3SAnirudh Venkataramanan #define ICE_VSI_MAP_SCATTER	1
783a858ba3SAnirudh Venkataramanan #define ICE_MAX_SCATTER_TXQS	16
793a858ba3SAnirudh Venkataramanan #define ICE_MAX_SCATTER_RXQS	16
80cdedef59SAnirudh Venkataramanan #define ICE_Q_WAIT_RETRY_LIMIT	10
81cdedef59SAnirudh Venkataramanan #define ICE_Q_WAIT_MAX_RETRY	(5 * ICE_Q_WAIT_RETRY_LIMIT)
82d76a60baSAnirudh Venkataramanan #define ICE_MAX_LG_RSS_QS	256
83d76a60baSAnirudh Venkataramanan #define ICE_MAX_SMALL_RSS_QS	8
84940b61afSAnirudh Venkataramanan #define ICE_RES_VALID_BIT	0x8000
85940b61afSAnirudh Venkataramanan #define ICE_RES_MISC_VEC_ID	(ICE_RES_VALID_BIT - 1)
863a858ba3SAnirudh Venkataramanan #define ICE_INVAL_Q_INDEX	0xffff
870f9d5027SAnirudh Venkataramanan #define ICE_INVAL_VFID		256
88837f08fdSAnirudh Venkataramanan 
89afd9d4abSAnirudh Venkataramanan #define ICE_MAX_RESET_WAIT		20
90afd9d4abSAnirudh Venkataramanan 
91fcea6f3dSAnirudh Venkataramanan #define ICE_VSIQF_HKEY_ARRAY_SIZE	((VSIQF_HKEY_MAX_INDEX + 1) *	4)
92fcea6f3dSAnirudh Venkataramanan 
93837f08fdSAnirudh Venkataramanan #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
94837f08fdSAnirudh Venkataramanan 
953a858ba3SAnirudh Venkataramanan #define ICE_MAX_MTU	(ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
965ed5d316SMaciej Fijalkowski 			(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)))
973a858ba3SAnirudh Venkataramanan 
983a858ba3SAnirudh Venkataramanan #define ICE_UP_TABLE_TRANSLATE(val, i) \
993a858ba3SAnirudh Venkataramanan 		(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
1003a858ba3SAnirudh Venkataramanan 		  ICE_AQ_VSI_UP_TABLE_UP##i##_M)
1013a858ba3SAnirudh Venkataramanan 
1022b245cb2SAnirudh Venkataramanan #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
103cdedef59SAnirudh Venkataramanan #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
104d76a60baSAnirudh Venkataramanan #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
105cdedef59SAnirudh Venkataramanan 
1060b28b702SAnirudh Venkataramanan /* Macro for each VSI in a PF */
1070b28b702SAnirudh Venkataramanan #define ice_for_each_vsi(pf, i) \
1080b28b702SAnirudh Venkataramanan 	for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
1090b28b702SAnirudh Venkataramanan 
110d337f2afSAnirudh Venkataramanan /* Macros for each Tx/Rx ring in a VSI */
111cdedef59SAnirudh Venkataramanan #define ice_for_each_txq(vsi, i) \
112cdedef59SAnirudh Venkataramanan 	for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
113cdedef59SAnirudh Venkataramanan 
114cdedef59SAnirudh Venkataramanan #define ice_for_each_rxq(vsi, i) \
115cdedef59SAnirudh Venkataramanan 	for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
116cdedef59SAnirudh Venkataramanan 
117d337f2afSAnirudh Venkataramanan /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */
118f8ba7db8SJacob Keller #define ice_for_each_alloc_txq(vsi, i) \
119f8ba7db8SJacob Keller 	for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
120f8ba7db8SJacob Keller 
121f8ba7db8SJacob Keller #define ice_for_each_alloc_rxq(vsi, i) \
122f8ba7db8SJacob Keller 	for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
123f8ba7db8SJacob Keller 
12467fe64d7SBrett Creeley #define ice_for_each_q_vector(vsi, i) \
12567fe64d7SBrett Creeley 	for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
12667fe64d7SBrett Creeley 
1275eda8afdSAkeem G Abodunrin #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \
1285eda8afdSAkeem G Abodunrin 				ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX)
1295eda8afdSAkeem G Abodunrin 
1305eda8afdSAkeem G Abodunrin #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \
1315eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_MCAST_TX | \
1325eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_UCAST_RX | \
1335eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_MCAST_RX | \
1345eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_VLAN_TX  | \
1355eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_VLAN_RX)
1365eda8afdSAkeem G Abodunrin 
1375eda8afdSAkeem G Abodunrin #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX)
1385eda8afdSAkeem G Abodunrin 
1395eda8afdSAkeem G Abodunrin #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \
1405eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_MCAST_RX | \
1415eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_VLAN_TX  | \
1425eda8afdSAkeem G Abodunrin 				     ICE_PROMISC_VLAN_RX)
1435eda8afdSAkeem G Abodunrin 
1443a858ba3SAnirudh Venkataramanan struct ice_tc_info {
1453a858ba3SAnirudh Venkataramanan 	u16 qoffset;
146c5a2a4a3SUsha Ketineni 	u16 qcount_tx;
147c5a2a4a3SUsha Ketineni 	u16 qcount_rx;
148c5a2a4a3SUsha Ketineni 	u8 netdev_tc;
1493a858ba3SAnirudh Venkataramanan };
1503a858ba3SAnirudh Venkataramanan 
1513a858ba3SAnirudh Venkataramanan struct ice_tc_cfg {
1523a858ba3SAnirudh Venkataramanan 	u8 numtc; /* Total number of enabled TCs */
153f9867df6SAnirudh Venkataramanan 	u8 ena_tc; /* Tx map */
1543a858ba3SAnirudh Venkataramanan 	struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
1553a858ba3SAnirudh Venkataramanan };
1563a858ba3SAnirudh Venkataramanan 
157940b61afSAnirudh Venkataramanan struct ice_res_tracker {
158940b61afSAnirudh Venkataramanan 	u16 num_entries;
159cbe66bfeSBrett Creeley 	u16 end;
160940b61afSAnirudh Venkataramanan 	u16 list[1];
161940b61afSAnirudh Venkataramanan };
162940b61afSAnirudh Venkataramanan 
16303f7a986SAnirudh Venkataramanan struct ice_qs_cfg {
16494c4441bSAnirudh Venkataramanan 	struct mutex *qs_mutex;  /* will be assigned to &pf->avail_q_mutex */
16503f7a986SAnirudh Venkataramanan 	unsigned long *pf_map;
16603f7a986SAnirudh Venkataramanan 	unsigned long pf_map_size;
16703f7a986SAnirudh Venkataramanan 	unsigned int q_count;
16803f7a986SAnirudh Venkataramanan 	unsigned int scatter_count;
16903f7a986SAnirudh Venkataramanan 	u16 *vsi_map;
17003f7a986SAnirudh Venkataramanan 	u16 vsi_map_offset;
17103f7a986SAnirudh Venkataramanan 	u8 mapping_mode;
17203f7a986SAnirudh Venkataramanan };
17303f7a986SAnirudh Venkataramanan 
174940b61afSAnirudh Venkataramanan struct ice_sw {
175940b61afSAnirudh Venkataramanan 	struct ice_pf *pf;
176940b61afSAnirudh Venkataramanan 	u16 sw_id;		/* switch ID for this switch */
177940b61afSAnirudh Venkataramanan 	u16 bridge_mode;	/* VEB/VEPA/Port Virtualizer */
178940b61afSAnirudh Venkataramanan };
179940b61afSAnirudh Venkataramanan 
180837f08fdSAnirudh Venkataramanan enum ice_state {
1810e674aebSAnirudh Venkataramanan 	__ICE_TESTING,
182837f08fdSAnirudh Venkataramanan 	__ICE_DOWN,
1830b28b702SAnirudh Venkataramanan 	__ICE_NEEDS_RESTART,
1840f9d5027SAnirudh Venkataramanan 	__ICE_PREPARED_FOR_RESET,	/* set by driver when prepared */
1855df7e45dSDave Ertman 	__ICE_RESET_OICR_RECV,		/* set by driver after rcv reset OICR */
186940b61afSAnirudh Venkataramanan 	__ICE_PFR_REQ,			/* set by driver and peers */
1870b28b702SAnirudh Venkataramanan 	__ICE_CORER_REQ,		/* set by driver and peers */
1880b28b702SAnirudh Venkataramanan 	__ICE_GLOBR_REQ,		/* set by driver and peers */
1890b28b702SAnirudh Venkataramanan 	__ICE_CORER_RECV,		/* set by OICR handler */
1900b28b702SAnirudh Venkataramanan 	__ICE_GLOBR_RECV,		/* set by OICR handler */
1910b28b702SAnirudh Venkataramanan 	__ICE_EMPR_RECV,		/* set by OICR handler */
1920b28b702SAnirudh Venkataramanan 	__ICE_SUSPENDED,		/* set on module remove path */
1930b28b702SAnirudh Venkataramanan 	__ICE_RESET_FAILED,		/* set by reset/rebuild */
194ddf30f7fSAnirudh Venkataramanan 	/* When checking for the PF to be in a nominal operating state, the
195ddf30f7fSAnirudh Venkataramanan 	 * bits that are grouped at the beginning of the list need to be
196ddf30f7fSAnirudh Venkataramanan 	 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will
197ddf30f7fSAnirudh Venkataramanan 	 * be checked. If you need to add a bit into consideration for nominal
198ddf30f7fSAnirudh Venkataramanan 	 * operating state, it must be added before
199ddf30f7fSAnirudh Venkataramanan 	 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
200ddf30f7fSAnirudh Venkataramanan 	 * without appropriate consideration.
201ddf30f7fSAnirudh Venkataramanan 	 */
202ddf30f7fSAnirudh Venkataramanan 	__ICE_STATE_NOMINAL_CHECK_BITS,
203940b61afSAnirudh Venkataramanan 	__ICE_ADMINQ_EVENT_PENDING,
20475d2b253SAnirudh Venkataramanan 	__ICE_MAILBOXQ_EVENT_PENDING,
205b3969fd7SSudheer Mogilappagari 	__ICE_MDD_EVENT_PENDING,
206007676b4SAnirudh Venkataramanan 	__ICE_VFLR_EVENT_PENDING,
207e94d4478SAnirudh Venkataramanan 	__ICE_FLTR_OVERFLOW_PROMISC,
208ddf30f7fSAnirudh Venkataramanan 	__ICE_VF_DIS,
209fcea6f3dSAnirudh Venkataramanan 	__ICE_CFG_BUSY,
210940b61afSAnirudh Venkataramanan 	__ICE_SERVICE_SCHED,
2118d81fa55SAkeem G Abodunrin 	__ICE_SERVICE_DIS,
212d82dd83dSAkeem G Abodunrin 	__ICE_OICR_INTR_DIS,		/* Global OICR interrupt disabled */
213837f08fdSAnirudh Venkataramanan 	__ICE_STATE_NBITS		/* must be last */
214837f08fdSAnirudh Venkataramanan };
215837f08fdSAnirudh Venkataramanan 
216e94d4478SAnirudh Venkataramanan enum ice_vsi_flags {
217e94d4478SAnirudh Venkataramanan 	ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
218e94d4478SAnirudh Venkataramanan 	ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
219e94d4478SAnirudh Venkataramanan 	ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
220e94d4478SAnirudh Venkataramanan 	ICE_VSI_FLAG_PROMISC_CHANGED,
221e94d4478SAnirudh Venkataramanan 	ICE_VSI_FLAG_NBITS		/* must be last */
222e94d4478SAnirudh Venkataramanan };
223e94d4478SAnirudh Venkataramanan 
224940b61afSAnirudh Venkataramanan /* struct that defines a VSI, associated with a dev */
225940b61afSAnirudh Venkataramanan struct ice_vsi {
226940b61afSAnirudh Venkataramanan 	struct net_device *netdev;
2273a858ba3SAnirudh Venkataramanan 	struct ice_sw *vsw;		 /* switch this VSI is on */
2283a858ba3SAnirudh Venkataramanan 	struct ice_pf *back;		 /* back pointer to PF */
229940b61afSAnirudh Venkataramanan 	struct ice_port_info *port_info; /* back pointer to port_info */
230d337f2afSAnirudh Venkataramanan 	struct ice_ring **rx_rings;	 /* Rx ring array */
231d337f2afSAnirudh Venkataramanan 	struct ice_ring **tx_rings;	 /* Tx ring array */
2323a858ba3SAnirudh Venkataramanan 	struct ice_q_vector **q_vectors; /* q_vector array */
233cdedef59SAnirudh Venkataramanan 
234cdedef59SAnirudh Venkataramanan 	irqreturn_t (*irq_handler)(int irq, void *data);
235cdedef59SAnirudh Venkataramanan 
236fcea6f3dSAnirudh Venkataramanan 	u64 tx_linearize;
2373a858ba3SAnirudh Venkataramanan 	DECLARE_BITMAP(state, __ICE_STATE_NBITS);
238e94d4478SAnirudh Venkataramanan 	DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
239e94d4478SAnirudh Venkataramanan 	unsigned int current_netdev_flags;
240fcea6f3dSAnirudh Venkataramanan 	u32 tx_restart;
241fcea6f3dSAnirudh Venkataramanan 	u32 tx_busy;
242fcea6f3dSAnirudh Venkataramanan 	u32 rx_buf_failed;
243fcea6f3dSAnirudh Venkataramanan 	u32 rx_page_failed;
2443a858ba3SAnirudh Venkataramanan 	int num_q_vectors;
245cbe66bfeSBrett Creeley 	int base_vector;		/* IRQ base for OS reserved vectors */
2463a858ba3SAnirudh Venkataramanan 	enum ice_vsi_type type;
247940b61afSAnirudh Venkataramanan 	u16 vsi_num;			/* HW (absolute) index of this VSI */
2483a858ba3SAnirudh Venkataramanan 	u16 idx;			/* software index in pf->vsi[] */
2493a858ba3SAnirudh Venkataramanan 
2508ede0178SAnirudh Venkataramanan 	s16 vf_id;			/* VF ID for SR-IOV VSIs */
2518ede0178SAnirudh Venkataramanan 
252d95276ceSAkeem G Abodunrin 	u16 ethtype;			/* Ethernet protocol for pause frame */
253d95276ceSAkeem G Abodunrin 
254d76a60baSAnirudh Venkataramanan 	/* RSS config */
255d76a60baSAnirudh Venkataramanan 	u16 rss_table_size;	/* HW RSS table size */
256d76a60baSAnirudh Venkataramanan 	u16 rss_size;		/* Allocated RSS queues */
257d76a60baSAnirudh Venkataramanan 	u8 *rss_hkey_user;	/* User configured hash keys */
258d76a60baSAnirudh Venkataramanan 	u8 *rss_lut_user;	/* User configured lookup table entries */
259d76a60baSAnirudh Venkataramanan 	u8 rss_lut_type;	/* used to configure Get/Set RSS LUT AQ call */
260d76a60baSAnirudh Venkataramanan 
261cdedef59SAnirudh Venkataramanan 	u16 max_frame;
262cdedef59SAnirudh Venkataramanan 	u16 rx_buf_len;
263cdedef59SAnirudh Venkataramanan 
2643a858ba3SAnirudh Venkataramanan 	struct ice_aqc_vsi_props info;	 /* VSI properties */
2653a858ba3SAnirudh Venkataramanan 
266fcea6f3dSAnirudh Venkataramanan 	/* VSI stats */
267fcea6f3dSAnirudh Venkataramanan 	struct rtnl_link_stats64 net_stats;
268fcea6f3dSAnirudh Venkataramanan 	struct ice_eth_stats eth_stats;
269fcea6f3dSAnirudh Venkataramanan 	struct ice_eth_stats eth_stats_prev;
270fcea6f3dSAnirudh Venkataramanan 
271e94d4478SAnirudh Venkataramanan 	struct list_head tmp_sync_list;		/* MAC filters to be synced */
272e94d4478SAnirudh Venkataramanan 	struct list_head tmp_unsync_list;	/* MAC filters to be unsynced */
273e94d4478SAnirudh Venkataramanan 
2740ab54c5fSJesse Brandeburg 	u8 irqs_ready:1;
2750ab54c5fSJesse Brandeburg 	u8 current_isup:1;		 /* Sync 'link up' logging */
2760ab54c5fSJesse Brandeburg 	u8 stat_offsets_loaded:1;
2770ab54c5fSJesse Brandeburg 	u8 vlan_ena:1;
278cdedef59SAnirudh Venkataramanan 
2793a858ba3SAnirudh Venkataramanan 	/* queue information */
2803a858ba3SAnirudh Venkataramanan 	u8 tx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */
2813a858ba3SAnirudh Venkataramanan 	u8 rx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */
28278b5713aSAnirudh Venkataramanan 	u16 *txq_map;			 /* index in pf->avail_txqs */
28378b5713aSAnirudh Venkataramanan 	u16 *rxq_map;			 /* index in pf->avail_rxqs */
2843a858ba3SAnirudh Venkataramanan 	u16 alloc_txq;			 /* Allocated Tx queues */
2853a858ba3SAnirudh Venkataramanan 	u16 num_txq;			 /* Used Tx queues */
2863a858ba3SAnirudh Venkataramanan 	u16 alloc_rxq;			 /* Allocated Rx queues */
2873a858ba3SAnirudh Venkataramanan 	u16 num_rxq;			 /* Used Rx queues */
288ad71b256SBrett Creeley 	u16 num_rx_desc;
289ad71b256SBrett Creeley 	u16 num_tx_desc;
2903a858ba3SAnirudh Venkataramanan 	struct ice_tc_cfg tc_cfg;
2913a858ba3SAnirudh Venkataramanan } ____cacheline_internodealigned_in_smp;
2923a858ba3SAnirudh Venkataramanan 
2933a858ba3SAnirudh Venkataramanan /* struct that defines an interrupt vector */
2943a858ba3SAnirudh Venkataramanan struct ice_q_vector {
2953a858ba3SAnirudh Venkataramanan 	struct ice_vsi *vsi;
2968244dd2dSBrett Creeley 
2973a858ba3SAnirudh Venkataramanan 	u16 v_idx;			/* index in the vsi->q_vector array. */
298b07833a0SBrett Creeley 	u16 reg_idx;
299d337f2afSAnirudh Venkataramanan 	u8 num_ring_rx;			/* total number of Rx rings in vector */
3008244dd2dSBrett Creeley 	u8 num_ring_tx;			/* total number of Tx rings in vector */
3018244dd2dSBrett Creeley 	u8 itr_countdown;		/* when 0 should adjust adaptive ITR */
3029e4ab4c2SBrett Creeley 	/* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
3039e4ab4c2SBrett Creeley 	 * value to the device
3049e4ab4c2SBrett Creeley 	 */
3059e4ab4c2SBrett Creeley 	u8 intrl;
3068244dd2dSBrett Creeley 
3078244dd2dSBrett Creeley 	struct napi_struct napi;
3088244dd2dSBrett Creeley 
3098244dd2dSBrett Creeley 	struct ice_ring_container rx;
3108244dd2dSBrett Creeley 	struct ice_ring_container tx;
3118244dd2dSBrett Creeley 
3128244dd2dSBrett Creeley 	cpumask_t affinity_mask;
3138244dd2dSBrett Creeley 	struct irq_affinity_notify affinity_notify;
3148244dd2dSBrett Creeley 
3158244dd2dSBrett Creeley 	char name[ICE_INT_NAME_STR_LEN];
316940b61afSAnirudh Venkataramanan } ____cacheline_internodealigned_in_smp;
317940b61afSAnirudh Venkataramanan 
318940b61afSAnirudh Venkataramanan enum ice_pf_flags {
319940b61afSAnirudh Venkataramanan 	ICE_FLAG_FLTR_SYNC,
320940b61afSAnirudh Venkataramanan 	ICE_FLAG_RSS_ENA,
321ddf30f7fSAnirudh Venkataramanan 	ICE_FLAG_SRIOV_ENA,
32275d2b253SAnirudh Venkataramanan 	ICE_FLAG_SRIOV_CAPABLE,
32337b6f646SAnirudh Venkataramanan 	ICE_FLAG_DCB_CAPABLE,
32437b6f646SAnirudh Venkataramanan 	ICE_FLAG_DCB_ENA,
325ab4ab73fSBruce Allan 	ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
3266d599946STony Nguyen 	ICE_FLAG_NO_MEDIA,
32784a118abSDave Ertman 	ICE_FLAG_FW_LLDP_AGENT,
3283a257a14SAnirudh Venkataramanan 	ICE_FLAG_ETHTOOL_CTXT,		/* set when ethtool holds RTNL lock */
329940b61afSAnirudh Venkataramanan 	ICE_PF_FLAGS_NBITS		/* must be last */
330940b61afSAnirudh Venkataramanan };
331940b61afSAnirudh Venkataramanan 
332837f08fdSAnirudh Venkataramanan struct ice_pf {
333837f08fdSAnirudh Venkataramanan 	struct pci_dev *pdev;
334eb0208ecSPreethi Banala 
335eb0208ecSPreethi Banala 	/* OS reserved IRQ details */
336940b61afSAnirudh Venkataramanan 	struct msix_entry *msix_entries;
337cbe66bfeSBrett Creeley 	struct ice_res_tracker *irq_tracker;
338cbe66bfeSBrett Creeley 	/* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the
339cbe66bfeSBrett Creeley 	 * number of MSIX vectors needed for all SR-IOV VFs from the number of
340cbe66bfeSBrett Creeley 	 * MSIX vectors allowed on this PF.
341cbe66bfeSBrett Creeley 	 */
342cbe66bfeSBrett Creeley 	u16 sriov_base_vector;
343eb0208ecSPreethi Banala 
344940b61afSAnirudh Venkataramanan 	struct ice_vsi **vsi;		/* VSIs created by the driver */
345940b61afSAnirudh Venkataramanan 	struct ice_sw *first_sw;	/* first switch created by firmware */
346ddf30f7fSAnirudh Venkataramanan 	/* Virtchnl/SR-IOV config info */
347ddf30f7fSAnirudh Venkataramanan 	struct ice_vf *vf;
348ddf30f7fSAnirudh Venkataramanan 	int num_alloc_vfs;		/* actual number of VFs allocated */
34975d2b253SAnirudh Venkataramanan 	u16 num_vfs_supported;		/* num VFs supported for this PF */
350ddf30f7fSAnirudh Venkataramanan 	u16 num_vf_qps;			/* num queue pairs per VF */
351ddf30f7fSAnirudh Venkataramanan 	u16 num_vf_msix;		/* num vectors per VF */
352837f08fdSAnirudh Venkataramanan 	DECLARE_BITMAP(state, __ICE_STATE_NBITS);
353940b61afSAnirudh Venkataramanan 	DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
35478b5713aSAnirudh Venkataramanan 	unsigned long *avail_txqs;	/* bitmap to track PF Tx queue usage */
35578b5713aSAnirudh Venkataramanan 	unsigned long *avail_rxqs;	/* bitmap to track PF Rx queue usage */
356940b61afSAnirudh Venkataramanan 	unsigned long serv_tmr_period;
357940b61afSAnirudh Venkataramanan 	unsigned long serv_tmr_prev;
358940b61afSAnirudh Venkataramanan 	struct timer_list serv_tmr;
359940b61afSAnirudh Venkataramanan 	struct work_struct serv_task;
360940b61afSAnirudh Venkataramanan 	struct mutex avail_q_mutex;	/* protects access to avail_[rx|tx]qs */
361940b61afSAnirudh Venkataramanan 	struct mutex sw_mutex;		/* lock for protecting VSI alloc flow */
362837f08fdSAnirudh Venkataramanan 	u32 msg_enable;
363d76a60baSAnirudh Venkataramanan 	u32 hw_csum_rx_error;
364cbe66bfeSBrett Creeley 	u32 oicr_idx;		/* Other interrupt cause MSIX vector index */
365eb0208ecSPreethi Banala 	u32 num_avail_sw_msix;	/* remaining MSIX SW vectors left unclaimed */
36678b5713aSAnirudh Venkataramanan 	u16 max_pf_txqs;	/* Total Tx queues PF wide */
36778b5713aSAnirudh Venkataramanan 	u16 max_pf_rxqs;	/* Total Rx queues PF wide */
368940b61afSAnirudh Venkataramanan 	u32 num_lan_msix;	/* Total MSIX vectors for base driver */
369f9867df6SAnirudh Venkataramanan 	u16 num_lan_tx;		/* num LAN Tx queues setup */
370f9867df6SAnirudh Venkataramanan 	u16 num_lan_rx;		/* num LAN Rx queues setup */
371940b61afSAnirudh Venkataramanan 	u16 next_vsi;		/* Next free slot in pf->vsi[] - 0-based! */
372940b61afSAnirudh Venkataramanan 	u16 num_alloc_vsi;
3730b28b702SAnirudh Venkataramanan 	u16 corer_count;	/* Core reset count */
3740b28b702SAnirudh Venkataramanan 	u16 globr_count;	/* Global reset count */
3750b28b702SAnirudh Venkataramanan 	u16 empr_count;		/* EMP reset count */
3760b28b702SAnirudh Venkataramanan 	u16 pfr_count;		/* PF reset count */
3770b28b702SAnirudh Venkataramanan 
378fcea6f3dSAnirudh Venkataramanan 	struct ice_hw_port_stats stats;
379fcea6f3dSAnirudh Venkataramanan 	struct ice_hw_port_stats stats_prev;
380837f08fdSAnirudh Venkataramanan 	struct ice_hw hw;
3810ab54c5fSJesse Brandeburg 	u8 stat_prev_loaded:1; /* has previous stats been loaded */
3827b9ffc76SAnirudh Venkataramanan #ifdef CONFIG_DCB
3837b9ffc76SAnirudh Venkataramanan 	u16 dcbx_cap;
3847b9ffc76SAnirudh Venkataramanan #endif /* CONFIG_DCB */
385b3969fd7SSudheer Mogilappagari 	u32 tx_timeout_count;
386b3969fd7SSudheer Mogilappagari 	unsigned long tx_timeout_last_recovery;
387b3969fd7SSudheer Mogilappagari 	u32 tx_timeout_recovery_level;
388940b61afSAnirudh Venkataramanan 	char int_name[ICE_INT_NAME_STR_LEN];
3890e674aebSAnirudh Venkataramanan 	u32 sw_int_count;
390837f08fdSAnirudh Venkataramanan };
391940b61afSAnirudh Venkataramanan 
3923a858ba3SAnirudh Venkataramanan struct ice_netdev_priv {
3933a858ba3SAnirudh Venkataramanan 	struct ice_vsi *vsi;
3943a858ba3SAnirudh Venkataramanan };
3953a858ba3SAnirudh Venkataramanan 
396940b61afSAnirudh Venkataramanan /**
397940b61afSAnirudh Venkataramanan  * ice_irq_dynamic_ena - Enable default interrupt generation settings
398f9867df6SAnirudh Venkataramanan  * @hw: pointer to HW struct
399f9867df6SAnirudh Venkataramanan  * @vsi: pointer to VSI struct, can be NULL
400cdedef59SAnirudh Venkataramanan  * @q_vector: pointer to q_vector, can be NULL
401940b61afSAnirudh Venkataramanan  */
402c8b7abddSBruce Allan static inline void
403c8b7abddSBruce Allan ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
404cdedef59SAnirudh Venkataramanan 		    struct ice_q_vector *q_vector)
405940b61afSAnirudh Venkataramanan {
406b07833a0SBrett Creeley 	u32 vector = (vsi && q_vector) ? q_vector->reg_idx :
407cbe66bfeSBrett Creeley 				((struct ice_pf *)hw->back)->oicr_idx;
408940b61afSAnirudh Venkataramanan 	int itr = ICE_ITR_NONE;
409940b61afSAnirudh Venkataramanan 	u32 val;
410940b61afSAnirudh Venkataramanan 
411940b61afSAnirudh Venkataramanan 	/* clear the PBA here, as this function is meant to clean out all
412940b61afSAnirudh Venkataramanan 	 * previous interrupts and enable the interrupt
413940b61afSAnirudh Venkataramanan 	 */
414940b61afSAnirudh Venkataramanan 	val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
415940b61afSAnirudh Venkataramanan 	      (itr << GLINT_DYN_CTL_ITR_INDX_S);
416cdedef59SAnirudh Venkataramanan 	if (vsi)
417cdedef59SAnirudh Venkataramanan 		if (test_bit(__ICE_DOWN, vsi->state))
418cdedef59SAnirudh Venkataramanan 			return;
419940b61afSAnirudh Venkataramanan 	wr32(hw, GLINT_DYN_CTL(vector), val);
420940b61afSAnirudh Venkataramanan }
421cdedef59SAnirudh Venkataramanan 
422c2a23e00SBrett Creeley /**
423208ff751SAnirudh Venkataramanan  * ice_get_main_vsi - Get the PF VSI
424208ff751SAnirudh Venkataramanan  * @pf: PF instance
425208ff751SAnirudh Venkataramanan  *
426208ff751SAnirudh Venkataramanan  * returns pf->vsi[0], which by definition is the PF VSI
427c2a23e00SBrett Creeley  */
428208ff751SAnirudh Venkataramanan static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf)
429c2a23e00SBrett Creeley {
430208ff751SAnirudh Venkataramanan 	if (pf->vsi)
431208ff751SAnirudh Venkataramanan 		return pf->vsi[0];
432c2a23e00SBrett Creeley 
433c2a23e00SBrett Creeley 	return NULL;
434c2a23e00SBrett Creeley }
435c2a23e00SBrett Creeley 
4360e674aebSAnirudh Venkataramanan int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);
4370e674aebSAnirudh Venkataramanan int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);
438fcea6f3dSAnirudh Venkataramanan void ice_set_ethtool_ops(struct net_device *netdev);
439*8c243700SAnirudh Venkataramanan u16 ice_get_avail_txq_count(struct ice_pf *pf);
440*8c243700SAnirudh Venkataramanan u16 ice_get_avail_rxq_count(struct ice_pf *pf);
4415a4a8673SBruce Allan void ice_update_vsi_stats(struct ice_vsi *vsi);
4425a4a8673SBruce Allan void ice_update_pf_stats(struct ice_pf *pf);
443fcea6f3dSAnirudh Venkataramanan int ice_up(struct ice_vsi *vsi);
444fcea6f3dSAnirudh Venkataramanan int ice_down(struct ice_vsi *vsi);
4450e674aebSAnirudh Venkataramanan int ice_vsi_cfg(struct ice_vsi *vsi);
4460e674aebSAnirudh Venkataramanan struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi);
447d76a60baSAnirudh Venkataramanan int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
448d76a60baSAnirudh Venkataramanan int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
449d76a60baSAnirudh Venkataramanan void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
450fcea6f3dSAnirudh Venkataramanan void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
4517b9ffc76SAnirudh Venkataramanan #ifdef CONFIG_DCB
4527b9ffc76SAnirudh Venkataramanan int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked);
4537b9ffc76SAnirudh Venkataramanan void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked);
4547b9ffc76SAnirudh Venkataramanan #endif /* CONFIG_DCB */
4550e674aebSAnirudh Venkataramanan int ice_open(struct net_device *netdev);
4560e674aebSAnirudh Venkataramanan int ice_stop(struct net_device *netdev);
457d76a60baSAnirudh Venkataramanan 
458837f08fdSAnirudh Venkataramanan #endif /* _ICE_H_ */
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