1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 #ifndef _E1000E_PHY_H_ 24 #define _E1000E_PHY_H_ 25 26 s32 e1000e_check_downshift(struct e1000_hw *hw); 27 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 28 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 29 s32 e1000_check_polarity_ife(struct e1000_hw *hw); 30 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 31 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 32 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 33 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 34 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 35 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 36 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 37 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 38 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); 39 s32 e1000e_get_phy_id(struct e1000_hw *hw); 40 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 41 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 42 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 43 s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 44 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 45 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 46 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 47 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 48 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 49 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 50 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 51 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 52 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 53 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 54 s32 e1000e_setup_copper_link(struct e1000_hw *hw); 55 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 56 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 57 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 58 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 59 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 60 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 61 u32 usec_interval, bool *success); 62 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 63 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 64 s32 e1000e_determine_phy_address(struct e1000_hw *hw); 65 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 66 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 67 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 68 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 69 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 70 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 71 void e1000_power_up_phy_copper(struct e1000_hw *hw); 72 void e1000_power_down_phy_copper(struct e1000_hw *hw); 73 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 74 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 75 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 76 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 77 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 78 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 79 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 80 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 81 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 82 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 83 s32 e1000_check_polarity_82577(struct e1000_hw *hw); 84 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 85 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 86 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 87 88 #define E1000_MAX_PHY_ADDR 8 89 90 /* IGP01E1000 Specific Registers */ 91 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 92 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 93 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 94 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 95 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 96 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 97 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 98 #define IGP_PAGE_SHIFT 5 99 #define PHY_REG_MASK 0x1F 100 101 /* BM/HV Specific Registers */ 102 #define BM_PORT_CTRL_PAGE 769 103 #define BM_WUC_PAGE 800 104 #define BM_WUC_ADDRESS_OPCODE 0x11 105 #define BM_WUC_DATA_OPCODE 0x12 106 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 107 #define BM_WUC_ENABLE_REG 17 108 #define BM_WUC_ENABLE_BIT BIT(2) 109 #define BM_WUC_HOST_WU_BIT BIT(4) 110 #define BM_WUC_ME_WU_BIT BIT(5) 111 112 #define PHY_UPPER_SHIFT 21 113 #define BM_PHY_REG(page, reg) \ 114 (((reg) & MAX_PHY_REG_ADDRESS) |\ 115 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 116 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 117 #define BM_PHY_REG_PAGE(offset) \ 118 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 119 #define BM_PHY_REG_NUM(offset) \ 120 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 121 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 122 ~MAX_PHY_REG_ADDRESS))) 123 124 #define HV_INTC_FC_PAGE_START 768 125 #define I82578_ADDR_REG 29 126 #define I82577_ADDR_REG 16 127 #define I82577_CFG_REG 22 128 #define I82577_CFG_ASSERT_CRS_ON_TX BIT(15) 129 #define I82577_CFG_ENABLE_DOWNSHIFT (3u << 10) /* auto downshift */ 130 #define I82577_CTRL_REG 23 131 132 /* 82577 specific PHY registers */ 133 #define I82577_PHY_CTRL_2 18 134 #define I82577_PHY_LBK_CTRL 19 135 #define I82577_PHY_STATUS_2 26 136 #define I82577_PHY_DIAG_STATUS 31 137 138 /* I82577 PHY Status 2 */ 139 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 140 #define I82577_PHY_STATUS2_MDIX 0x0800 141 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 142 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 143 144 /* I82577 PHY Control 2 */ 145 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 146 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 147 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 148 149 /* I82577 PHY Diagnostics Status */ 150 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 151 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 152 153 /* BM PHY Copper Specific Control 1 */ 154 #define BM_CS_CTRL1 16 155 156 /* BM PHY Copper Specific Status */ 157 #define BM_CS_STATUS 17 158 #define BM_CS_STATUS_LINK_UP 0x0400 159 #define BM_CS_STATUS_RESOLVED 0x0800 160 #define BM_CS_STATUS_SPEED_MASK 0xC000 161 #define BM_CS_STATUS_SPEED_1000 0x8000 162 163 /* 82577 Mobile Phy Status Register */ 164 #define HV_M_STATUS 26 165 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 166 #define HV_M_STATUS_SPEED_MASK 0x0300 167 #define HV_M_STATUS_SPEED_1000 0x0200 168 #define HV_M_STATUS_SPEED_100 0x0100 169 #define HV_M_STATUS_LINK_UP 0x0040 170 171 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 172 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 173 174 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 175 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 176 177 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 178 179 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 180 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 181 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 182 183 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 184 185 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 186 #define IGP01E1000_PSSR_MDIX 0x0800 187 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 188 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 189 190 #define IGP02E1000_PHY_CHANNEL_NUM 4 191 #define IGP02E1000_PHY_AGC_A 0x11B1 192 #define IGP02E1000_PHY_AGC_B 0x12B1 193 #define IGP02E1000_PHY_AGC_C 0x14B1 194 #define IGP02E1000_PHY_AGC_D 0x18B1 195 196 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 197 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 198 #define IGP02E1000_AGC_RANGE 15 199 200 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 201 202 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 203 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 204 #define E1000_KMRNCTRLSTA_REN 0x00200000 205 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 206 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 207 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 208 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 209 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 210 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 211 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 212 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 213 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 214 215 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 216 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 217 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 218 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 219 220 /* IFE PHY Extended Status Control */ 221 #define IFE_PESC_POLARITY_REVERSED 0x0100 222 223 /* IFE PHY Special Control */ 224 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 225 #define IFE_PSC_FORCE_POLARITY 0x0020 226 227 /* IFE PHY Special Control and LED Control */ 228 #define IFE_PSCL_PROBE_MODE 0x0020 229 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 230 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 231 232 /* IFE PHY MDIX Control */ 233 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 234 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 235 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 236 237 #endif 238