1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3948f97acSBruce Allan 4948f97acSBruce Allan #ifndef _E1000E_MANAGE_H_ 5948f97acSBruce Allan #define _E1000E_MANAGE_H_ 6948f97acSBruce Allan 7948f97acSBruce Allan bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 8948f97acSBruce Allan bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 9948f97acSBruce Allan s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 10948f97acSBruce Allan bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 11948f97acSBruce Allan 12948f97acSBruce Allan enum e1000_mng_mode { 13948f97acSBruce Allan e1000_mng_mode_none = 0, 14948f97acSBruce Allan e1000_mng_mode_asf, 15948f97acSBruce Allan e1000_mng_mode_pt, 16948f97acSBruce Allan e1000_mng_mode_ipmi, 17948f97acSBruce Allan e1000_mng_mode_host_if_only 18948f97acSBruce Allan }; 19948f97acSBruce Allan 20948f97acSBruce Allan #define E1000_FACTPS_MNGCG 0x20000000 21948f97acSBruce Allan 22948f97acSBruce Allan #define E1000_FWSM_MODE_MASK 0xE 23948f97acSBruce Allan #define E1000_FWSM_MODE_SHIFT 1 24948f97acSBruce Allan 25948f97acSBruce Allan #define E1000_MNG_IAMT_MODE 0x3 26948f97acSBruce Allan #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 27948f97acSBruce Allan #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 28948f97acSBruce Allan #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 29948f97acSBruce Allan #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 30948f97acSBruce Allan #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 31948f97acSBruce Allan #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 32948f97acSBruce Allan 33948f97acSBruce Allan #define E1000_VFTA_ENTRY_SHIFT 5 34948f97acSBruce Allan #define E1000_VFTA_ENTRY_MASK 0x7F 35948f97acSBruce Allan #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 36948f97acSBruce Allan 37948f97acSBruce Allan #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 38948f97acSBruce Allan /* Driver sets this bit when done to put command in RAM */ 39948f97acSBruce Allan #define E1000_HICR_C 0x02 40948f97acSBruce Allan #define E1000_HICR_SV 0x04 /* Status Validity */ 41948f97acSBruce Allan #define E1000_HICR_FW_RESET_ENABLE 0x40 42948f97acSBruce Allan #define E1000_HICR_FW_RESET 0x80 43948f97acSBruce Allan 44948f97acSBruce Allan /* Intel(R) Active Management Technology signature */ 45948f97acSBruce Allan #define E1000_IAMT_SIGNATURE 0x544D4149 46948f97acSBruce Allan 47948f97acSBruce Allan #endif 48