1*dee1ad47SJeff Kirsher /******************************************************************************* 2*dee1ad47SJeff Kirsher 3*dee1ad47SJeff Kirsher Intel PRO/1000 Linux driver 4*dee1ad47SJeff Kirsher Copyright(c) 1999 - 2011 Intel Corporation. 5*dee1ad47SJeff Kirsher 6*dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7*dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8*dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9*dee1ad47SJeff Kirsher 10*dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11*dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*dee1ad47SJeff Kirsher more details. 14*dee1ad47SJeff Kirsher 15*dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16*dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17*dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18*dee1ad47SJeff Kirsher 19*dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20*dee1ad47SJeff Kirsher the file called "COPYING". 21*dee1ad47SJeff Kirsher 22*dee1ad47SJeff Kirsher Contact Information: 23*dee1ad47SJeff Kirsher Linux NICS <linux.nics@intel.com> 24*dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25*dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26*dee1ad47SJeff Kirsher 27*dee1ad47SJeff Kirsher *******************************************************************************/ 28*dee1ad47SJeff Kirsher 29*dee1ad47SJeff Kirsher /* Linux PRO/1000 Ethernet Driver main header file */ 30*dee1ad47SJeff Kirsher 31*dee1ad47SJeff Kirsher #ifndef _E1000_H_ 32*dee1ad47SJeff Kirsher #define _E1000_H_ 33*dee1ad47SJeff Kirsher 34*dee1ad47SJeff Kirsher #include <linux/bitops.h> 35*dee1ad47SJeff Kirsher #include <linux/types.h> 36*dee1ad47SJeff Kirsher #include <linux/timer.h> 37*dee1ad47SJeff Kirsher #include <linux/workqueue.h> 38*dee1ad47SJeff Kirsher #include <linux/io.h> 39*dee1ad47SJeff Kirsher #include <linux/netdevice.h> 40*dee1ad47SJeff Kirsher #include <linux/pci.h> 41*dee1ad47SJeff Kirsher #include <linux/pci-aspm.h> 42*dee1ad47SJeff Kirsher #include <linux/crc32.h> 43*dee1ad47SJeff Kirsher #include <linux/if_vlan.h> 44*dee1ad47SJeff Kirsher 45*dee1ad47SJeff Kirsher #include "hw.h" 46*dee1ad47SJeff Kirsher 47*dee1ad47SJeff Kirsher struct e1000_info; 48*dee1ad47SJeff Kirsher 49*dee1ad47SJeff Kirsher #define e_dbg(format, arg...) \ 50*dee1ad47SJeff Kirsher netdev_dbg(hw->adapter->netdev, format, ## arg) 51*dee1ad47SJeff Kirsher #define e_err(format, arg...) \ 52*dee1ad47SJeff Kirsher netdev_err(adapter->netdev, format, ## arg) 53*dee1ad47SJeff Kirsher #define e_info(format, arg...) \ 54*dee1ad47SJeff Kirsher netdev_info(adapter->netdev, format, ## arg) 55*dee1ad47SJeff Kirsher #define e_warn(format, arg...) \ 56*dee1ad47SJeff Kirsher netdev_warn(adapter->netdev, format, ## arg) 57*dee1ad47SJeff Kirsher #define e_notice(format, arg...) \ 58*dee1ad47SJeff Kirsher netdev_notice(adapter->netdev, format, ## arg) 59*dee1ad47SJeff Kirsher 60*dee1ad47SJeff Kirsher 61*dee1ad47SJeff Kirsher /* Interrupt modes, as used by the IntMode parameter */ 62*dee1ad47SJeff Kirsher #define E1000E_INT_MODE_LEGACY 0 63*dee1ad47SJeff Kirsher #define E1000E_INT_MODE_MSI 1 64*dee1ad47SJeff Kirsher #define E1000E_INT_MODE_MSIX 2 65*dee1ad47SJeff Kirsher 66*dee1ad47SJeff Kirsher /* Tx/Rx descriptor defines */ 67*dee1ad47SJeff Kirsher #define E1000_DEFAULT_TXD 256 68*dee1ad47SJeff Kirsher #define E1000_MAX_TXD 4096 69*dee1ad47SJeff Kirsher #define E1000_MIN_TXD 64 70*dee1ad47SJeff Kirsher 71*dee1ad47SJeff Kirsher #define E1000_DEFAULT_RXD 256 72*dee1ad47SJeff Kirsher #define E1000_MAX_RXD 4096 73*dee1ad47SJeff Kirsher #define E1000_MIN_RXD 64 74*dee1ad47SJeff Kirsher 75*dee1ad47SJeff Kirsher #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 76*dee1ad47SJeff Kirsher #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 77*dee1ad47SJeff Kirsher 78*dee1ad47SJeff Kirsher /* Early Receive defines */ 79*dee1ad47SJeff Kirsher #define E1000_ERT_2048 0x100 80*dee1ad47SJeff Kirsher 81*dee1ad47SJeff Kirsher #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 82*dee1ad47SJeff Kirsher 83*dee1ad47SJeff Kirsher /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 84*dee1ad47SJeff Kirsher /* How many Rx Buffers do we bundle into one write to the hardware ? */ 85*dee1ad47SJeff Kirsher #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 86*dee1ad47SJeff Kirsher 87*dee1ad47SJeff Kirsher #define AUTO_ALL_MODES 0 88*dee1ad47SJeff Kirsher #define E1000_EEPROM_APME 0x0400 89*dee1ad47SJeff Kirsher 90*dee1ad47SJeff Kirsher #define E1000_MNG_VLAN_NONE (-1) 91*dee1ad47SJeff Kirsher 92*dee1ad47SJeff Kirsher /* Number of packet split data buffers (not including the header buffer) */ 93*dee1ad47SJeff Kirsher #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 94*dee1ad47SJeff Kirsher 95*dee1ad47SJeff Kirsher #define DEFAULT_JUMBO 9234 96*dee1ad47SJeff Kirsher 97*dee1ad47SJeff Kirsher /* BM/HV Specific Registers */ 98*dee1ad47SJeff Kirsher #define BM_PORT_CTRL_PAGE 769 99*dee1ad47SJeff Kirsher 100*dee1ad47SJeff Kirsher #define PHY_UPPER_SHIFT 21 101*dee1ad47SJeff Kirsher #define BM_PHY_REG(page, reg) \ 102*dee1ad47SJeff Kirsher (((reg) & MAX_PHY_REG_ADDRESS) |\ 103*dee1ad47SJeff Kirsher (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 104*dee1ad47SJeff Kirsher (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 105*dee1ad47SJeff Kirsher 106*dee1ad47SJeff Kirsher /* PHY Wakeup Registers and defines */ 107*dee1ad47SJeff Kirsher #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 108*dee1ad47SJeff Kirsher #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 109*dee1ad47SJeff Kirsher #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 110*dee1ad47SJeff Kirsher #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 111*dee1ad47SJeff Kirsher #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 112*dee1ad47SJeff Kirsher #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 113*dee1ad47SJeff Kirsher #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 114*dee1ad47SJeff Kirsher #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 115*dee1ad47SJeff Kirsher #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 116*dee1ad47SJeff Kirsher #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 117*dee1ad47SJeff Kirsher 118*dee1ad47SJeff Kirsher #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 119*dee1ad47SJeff Kirsher #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 120*dee1ad47SJeff Kirsher #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 121*dee1ad47SJeff Kirsher #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 122*dee1ad47SJeff Kirsher #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 123*dee1ad47SJeff Kirsher #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 124*dee1ad47SJeff Kirsher #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 125*dee1ad47SJeff Kirsher 126*dee1ad47SJeff Kirsher #define HV_STATS_PAGE 778 127*dee1ad47SJeff Kirsher #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ 128*dee1ad47SJeff Kirsher #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 129*dee1ad47SJeff Kirsher #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ 130*dee1ad47SJeff Kirsher #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 131*dee1ad47SJeff Kirsher #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ 132*dee1ad47SJeff Kirsher #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 133*dee1ad47SJeff Kirsher #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ 134*dee1ad47SJeff Kirsher #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 135*dee1ad47SJeff Kirsher #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ 136*dee1ad47SJeff Kirsher #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 137*dee1ad47SJeff Kirsher #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 138*dee1ad47SJeff Kirsher #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 139*dee1ad47SJeff Kirsher #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ 140*dee1ad47SJeff Kirsher #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 141*dee1ad47SJeff Kirsher 142*dee1ad47SJeff Kirsher #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 143*dee1ad47SJeff Kirsher 144*dee1ad47SJeff Kirsher /* BM PHY Copper Specific Status */ 145*dee1ad47SJeff Kirsher #define BM_CS_STATUS 17 146*dee1ad47SJeff Kirsher #define BM_CS_STATUS_LINK_UP 0x0400 147*dee1ad47SJeff Kirsher #define BM_CS_STATUS_RESOLVED 0x0800 148*dee1ad47SJeff Kirsher #define BM_CS_STATUS_SPEED_MASK 0xC000 149*dee1ad47SJeff Kirsher #define BM_CS_STATUS_SPEED_1000 0x8000 150*dee1ad47SJeff Kirsher 151*dee1ad47SJeff Kirsher /* 82577 Mobile Phy Status Register */ 152*dee1ad47SJeff Kirsher #define HV_M_STATUS 26 153*dee1ad47SJeff Kirsher #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 154*dee1ad47SJeff Kirsher #define HV_M_STATUS_SPEED_MASK 0x0300 155*dee1ad47SJeff Kirsher #define HV_M_STATUS_SPEED_1000 0x0200 156*dee1ad47SJeff Kirsher #define HV_M_STATUS_LINK_UP 0x0040 157*dee1ad47SJeff Kirsher 158*dee1ad47SJeff Kirsher /* Time to wait before putting the device into D3 if there's no link (in ms). */ 159*dee1ad47SJeff Kirsher #define LINK_TIMEOUT 100 160*dee1ad47SJeff Kirsher 161*dee1ad47SJeff Kirsher #define DEFAULT_RDTR 0 162*dee1ad47SJeff Kirsher #define DEFAULT_RADV 8 163*dee1ad47SJeff Kirsher #define BURST_RDTR 0x20 164*dee1ad47SJeff Kirsher #define BURST_RADV 0x20 165*dee1ad47SJeff Kirsher 166*dee1ad47SJeff Kirsher /* 167*dee1ad47SJeff Kirsher * in the case of WTHRESH, it appears at least the 82571/2 hardware 168*dee1ad47SJeff Kirsher * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 169*dee1ad47SJeff Kirsher * WTHRESH=4, and since we want 64 bytes at a time written back, set 170*dee1ad47SJeff Kirsher * it to 5 171*dee1ad47SJeff Kirsher */ 172*dee1ad47SJeff Kirsher #define E1000_TXDCTL_DMA_BURST_ENABLE \ 173*dee1ad47SJeff Kirsher (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 174*dee1ad47SJeff Kirsher E1000_TXDCTL_COUNT_DESC | \ 175*dee1ad47SJeff Kirsher (5 << 16) | /* wthresh must be +1 more than desired */\ 176*dee1ad47SJeff Kirsher (1 << 8) | /* hthresh */ \ 177*dee1ad47SJeff Kirsher 0x1f) /* pthresh */ 178*dee1ad47SJeff Kirsher 179*dee1ad47SJeff Kirsher #define E1000_RXDCTL_DMA_BURST_ENABLE \ 180*dee1ad47SJeff Kirsher (0x01000000 | /* set descriptor granularity */ \ 181*dee1ad47SJeff Kirsher (4 << 16) | /* set writeback threshold */ \ 182*dee1ad47SJeff Kirsher (4 << 8) | /* set prefetch threshold */ \ 183*dee1ad47SJeff Kirsher 0x20) /* set hthresh */ 184*dee1ad47SJeff Kirsher 185*dee1ad47SJeff Kirsher #define E1000_TIDV_FPD (1 << 31) 186*dee1ad47SJeff Kirsher #define E1000_RDTR_FPD (1 << 31) 187*dee1ad47SJeff Kirsher 188*dee1ad47SJeff Kirsher enum e1000_boards { 189*dee1ad47SJeff Kirsher board_82571, 190*dee1ad47SJeff Kirsher board_82572, 191*dee1ad47SJeff Kirsher board_82573, 192*dee1ad47SJeff Kirsher board_82574, 193*dee1ad47SJeff Kirsher board_82583, 194*dee1ad47SJeff Kirsher board_80003es2lan, 195*dee1ad47SJeff Kirsher board_ich8lan, 196*dee1ad47SJeff Kirsher board_ich9lan, 197*dee1ad47SJeff Kirsher board_ich10lan, 198*dee1ad47SJeff Kirsher board_pchlan, 199*dee1ad47SJeff Kirsher board_pch2lan, 200*dee1ad47SJeff Kirsher }; 201*dee1ad47SJeff Kirsher 202*dee1ad47SJeff Kirsher struct e1000_ps_page { 203*dee1ad47SJeff Kirsher struct page *page; 204*dee1ad47SJeff Kirsher u64 dma; /* must be u64 - written to hw */ 205*dee1ad47SJeff Kirsher }; 206*dee1ad47SJeff Kirsher 207*dee1ad47SJeff Kirsher /* 208*dee1ad47SJeff Kirsher * wrappers around a pointer to a socket buffer, 209*dee1ad47SJeff Kirsher * so a DMA handle can be stored along with the buffer 210*dee1ad47SJeff Kirsher */ 211*dee1ad47SJeff Kirsher struct e1000_buffer { 212*dee1ad47SJeff Kirsher dma_addr_t dma; 213*dee1ad47SJeff Kirsher struct sk_buff *skb; 214*dee1ad47SJeff Kirsher union { 215*dee1ad47SJeff Kirsher /* Tx */ 216*dee1ad47SJeff Kirsher struct { 217*dee1ad47SJeff Kirsher unsigned long time_stamp; 218*dee1ad47SJeff Kirsher u16 length; 219*dee1ad47SJeff Kirsher u16 next_to_watch; 220*dee1ad47SJeff Kirsher unsigned int segs; 221*dee1ad47SJeff Kirsher unsigned int bytecount; 222*dee1ad47SJeff Kirsher u16 mapped_as_page; 223*dee1ad47SJeff Kirsher }; 224*dee1ad47SJeff Kirsher /* Rx */ 225*dee1ad47SJeff Kirsher struct { 226*dee1ad47SJeff Kirsher /* arrays of page information for packet split */ 227*dee1ad47SJeff Kirsher struct e1000_ps_page *ps_pages; 228*dee1ad47SJeff Kirsher struct page *page; 229*dee1ad47SJeff Kirsher }; 230*dee1ad47SJeff Kirsher }; 231*dee1ad47SJeff Kirsher }; 232*dee1ad47SJeff Kirsher 233*dee1ad47SJeff Kirsher struct e1000_ring { 234*dee1ad47SJeff Kirsher void *desc; /* pointer to ring memory */ 235*dee1ad47SJeff Kirsher dma_addr_t dma; /* phys address of ring */ 236*dee1ad47SJeff Kirsher unsigned int size; /* length of ring in bytes */ 237*dee1ad47SJeff Kirsher unsigned int count; /* number of desc. in ring */ 238*dee1ad47SJeff Kirsher 239*dee1ad47SJeff Kirsher u16 next_to_use; 240*dee1ad47SJeff Kirsher u16 next_to_clean; 241*dee1ad47SJeff Kirsher 242*dee1ad47SJeff Kirsher u16 head; 243*dee1ad47SJeff Kirsher u16 tail; 244*dee1ad47SJeff Kirsher 245*dee1ad47SJeff Kirsher /* array of buffer information structs */ 246*dee1ad47SJeff Kirsher struct e1000_buffer *buffer_info; 247*dee1ad47SJeff Kirsher 248*dee1ad47SJeff Kirsher char name[IFNAMSIZ + 5]; 249*dee1ad47SJeff Kirsher u32 ims_val; 250*dee1ad47SJeff Kirsher u32 itr_val; 251*dee1ad47SJeff Kirsher u16 itr_register; 252*dee1ad47SJeff Kirsher int set_itr; 253*dee1ad47SJeff Kirsher 254*dee1ad47SJeff Kirsher struct sk_buff *rx_skb_top; 255*dee1ad47SJeff Kirsher }; 256*dee1ad47SJeff Kirsher 257*dee1ad47SJeff Kirsher /* PHY register snapshot values */ 258*dee1ad47SJeff Kirsher struct e1000_phy_regs { 259*dee1ad47SJeff Kirsher u16 bmcr; /* basic mode control register */ 260*dee1ad47SJeff Kirsher u16 bmsr; /* basic mode status register */ 261*dee1ad47SJeff Kirsher u16 advertise; /* auto-negotiation advertisement */ 262*dee1ad47SJeff Kirsher u16 lpa; /* link partner ability register */ 263*dee1ad47SJeff Kirsher u16 expansion; /* auto-negotiation expansion reg */ 264*dee1ad47SJeff Kirsher u16 ctrl1000; /* 1000BASE-T control register */ 265*dee1ad47SJeff Kirsher u16 stat1000; /* 1000BASE-T status register */ 266*dee1ad47SJeff Kirsher u16 estatus; /* extended status register */ 267*dee1ad47SJeff Kirsher }; 268*dee1ad47SJeff Kirsher 269*dee1ad47SJeff Kirsher /* board specific private data structure */ 270*dee1ad47SJeff Kirsher struct e1000_adapter { 271*dee1ad47SJeff Kirsher struct timer_list watchdog_timer; 272*dee1ad47SJeff Kirsher struct timer_list phy_info_timer; 273*dee1ad47SJeff Kirsher struct timer_list blink_timer; 274*dee1ad47SJeff Kirsher 275*dee1ad47SJeff Kirsher struct work_struct reset_task; 276*dee1ad47SJeff Kirsher struct work_struct watchdog_task; 277*dee1ad47SJeff Kirsher 278*dee1ad47SJeff Kirsher const struct e1000_info *ei; 279*dee1ad47SJeff Kirsher 280*dee1ad47SJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 281*dee1ad47SJeff Kirsher u32 bd_number; 282*dee1ad47SJeff Kirsher u32 rx_buffer_len; 283*dee1ad47SJeff Kirsher u16 mng_vlan_id; 284*dee1ad47SJeff Kirsher u16 link_speed; 285*dee1ad47SJeff Kirsher u16 link_duplex; 286*dee1ad47SJeff Kirsher u16 eeprom_vers; 287*dee1ad47SJeff Kirsher 288*dee1ad47SJeff Kirsher /* track device up/down/testing state */ 289*dee1ad47SJeff Kirsher unsigned long state; 290*dee1ad47SJeff Kirsher 291*dee1ad47SJeff Kirsher /* Interrupt Throttle Rate */ 292*dee1ad47SJeff Kirsher u32 itr; 293*dee1ad47SJeff Kirsher u32 itr_setting; 294*dee1ad47SJeff Kirsher u16 tx_itr; 295*dee1ad47SJeff Kirsher u16 rx_itr; 296*dee1ad47SJeff Kirsher 297*dee1ad47SJeff Kirsher /* 298*dee1ad47SJeff Kirsher * Tx 299*dee1ad47SJeff Kirsher */ 300*dee1ad47SJeff Kirsher struct e1000_ring *tx_ring /* One per active queue */ 301*dee1ad47SJeff Kirsher ____cacheline_aligned_in_smp; 302*dee1ad47SJeff Kirsher 303*dee1ad47SJeff Kirsher struct napi_struct napi; 304*dee1ad47SJeff Kirsher 305*dee1ad47SJeff Kirsher unsigned int restart_queue; 306*dee1ad47SJeff Kirsher u32 txd_cmd; 307*dee1ad47SJeff Kirsher 308*dee1ad47SJeff Kirsher bool detect_tx_hung; 309*dee1ad47SJeff Kirsher u8 tx_timeout_factor; 310*dee1ad47SJeff Kirsher 311*dee1ad47SJeff Kirsher u32 tx_int_delay; 312*dee1ad47SJeff Kirsher u32 tx_abs_int_delay; 313*dee1ad47SJeff Kirsher 314*dee1ad47SJeff Kirsher unsigned int total_tx_bytes; 315*dee1ad47SJeff Kirsher unsigned int total_tx_packets; 316*dee1ad47SJeff Kirsher unsigned int total_rx_bytes; 317*dee1ad47SJeff Kirsher unsigned int total_rx_packets; 318*dee1ad47SJeff Kirsher 319*dee1ad47SJeff Kirsher /* Tx stats */ 320*dee1ad47SJeff Kirsher u64 tpt_old; 321*dee1ad47SJeff Kirsher u64 colc_old; 322*dee1ad47SJeff Kirsher u32 gotc; 323*dee1ad47SJeff Kirsher u64 gotc_old; 324*dee1ad47SJeff Kirsher u32 tx_timeout_count; 325*dee1ad47SJeff Kirsher u32 tx_fifo_head; 326*dee1ad47SJeff Kirsher u32 tx_head_addr; 327*dee1ad47SJeff Kirsher u32 tx_fifo_size; 328*dee1ad47SJeff Kirsher u32 tx_dma_failed; 329*dee1ad47SJeff Kirsher 330*dee1ad47SJeff Kirsher /* 331*dee1ad47SJeff Kirsher * Rx 332*dee1ad47SJeff Kirsher */ 333*dee1ad47SJeff Kirsher bool (*clean_rx) (struct e1000_adapter *adapter, 334*dee1ad47SJeff Kirsher int *work_done, int work_to_do) 335*dee1ad47SJeff Kirsher ____cacheline_aligned_in_smp; 336*dee1ad47SJeff Kirsher void (*alloc_rx_buf) (struct e1000_adapter *adapter, 337*dee1ad47SJeff Kirsher int cleaned_count, gfp_t gfp); 338*dee1ad47SJeff Kirsher struct e1000_ring *rx_ring; 339*dee1ad47SJeff Kirsher 340*dee1ad47SJeff Kirsher u32 rx_int_delay; 341*dee1ad47SJeff Kirsher u32 rx_abs_int_delay; 342*dee1ad47SJeff Kirsher 343*dee1ad47SJeff Kirsher /* Rx stats */ 344*dee1ad47SJeff Kirsher u64 hw_csum_err; 345*dee1ad47SJeff Kirsher u64 hw_csum_good; 346*dee1ad47SJeff Kirsher u64 rx_hdr_split; 347*dee1ad47SJeff Kirsher u32 gorc; 348*dee1ad47SJeff Kirsher u64 gorc_old; 349*dee1ad47SJeff Kirsher u32 alloc_rx_buff_failed; 350*dee1ad47SJeff Kirsher u32 rx_dma_failed; 351*dee1ad47SJeff Kirsher 352*dee1ad47SJeff Kirsher unsigned int rx_ps_pages; 353*dee1ad47SJeff Kirsher u16 rx_ps_bsize0; 354*dee1ad47SJeff Kirsher u32 max_frame_size; 355*dee1ad47SJeff Kirsher u32 min_frame_size; 356*dee1ad47SJeff Kirsher 357*dee1ad47SJeff Kirsher /* OS defined structs */ 358*dee1ad47SJeff Kirsher struct net_device *netdev; 359*dee1ad47SJeff Kirsher struct pci_dev *pdev; 360*dee1ad47SJeff Kirsher 361*dee1ad47SJeff Kirsher /* structs defined in e1000_hw.h */ 362*dee1ad47SJeff Kirsher struct e1000_hw hw; 363*dee1ad47SJeff Kirsher 364*dee1ad47SJeff Kirsher spinlock_t stats64_lock; 365*dee1ad47SJeff Kirsher struct e1000_hw_stats stats; 366*dee1ad47SJeff Kirsher struct e1000_phy_info phy_info; 367*dee1ad47SJeff Kirsher struct e1000_phy_stats phy_stats; 368*dee1ad47SJeff Kirsher 369*dee1ad47SJeff Kirsher /* Snapshot of PHY registers */ 370*dee1ad47SJeff Kirsher struct e1000_phy_regs phy_regs; 371*dee1ad47SJeff Kirsher 372*dee1ad47SJeff Kirsher struct e1000_ring test_tx_ring; 373*dee1ad47SJeff Kirsher struct e1000_ring test_rx_ring; 374*dee1ad47SJeff Kirsher u32 test_icr; 375*dee1ad47SJeff Kirsher 376*dee1ad47SJeff Kirsher u32 msg_enable; 377*dee1ad47SJeff Kirsher unsigned int num_vectors; 378*dee1ad47SJeff Kirsher struct msix_entry *msix_entries; 379*dee1ad47SJeff Kirsher int int_mode; 380*dee1ad47SJeff Kirsher u32 eiac_mask; 381*dee1ad47SJeff Kirsher 382*dee1ad47SJeff Kirsher u32 eeprom_wol; 383*dee1ad47SJeff Kirsher u32 wol; 384*dee1ad47SJeff Kirsher u32 pba; 385*dee1ad47SJeff Kirsher u32 max_hw_frame_size; 386*dee1ad47SJeff Kirsher 387*dee1ad47SJeff Kirsher bool fc_autoneg; 388*dee1ad47SJeff Kirsher 389*dee1ad47SJeff Kirsher unsigned int flags; 390*dee1ad47SJeff Kirsher unsigned int flags2; 391*dee1ad47SJeff Kirsher struct work_struct downshift_task; 392*dee1ad47SJeff Kirsher struct work_struct update_phy_task; 393*dee1ad47SJeff Kirsher struct work_struct print_hang_task; 394*dee1ad47SJeff Kirsher 395*dee1ad47SJeff Kirsher bool idle_check; 396*dee1ad47SJeff Kirsher int phy_hang_count; 397*dee1ad47SJeff Kirsher }; 398*dee1ad47SJeff Kirsher 399*dee1ad47SJeff Kirsher struct e1000_info { 400*dee1ad47SJeff Kirsher enum e1000_mac_type mac; 401*dee1ad47SJeff Kirsher unsigned int flags; 402*dee1ad47SJeff Kirsher unsigned int flags2; 403*dee1ad47SJeff Kirsher u32 pba; 404*dee1ad47SJeff Kirsher u32 max_hw_frame_size; 405*dee1ad47SJeff Kirsher s32 (*get_variants)(struct e1000_adapter *); 406*dee1ad47SJeff Kirsher struct e1000_mac_operations *mac_ops; 407*dee1ad47SJeff Kirsher struct e1000_phy_operations *phy_ops; 408*dee1ad47SJeff Kirsher struct e1000_nvm_operations *nvm_ops; 409*dee1ad47SJeff Kirsher }; 410*dee1ad47SJeff Kirsher 411*dee1ad47SJeff Kirsher /* hardware capability, feature, and workaround flags */ 412*dee1ad47SJeff Kirsher #define FLAG_HAS_AMT (1 << 0) 413*dee1ad47SJeff Kirsher #define FLAG_HAS_FLASH (1 << 1) 414*dee1ad47SJeff Kirsher #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 415*dee1ad47SJeff Kirsher #define FLAG_HAS_WOL (1 << 3) 416*dee1ad47SJeff Kirsher #define FLAG_HAS_ERT (1 << 4) 417*dee1ad47SJeff Kirsher #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 418*dee1ad47SJeff Kirsher #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 419*dee1ad47SJeff Kirsher #define FLAG_HAS_JUMBO_FRAMES (1 << 7) 420*dee1ad47SJeff Kirsher #define FLAG_READ_ONLY_NVM (1 << 8) 421*dee1ad47SJeff Kirsher #define FLAG_IS_ICH (1 << 9) 422*dee1ad47SJeff Kirsher #define FLAG_HAS_MSIX (1 << 10) 423*dee1ad47SJeff Kirsher #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 424*dee1ad47SJeff Kirsher #define FLAG_IS_QUAD_PORT_A (1 << 12) 425*dee1ad47SJeff Kirsher #define FLAG_IS_QUAD_PORT (1 << 13) 426*dee1ad47SJeff Kirsher #define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) 427*dee1ad47SJeff Kirsher #define FLAG_APME_IN_WUC (1 << 15) 428*dee1ad47SJeff Kirsher #define FLAG_APME_IN_CTRL3 (1 << 16) 429*dee1ad47SJeff Kirsher #define FLAG_APME_CHECK_PORT_B (1 << 17) 430*dee1ad47SJeff Kirsher #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 431*dee1ad47SJeff Kirsher #define FLAG_NO_WAKE_UCAST (1 << 19) 432*dee1ad47SJeff Kirsher #define FLAG_MNG_PT_ENABLED (1 << 20) 433*dee1ad47SJeff Kirsher #define FLAG_RESET_OVERWRITES_LAA (1 << 21) 434*dee1ad47SJeff Kirsher #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 435*dee1ad47SJeff Kirsher #define FLAG_TARC_SET_BIT_ZERO (1 << 23) 436*dee1ad47SJeff Kirsher #define FLAG_RX_NEEDS_RESTART (1 << 24) 437*dee1ad47SJeff Kirsher #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 438*dee1ad47SJeff Kirsher #define FLAG_SMART_POWER_DOWN (1 << 26) 439*dee1ad47SJeff Kirsher #define FLAG_MSI_ENABLED (1 << 27) 440*dee1ad47SJeff Kirsher #define FLAG_RX_CSUM_ENABLED (1 << 28) 441*dee1ad47SJeff Kirsher #define FLAG_TSO_FORCE (1 << 29) 442*dee1ad47SJeff Kirsher #define FLAG_RX_RESTART_NOW (1 << 30) 443*dee1ad47SJeff Kirsher #define FLAG_MSI_TEST_FAILED (1 << 31) 444*dee1ad47SJeff Kirsher 445*dee1ad47SJeff Kirsher /* CRC Stripping defines */ 446*dee1ad47SJeff Kirsher #define FLAG2_CRC_STRIPPING (1 << 0) 447*dee1ad47SJeff Kirsher #define FLAG2_HAS_PHY_WAKEUP (1 << 1) 448*dee1ad47SJeff Kirsher #define FLAG2_IS_DISCARDING (1 << 2) 449*dee1ad47SJeff Kirsher #define FLAG2_DISABLE_ASPM_L1 (1 << 3) 450*dee1ad47SJeff Kirsher #define FLAG2_HAS_PHY_STATS (1 << 4) 451*dee1ad47SJeff Kirsher #define FLAG2_HAS_EEE (1 << 5) 452*dee1ad47SJeff Kirsher #define FLAG2_DMA_BURST (1 << 6) 453*dee1ad47SJeff Kirsher #define FLAG2_DISABLE_ASPM_L0S (1 << 7) 454*dee1ad47SJeff Kirsher #define FLAG2_DISABLE_AIM (1 << 8) 455*dee1ad47SJeff Kirsher #define FLAG2_CHECK_PHY_HANG (1 << 9) 456*dee1ad47SJeff Kirsher 457*dee1ad47SJeff Kirsher #define E1000_RX_DESC_PS(R, i) \ 458*dee1ad47SJeff Kirsher (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 459*dee1ad47SJeff Kirsher #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 460*dee1ad47SJeff Kirsher #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) 461*dee1ad47SJeff Kirsher #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 462*dee1ad47SJeff Kirsher #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 463*dee1ad47SJeff Kirsher 464*dee1ad47SJeff Kirsher enum e1000_state_t { 465*dee1ad47SJeff Kirsher __E1000_TESTING, 466*dee1ad47SJeff Kirsher __E1000_RESETTING, 467*dee1ad47SJeff Kirsher __E1000_DOWN 468*dee1ad47SJeff Kirsher }; 469*dee1ad47SJeff Kirsher 470*dee1ad47SJeff Kirsher enum latency_range { 471*dee1ad47SJeff Kirsher lowest_latency = 0, 472*dee1ad47SJeff Kirsher low_latency = 1, 473*dee1ad47SJeff Kirsher bulk_latency = 2, 474*dee1ad47SJeff Kirsher latency_invalid = 255 475*dee1ad47SJeff Kirsher }; 476*dee1ad47SJeff Kirsher 477*dee1ad47SJeff Kirsher extern char e1000e_driver_name[]; 478*dee1ad47SJeff Kirsher extern const char e1000e_driver_version[]; 479*dee1ad47SJeff Kirsher 480*dee1ad47SJeff Kirsher extern void e1000e_check_options(struct e1000_adapter *adapter); 481*dee1ad47SJeff Kirsher extern void e1000e_set_ethtool_ops(struct net_device *netdev); 482*dee1ad47SJeff Kirsher 483*dee1ad47SJeff Kirsher extern int e1000e_up(struct e1000_adapter *adapter); 484*dee1ad47SJeff Kirsher extern void e1000e_down(struct e1000_adapter *adapter); 485*dee1ad47SJeff Kirsher extern void e1000e_reinit_locked(struct e1000_adapter *adapter); 486*dee1ad47SJeff Kirsher extern void e1000e_reset(struct e1000_adapter *adapter); 487*dee1ad47SJeff Kirsher extern void e1000e_power_up_phy(struct e1000_adapter *adapter); 488*dee1ad47SJeff Kirsher extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter); 489*dee1ad47SJeff Kirsher extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter); 490*dee1ad47SJeff Kirsher extern void e1000e_free_rx_resources(struct e1000_adapter *adapter); 491*dee1ad47SJeff Kirsher extern void e1000e_free_tx_resources(struct e1000_adapter *adapter); 492*dee1ad47SJeff Kirsher extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 493*dee1ad47SJeff Kirsher struct rtnl_link_stats64 494*dee1ad47SJeff Kirsher *stats); 495*dee1ad47SJeff Kirsher extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 496*dee1ad47SJeff Kirsher extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 497*dee1ad47SJeff Kirsher extern void e1000e_get_hw_control(struct e1000_adapter *adapter); 498*dee1ad47SJeff Kirsher extern void e1000e_release_hw_control(struct e1000_adapter *adapter); 499*dee1ad47SJeff Kirsher 500*dee1ad47SJeff Kirsher extern unsigned int copybreak; 501*dee1ad47SJeff Kirsher 502*dee1ad47SJeff Kirsher extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); 503*dee1ad47SJeff Kirsher 504*dee1ad47SJeff Kirsher extern struct e1000_info e1000_82571_info; 505*dee1ad47SJeff Kirsher extern struct e1000_info e1000_82572_info; 506*dee1ad47SJeff Kirsher extern struct e1000_info e1000_82573_info; 507*dee1ad47SJeff Kirsher extern struct e1000_info e1000_82574_info; 508*dee1ad47SJeff Kirsher extern struct e1000_info e1000_82583_info; 509*dee1ad47SJeff Kirsher extern struct e1000_info e1000_ich8_info; 510*dee1ad47SJeff Kirsher extern struct e1000_info e1000_ich9_info; 511*dee1ad47SJeff Kirsher extern struct e1000_info e1000_ich10_info; 512*dee1ad47SJeff Kirsher extern struct e1000_info e1000_pch_info; 513*dee1ad47SJeff Kirsher extern struct e1000_info e1000_pch2_info; 514*dee1ad47SJeff Kirsher extern struct e1000_info e1000_es2_info; 515*dee1ad47SJeff Kirsher 516*dee1ad47SJeff Kirsher extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 517*dee1ad47SJeff Kirsher u32 pba_num_size); 518*dee1ad47SJeff Kirsher 519*dee1ad47SJeff Kirsher extern s32 e1000e_commit_phy(struct e1000_hw *hw); 520*dee1ad47SJeff Kirsher 521*dee1ad47SJeff Kirsher extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 522*dee1ad47SJeff Kirsher 523*dee1ad47SJeff Kirsher extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 524*dee1ad47SJeff Kirsher extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 525*dee1ad47SJeff Kirsher 526*dee1ad47SJeff Kirsher extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); 527*dee1ad47SJeff Kirsher extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 528*dee1ad47SJeff Kirsher bool state); 529*dee1ad47SJeff Kirsher extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 530*dee1ad47SJeff Kirsher extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 531*dee1ad47SJeff Kirsher extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 532*dee1ad47SJeff Kirsher extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 533*dee1ad47SJeff Kirsher extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 534*dee1ad47SJeff Kirsher extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 535*dee1ad47SJeff Kirsher extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 536*dee1ad47SJeff Kirsher 537*dee1ad47SJeff Kirsher extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 538*dee1ad47SJeff Kirsher extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 539*dee1ad47SJeff Kirsher extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 540*dee1ad47SJeff Kirsher extern s32 e1000e_setup_led_generic(struct e1000_hw *hw); 541*dee1ad47SJeff Kirsher extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 542*dee1ad47SJeff Kirsher extern s32 e1000e_led_on_generic(struct e1000_hw *hw); 543*dee1ad47SJeff Kirsher extern s32 e1000e_led_off_generic(struct e1000_hw *hw); 544*dee1ad47SJeff Kirsher extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 545*dee1ad47SJeff Kirsher extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 546*dee1ad47SJeff Kirsher extern void e1000_set_lan_id_single_port(struct e1000_hw *hw); 547*dee1ad47SJeff Kirsher extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); 548*dee1ad47SJeff Kirsher extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); 549*dee1ad47SJeff Kirsher extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 550*dee1ad47SJeff Kirsher extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 551*dee1ad47SJeff Kirsher extern s32 e1000e_id_led_init(struct e1000_hw *hw); 552*dee1ad47SJeff Kirsher extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 553*dee1ad47SJeff Kirsher extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 554*dee1ad47SJeff Kirsher extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 555*dee1ad47SJeff Kirsher extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 556*dee1ad47SJeff Kirsher extern s32 e1000e_setup_link(struct e1000_hw *hw); 557*dee1ad47SJeff Kirsher extern void e1000_clear_vfta_generic(struct e1000_hw *hw); 558*dee1ad47SJeff Kirsher extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 559*dee1ad47SJeff Kirsher extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 560*dee1ad47SJeff Kirsher u8 *mc_addr_list, 561*dee1ad47SJeff Kirsher u32 mc_addr_count); 562*dee1ad47SJeff Kirsher extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); 563*dee1ad47SJeff Kirsher extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 564*dee1ad47SJeff Kirsher extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 565*dee1ad47SJeff Kirsher extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 566*dee1ad47SJeff Kirsher extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 567*dee1ad47SJeff Kirsher extern void e1000e_config_collision_dist(struct e1000_hw *hw); 568*dee1ad47SJeff Kirsher extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 569*dee1ad47SJeff Kirsher extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); 570*dee1ad47SJeff Kirsher extern s32 e1000e_blink_led_generic(struct e1000_hw *hw); 571*dee1ad47SJeff Kirsher extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 572*dee1ad47SJeff Kirsher extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 573*dee1ad47SJeff Kirsher extern void e1000e_reset_adaptive(struct e1000_hw *hw); 574*dee1ad47SJeff Kirsher extern void e1000e_update_adaptive(struct e1000_hw *hw); 575*dee1ad47SJeff Kirsher 576*dee1ad47SJeff Kirsher extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); 577*dee1ad47SJeff Kirsher extern s32 e1000e_get_phy_id(struct e1000_hw *hw); 578*dee1ad47SJeff Kirsher extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); 579*dee1ad47SJeff Kirsher extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 580*dee1ad47SJeff Kirsher extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 581*dee1ad47SJeff Kirsher extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 582*dee1ad47SJeff Kirsher extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 583*dee1ad47SJeff Kirsher extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 584*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 585*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 586*dee1ad47SJeff Kirsher u16 *data); 587*dee1ad47SJeff Kirsher extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 588*dee1ad47SJeff Kirsher extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 589*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 590*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 591*dee1ad47SJeff Kirsher u16 data); 592*dee1ad47SJeff Kirsher extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 593*dee1ad47SJeff Kirsher extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 594*dee1ad47SJeff Kirsher extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); 595*dee1ad47SJeff Kirsher extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 596*dee1ad47SJeff Kirsher extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 597*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 598*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 599*dee1ad47SJeff Kirsher extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 600*dee1ad47SJeff Kirsher extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 601*dee1ad47SJeff Kirsher extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); 602*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 603*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 604*dee1ad47SJeff Kirsher extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 605*dee1ad47SJeff Kirsher u16 *phy_reg); 606*dee1ad47SJeff Kirsher extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 607*dee1ad47SJeff Kirsher u16 *phy_reg); 608*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 609*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 610*dee1ad47SJeff Kirsher extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 611*dee1ad47SJeff Kirsher extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 612*dee1ad47SJeff Kirsher extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 613*dee1ad47SJeff Kirsher u16 data); 614*dee1ad47SJeff Kirsher extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 615*dee1ad47SJeff Kirsher extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 616*dee1ad47SJeff Kirsher u16 *data); 617*dee1ad47SJeff Kirsher extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 618*dee1ad47SJeff Kirsher u32 usec_interval, bool *success); 619*dee1ad47SJeff Kirsher extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 620*dee1ad47SJeff Kirsher extern void e1000_power_up_phy_copper(struct e1000_hw *hw); 621*dee1ad47SJeff Kirsher extern void e1000_power_down_phy_copper(struct e1000_hw *hw); 622*dee1ad47SJeff Kirsher extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 623*dee1ad47SJeff Kirsher extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 624*dee1ad47SJeff Kirsher extern s32 e1000e_check_downshift(struct e1000_hw *hw); 625*dee1ad47SJeff Kirsher extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 626*dee1ad47SJeff Kirsher extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 627*dee1ad47SJeff Kirsher u16 *data); 628*dee1ad47SJeff Kirsher extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 629*dee1ad47SJeff Kirsher u16 *data); 630*dee1ad47SJeff Kirsher extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 631*dee1ad47SJeff Kirsher extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 632*dee1ad47SJeff Kirsher u16 data); 633*dee1ad47SJeff Kirsher extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 634*dee1ad47SJeff Kirsher u16 data); 635*dee1ad47SJeff Kirsher extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 636*dee1ad47SJeff Kirsher extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 637*dee1ad47SJeff Kirsher extern s32 e1000_check_polarity_82577(struct e1000_hw *hw); 638*dee1ad47SJeff Kirsher extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 639*dee1ad47SJeff Kirsher extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 640*dee1ad47SJeff Kirsher extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 641*dee1ad47SJeff Kirsher 642*dee1ad47SJeff Kirsher extern s32 e1000_check_polarity_m88(struct e1000_hw *hw); 643*dee1ad47SJeff Kirsher extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 644*dee1ad47SJeff Kirsher extern s32 e1000_check_polarity_ife(struct e1000_hw *hw); 645*dee1ad47SJeff Kirsher extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 646*dee1ad47SJeff Kirsher extern s32 e1000_check_polarity_igp(struct e1000_hw *hw); 647*dee1ad47SJeff Kirsher extern bool e1000_check_phy_82574(struct e1000_hw *hw); 648*dee1ad47SJeff Kirsher 649*dee1ad47SJeff Kirsher static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 650*dee1ad47SJeff Kirsher { 651*dee1ad47SJeff Kirsher return hw->phy.ops.reset(hw); 652*dee1ad47SJeff Kirsher } 653*dee1ad47SJeff Kirsher 654*dee1ad47SJeff Kirsher static inline s32 e1000_check_reset_block(struct e1000_hw *hw) 655*dee1ad47SJeff Kirsher { 656*dee1ad47SJeff Kirsher return hw->phy.ops.check_reset_block(hw); 657*dee1ad47SJeff Kirsher } 658*dee1ad47SJeff Kirsher 659*dee1ad47SJeff Kirsher static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 660*dee1ad47SJeff Kirsher { 661*dee1ad47SJeff Kirsher return hw->phy.ops.read_reg(hw, offset, data); 662*dee1ad47SJeff Kirsher } 663*dee1ad47SJeff Kirsher 664*dee1ad47SJeff Kirsher static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 665*dee1ad47SJeff Kirsher { 666*dee1ad47SJeff Kirsher return hw->phy.ops.write_reg(hw, offset, data); 667*dee1ad47SJeff Kirsher } 668*dee1ad47SJeff Kirsher 669*dee1ad47SJeff Kirsher static inline s32 e1000_get_cable_length(struct e1000_hw *hw) 670*dee1ad47SJeff Kirsher { 671*dee1ad47SJeff Kirsher return hw->phy.ops.get_cable_length(hw); 672*dee1ad47SJeff Kirsher } 673*dee1ad47SJeff Kirsher 674*dee1ad47SJeff Kirsher extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); 675*dee1ad47SJeff Kirsher extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 676*dee1ad47SJeff Kirsher extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); 677*dee1ad47SJeff Kirsher extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); 678*dee1ad47SJeff Kirsher extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 679*dee1ad47SJeff Kirsher extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); 680*dee1ad47SJeff Kirsher extern void e1000e_release_nvm(struct e1000_hw *hw); 681*dee1ad47SJeff Kirsher extern void e1000e_reload_nvm(struct e1000_hw *hw); 682*dee1ad47SJeff Kirsher extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); 683*dee1ad47SJeff Kirsher 684*dee1ad47SJeff Kirsher static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 685*dee1ad47SJeff Kirsher { 686*dee1ad47SJeff Kirsher if (hw->mac.ops.read_mac_addr) 687*dee1ad47SJeff Kirsher return hw->mac.ops.read_mac_addr(hw); 688*dee1ad47SJeff Kirsher 689*dee1ad47SJeff Kirsher return e1000_read_mac_addr_generic(hw); 690*dee1ad47SJeff Kirsher } 691*dee1ad47SJeff Kirsher 692*dee1ad47SJeff Kirsher static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 693*dee1ad47SJeff Kirsher { 694*dee1ad47SJeff Kirsher return hw->nvm.ops.validate(hw); 695*dee1ad47SJeff Kirsher } 696*dee1ad47SJeff Kirsher 697*dee1ad47SJeff Kirsher static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 698*dee1ad47SJeff Kirsher { 699*dee1ad47SJeff Kirsher return hw->nvm.ops.update(hw); 700*dee1ad47SJeff Kirsher } 701*dee1ad47SJeff Kirsher 702*dee1ad47SJeff Kirsher static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 703*dee1ad47SJeff Kirsher { 704*dee1ad47SJeff Kirsher return hw->nvm.ops.read(hw, offset, words, data); 705*dee1ad47SJeff Kirsher } 706*dee1ad47SJeff Kirsher 707*dee1ad47SJeff Kirsher static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 708*dee1ad47SJeff Kirsher { 709*dee1ad47SJeff Kirsher return hw->nvm.ops.write(hw, offset, words, data); 710*dee1ad47SJeff Kirsher } 711*dee1ad47SJeff Kirsher 712*dee1ad47SJeff Kirsher static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 713*dee1ad47SJeff Kirsher { 714*dee1ad47SJeff Kirsher return hw->phy.ops.get_info(hw); 715*dee1ad47SJeff Kirsher } 716*dee1ad47SJeff Kirsher 717*dee1ad47SJeff Kirsher static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw) 718*dee1ad47SJeff Kirsher { 719*dee1ad47SJeff Kirsher return hw->mac.ops.check_mng_mode(hw); 720*dee1ad47SJeff Kirsher } 721*dee1ad47SJeff Kirsher 722*dee1ad47SJeff Kirsher extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 723*dee1ad47SJeff Kirsher extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 724*dee1ad47SJeff Kirsher extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 725*dee1ad47SJeff Kirsher 726*dee1ad47SJeff Kirsher static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 727*dee1ad47SJeff Kirsher { 728*dee1ad47SJeff Kirsher return readl(hw->hw_addr + reg); 729*dee1ad47SJeff Kirsher } 730*dee1ad47SJeff Kirsher 731*dee1ad47SJeff Kirsher static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 732*dee1ad47SJeff Kirsher { 733*dee1ad47SJeff Kirsher writel(val, hw->hw_addr + reg); 734*dee1ad47SJeff Kirsher } 735*dee1ad47SJeff Kirsher 736*dee1ad47SJeff Kirsher #endif /* _E1000_H_ */ 737