1e78b80b1SDavid Ertman /* Intel PRO/1000 Linux driver 2529498cdSYanir Lubetkin * Copyright(c) 1999 - 2015 Intel Corporation. 3e78b80b1SDavid Ertman * 4e78b80b1SDavid Ertman * This program is free software; you can redistribute it and/or modify it 5e78b80b1SDavid Ertman * under the terms and conditions of the GNU General Public License, 6e78b80b1SDavid Ertman * version 2, as published by the Free Software Foundation. 7e78b80b1SDavid Ertman * 8e78b80b1SDavid Ertman * This program is distributed in the hope it will be useful, but WITHOUT 9e78b80b1SDavid Ertman * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10e78b80b1SDavid Ertman * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11e78b80b1SDavid Ertman * more details. 12e78b80b1SDavid Ertman * 13e78b80b1SDavid Ertman * The full GNU General Public License is included in this distribution in 14e78b80b1SDavid Ertman * the file called "COPYING". 15e78b80b1SDavid Ertman * 16e78b80b1SDavid Ertman * Contact Information: 17e78b80b1SDavid Ertman * Linux NICS <linux.nics@intel.com> 18e78b80b1SDavid Ertman * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19e78b80b1SDavid Ertman * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20e78b80b1SDavid Ertman */ 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher /* Linux PRO/1000 Ethernet Driver main header file */ 23dee1ad47SJeff Kirsher 24dee1ad47SJeff Kirsher #ifndef _E1000_H_ 25dee1ad47SJeff Kirsher #define _E1000_H_ 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher #include <linux/bitops.h> 28dee1ad47SJeff Kirsher #include <linux/types.h> 29dee1ad47SJeff Kirsher #include <linux/timer.h> 30dee1ad47SJeff Kirsher #include <linux/workqueue.h> 31dee1ad47SJeff Kirsher #include <linux/io.h> 32dee1ad47SJeff Kirsher #include <linux/netdevice.h> 33dee1ad47SJeff Kirsher #include <linux/pci.h> 34dee1ad47SJeff Kirsher #include <linux/pci-aspm.h> 35dee1ad47SJeff Kirsher #include <linux/crc32.h> 36dee1ad47SJeff Kirsher #include <linux/if_vlan.h> 3774d23cc7SRichard Cochran #include <linux/timecounter.h> 38b67e1913SBruce Allan #include <linux/net_tstamp.h> 39d89777bfSBruce Allan #include <linux/ptp_clock_kernel.h> 40d89777bfSBruce Allan #include <linux/ptp_classify.h> 41c2ade1a4SBruce Allan #include <linux/mii.h> 42d495bcb8SBruce Allan #include <linux/mdio.h> 435684044fSDavid Ahern #include <linux/pm_qos.h> 44dee1ad47SJeff Kirsher #include "hw.h" 45dee1ad47SJeff Kirsher 46dee1ad47SJeff Kirsher struct e1000_info; 47dee1ad47SJeff Kirsher 48dee1ad47SJeff Kirsher #define e_dbg(format, arg...) \ 49dee1ad47SJeff Kirsher netdev_dbg(hw->adapter->netdev, format, ## arg) 50dee1ad47SJeff Kirsher #define e_err(format, arg...) \ 51dee1ad47SJeff Kirsher netdev_err(adapter->netdev, format, ## arg) 52dee1ad47SJeff Kirsher #define e_info(format, arg...) \ 53dee1ad47SJeff Kirsher netdev_info(adapter->netdev, format, ## arg) 54dee1ad47SJeff Kirsher #define e_warn(format, arg...) \ 55dee1ad47SJeff Kirsher netdev_warn(adapter->netdev, format, ## arg) 56dee1ad47SJeff Kirsher #define e_notice(format, arg...) \ 57dee1ad47SJeff Kirsher netdev_notice(adapter->netdev, format, ## arg) 58dee1ad47SJeff Kirsher 59dee1ad47SJeff Kirsher /* Interrupt modes, as used by the IntMode parameter */ 60dee1ad47SJeff Kirsher #define E1000E_INT_MODE_LEGACY 0 61dee1ad47SJeff Kirsher #define E1000E_INT_MODE_MSI 1 62dee1ad47SJeff Kirsher #define E1000E_INT_MODE_MSIX 2 63dee1ad47SJeff Kirsher 64dee1ad47SJeff Kirsher /* Tx/Rx descriptor defines */ 65dee1ad47SJeff Kirsher #define E1000_DEFAULT_TXD 256 66dee1ad47SJeff Kirsher #define E1000_MAX_TXD 4096 67dee1ad47SJeff Kirsher #define E1000_MIN_TXD 64 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher #define E1000_DEFAULT_RXD 256 70dee1ad47SJeff Kirsher #define E1000_MAX_RXD 4096 71dee1ad47SJeff Kirsher #define E1000_MIN_RXD 64 72dee1ad47SJeff Kirsher 73dee1ad47SJeff Kirsher #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 74dee1ad47SJeff Kirsher #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 75dee1ad47SJeff Kirsher 76dee1ad47SJeff Kirsher #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 77dee1ad47SJeff Kirsher 78dee1ad47SJeff Kirsher /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 79dee1ad47SJeff Kirsher /* How many Rx Buffers do we bundle into one write to the hardware ? */ 80dee1ad47SJeff Kirsher #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 81dee1ad47SJeff Kirsher 82dee1ad47SJeff Kirsher #define AUTO_ALL_MODES 0 83dee1ad47SJeff Kirsher #define E1000_EEPROM_APME 0x0400 84dee1ad47SJeff Kirsher 85dee1ad47SJeff Kirsher #define E1000_MNG_VLAN_NONE (-1) 86dee1ad47SJeff Kirsher 87dee1ad47SJeff Kirsher #define DEFAULT_JUMBO 9234 88dee1ad47SJeff Kirsher 89dee1ad47SJeff Kirsher /* Time to wait before putting the device into D3 if there's no link (in ms). */ 90dee1ad47SJeff Kirsher #define LINK_TIMEOUT 100 91dee1ad47SJeff Kirsher 92e921eb1aSBruce Allan /* Count for polling __E1000_RESET condition every 10-20msec. 93bb9e44d0SBruce Allan * Experimentation has shown the reset can take approximately 210msec. 94bb9e44d0SBruce Allan */ 95bb9e44d0SBruce Allan #define E1000_CHECK_RESET_COUNT 25 96bb9e44d0SBruce Allan 97dee1ad47SJeff Kirsher #define DEFAULT_RDTR 0 98dee1ad47SJeff Kirsher #define DEFAULT_RADV 8 99dee1ad47SJeff Kirsher #define BURST_RDTR 0x20 100dee1ad47SJeff Kirsher #define BURST_RADV 0x20 101ff917429SYanir Lubetkin #define PCICFG_DESC_RING_STATUS 0xe4 102ff917429SYanir Lubetkin #define FLUSH_DESC_REQUIRED 0x100 103dee1ad47SJeff Kirsher 104e921eb1aSBruce Allan /* in the case of WTHRESH, it appears at least the 82571/2 hardware 105dee1ad47SJeff Kirsher * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 1068edc0e62SHiroaki SHIMODA * WTHRESH=4, so a setting of 5 gives the most efficient bus 1078edc0e62SHiroaki SHIMODA * utilization but to avoid possible Tx stalls, set it to 1 108dee1ad47SJeff Kirsher */ 109dee1ad47SJeff Kirsher #define E1000_TXDCTL_DMA_BURST_ENABLE \ 110dee1ad47SJeff Kirsher (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 111dee1ad47SJeff Kirsher E1000_TXDCTL_COUNT_DESC | \ 11218dd2392SJacob Keller (1u << 16) | /* wthresh must be +1 more than desired */\ 11318dd2392SJacob Keller (1u << 8) | /* hthresh */ \ 114dee1ad47SJeff Kirsher 0x1f) /* pthresh */ 115dee1ad47SJeff Kirsher 116dee1ad47SJeff Kirsher #define E1000_RXDCTL_DMA_BURST_ENABLE \ 117dee1ad47SJeff Kirsher (0x01000000 | /* set descriptor granularity */ \ 11818dd2392SJacob Keller (4u << 16) | /* set writeback threshold */ \ 11918dd2392SJacob Keller (4u << 8) | /* set prefetch threshold */ \ 120dee1ad47SJeff Kirsher 0x20) /* set hthresh */ 121dee1ad47SJeff Kirsher 12218dd2392SJacob Keller #define E1000_TIDV_FPD BIT(31) 12318dd2392SJacob Keller #define E1000_RDTR_FPD BIT(31) 124dee1ad47SJeff Kirsher 125dee1ad47SJeff Kirsher enum e1000_boards { 126dee1ad47SJeff Kirsher board_82571, 127dee1ad47SJeff Kirsher board_82572, 128dee1ad47SJeff Kirsher board_82573, 129dee1ad47SJeff Kirsher board_82574, 130dee1ad47SJeff Kirsher board_82583, 131dee1ad47SJeff Kirsher board_80003es2lan, 132dee1ad47SJeff Kirsher board_ich8lan, 133dee1ad47SJeff Kirsher board_ich9lan, 134dee1ad47SJeff Kirsher board_ich10lan, 135dee1ad47SJeff Kirsher board_pchlan, 136dee1ad47SJeff Kirsher board_pch2lan, 1372fbe4526SBruce Allan board_pch_lpt, 1383a3173b9SSasha Neftin board_pch_spt, 1393a3173b9SSasha Neftin board_pch_cnp 140dee1ad47SJeff Kirsher }; 141dee1ad47SJeff Kirsher 142dee1ad47SJeff Kirsher struct e1000_ps_page { 143dee1ad47SJeff Kirsher struct page *page; 144dee1ad47SJeff Kirsher u64 dma; /* must be u64 - written to hw */ 145dee1ad47SJeff Kirsher }; 146dee1ad47SJeff Kirsher 147e921eb1aSBruce Allan /* wrappers around a pointer to a socket buffer, 148dee1ad47SJeff Kirsher * so a DMA handle can be stored along with the buffer 149dee1ad47SJeff Kirsher */ 150dee1ad47SJeff Kirsher struct e1000_buffer { 151dee1ad47SJeff Kirsher dma_addr_t dma; 152dee1ad47SJeff Kirsher struct sk_buff *skb; 153dee1ad47SJeff Kirsher union { 154dee1ad47SJeff Kirsher /* Tx */ 155dee1ad47SJeff Kirsher struct { 156dee1ad47SJeff Kirsher unsigned long time_stamp; 157dee1ad47SJeff Kirsher u16 length; 158dee1ad47SJeff Kirsher u16 next_to_watch; 159dee1ad47SJeff Kirsher unsigned int segs; 160dee1ad47SJeff Kirsher unsigned int bytecount; 161dee1ad47SJeff Kirsher u16 mapped_as_page; 162dee1ad47SJeff Kirsher }; 163dee1ad47SJeff Kirsher /* Rx */ 164dee1ad47SJeff Kirsher struct { 165dee1ad47SJeff Kirsher /* arrays of page information for packet split */ 166dee1ad47SJeff Kirsher struct e1000_ps_page *ps_pages; 167dee1ad47SJeff Kirsher struct page *page; 168dee1ad47SJeff Kirsher }; 169dee1ad47SJeff Kirsher }; 170dee1ad47SJeff Kirsher }; 171dee1ad47SJeff Kirsher 172dee1ad47SJeff Kirsher struct e1000_ring { 17355aa6985SBruce Allan struct e1000_adapter *adapter; /* back pointer to adapter */ 174dee1ad47SJeff Kirsher void *desc; /* pointer to ring memory */ 175dee1ad47SJeff Kirsher dma_addr_t dma; /* phys address of ring */ 176dee1ad47SJeff Kirsher unsigned int size; /* length of ring in bytes */ 177dee1ad47SJeff Kirsher unsigned int count; /* number of desc. in ring */ 178dee1ad47SJeff Kirsher 179dee1ad47SJeff Kirsher u16 next_to_use; 180dee1ad47SJeff Kirsher u16 next_to_clean; 181dee1ad47SJeff Kirsher 182c5083cf6SBruce Allan void __iomem *head; 183c5083cf6SBruce Allan void __iomem *tail; 184dee1ad47SJeff Kirsher 185dee1ad47SJeff Kirsher /* array of buffer information structs */ 186dee1ad47SJeff Kirsher struct e1000_buffer *buffer_info; 187dee1ad47SJeff Kirsher 188dee1ad47SJeff Kirsher char name[IFNAMSIZ + 5]; 189dee1ad47SJeff Kirsher u32 ims_val; 190dee1ad47SJeff Kirsher u32 itr_val; 191c5083cf6SBruce Allan void __iomem *itr_register; 192dee1ad47SJeff Kirsher int set_itr; 193dee1ad47SJeff Kirsher 194dee1ad47SJeff Kirsher struct sk_buff *rx_skb_top; 195dee1ad47SJeff Kirsher }; 196dee1ad47SJeff Kirsher 197dee1ad47SJeff Kirsher /* PHY register snapshot values */ 198dee1ad47SJeff Kirsher struct e1000_phy_regs { 199dee1ad47SJeff Kirsher u16 bmcr; /* basic mode control register */ 200dee1ad47SJeff Kirsher u16 bmsr; /* basic mode status register */ 201dee1ad47SJeff Kirsher u16 advertise; /* auto-negotiation advertisement */ 202dee1ad47SJeff Kirsher u16 lpa; /* link partner ability register */ 203dee1ad47SJeff Kirsher u16 expansion; /* auto-negotiation expansion reg */ 204dee1ad47SJeff Kirsher u16 ctrl1000; /* 1000BASE-T control register */ 205dee1ad47SJeff Kirsher u16 stat1000; /* 1000BASE-T status register */ 206dee1ad47SJeff Kirsher u16 estatus; /* extended status register */ 207dee1ad47SJeff Kirsher }; 208dee1ad47SJeff Kirsher 209dee1ad47SJeff Kirsher /* board specific private data structure */ 210dee1ad47SJeff Kirsher struct e1000_adapter { 211dee1ad47SJeff Kirsher struct timer_list watchdog_timer; 212dee1ad47SJeff Kirsher struct timer_list phy_info_timer; 213dee1ad47SJeff Kirsher struct timer_list blink_timer; 214dee1ad47SJeff Kirsher 215dee1ad47SJeff Kirsher struct work_struct reset_task; 216dee1ad47SJeff Kirsher struct work_struct watchdog_task; 217dee1ad47SJeff Kirsher 218dee1ad47SJeff Kirsher const struct e1000_info *ei; 219dee1ad47SJeff Kirsher 220dee1ad47SJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 221dee1ad47SJeff Kirsher u32 bd_number; 222dee1ad47SJeff Kirsher u32 rx_buffer_len; 223dee1ad47SJeff Kirsher u16 mng_vlan_id; 224dee1ad47SJeff Kirsher u16 link_speed; 225dee1ad47SJeff Kirsher u16 link_duplex; 226dee1ad47SJeff Kirsher u16 eeprom_vers; 227dee1ad47SJeff Kirsher 228dee1ad47SJeff Kirsher /* track device up/down/testing state */ 229dee1ad47SJeff Kirsher unsigned long state; 230dee1ad47SJeff Kirsher 231dee1ad47SJeff Kirsher /* Interrupt Throttle Rate */ 232dee1ad47SJeff Kirsher u32 itr; 233dee1ad47SJeff Kirsher u32 itr_setting; 234dee1ad47SJeff Kirsher u16 tx_itr; 235dee1ad47SJeff Kirsher u16 rx_itr; 236dee1ad47SJeff Kirsher 23733550cecSBruce Allan /* Tx - one ring per active queue */ 23833550cecSBruce Allan struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 239d821a4c4SBruce Allan u32 tx_fifo_limit; 240dee1ad47SJeff Kirsher 241dee1ad47SJeff Kirsher struct napi_struct napi; 242dee1ad47SJeff Kirsher 24394fb848bSBruce Allan unsigned int uncorr_errors; /* uncorrectable ECC errors */ 24494fb848bSBruce Allan unsigned int corr_errors; /* correctable ECC errors */ 245dee1ad47SJeff Kirsher unsigned int restart_queue; 246dee1ad47SJeff Kirsher u32 txd_cmd; 247dee1ad47SJeff Kirsher 248dee1ad47SJeff Kirsher bool detect_tx_hung; 24909357b00SJeff Kirsher bool tx_hang_recheck; 250dee1ad47SJeff Kirsher u8 tx_timeout_factor; 251dee1ad47SJeff Kirsher 252dee1ad47SJeff Kirsher u32 tx_int_delay; 253dee1ad47SJeff Kirsher u32 tx_abs_int_delay; 254dee1ad47SJeff Kirsher 255dee1ad47SJeff Kirsher unsigned int total_tx_bytes; 256dee1ad47SJeff Kirsher unsigned int total_tx_packets; 257dee1ad47SJeff Kirsher unsigned int total_rx_bytes; 258dee1ad47SJeff Kirsher unsigned int total_rx_packets; 259dee1ad47SJeff Kirsher 260dee1ad47SJeff Kirsher /* Tx stats */ 261dee1ad47SJeff Kirsher u64 tpt_old; 262dee1ad47SJeff Kirsher u64 colc_old; 263dee1ad47SJeff Kirsher u32 gotc; 264dee1ad47SJeff Kirsher u64 gotc_old; 265dee1ad47SJeff Kirsher u32 tx_timeout_count; 266dee1ad47SJeff Kirsher u32 tx_fifo_head; 267dee1ad47SJeff Kirsher u32 tx_head_addr; 268dee1ad47SJeff Kirsher u32 tx_fifo_size; 269dee1ad47SJeff Kirsher u32 tx_dma_failed; 27059c871c5SJakub Kicinski u32 tx_hwtstamp_timeouts; 271dee1ad47SJeff Kirsher 272e921eb1aSBruce Allan /* Rx */ 27355aa6985SBruce Allan bool (*clean_rx)(struct e1000_ring *ring, int *work_done, 27455aa6985SBruce Allan int work_to_do) ____cacheline_aligned_in_smp; 27555aa6985SBruce Allan void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, 27655aa6985SBruce Allan gfp_t gfp); 277dee1ad47SJeff Kirsher struct e1000_ring *rx_ring; 278dee1ad47SJeff Kirsher 279dee1ad47SJeff Kirsher u32 rx_int_delay; 280dee1ad47SJeff Kirsher u32 rx_abs_int_delay; 281dee1ad47SJeff Kirsher 282dee1ad47SJeff Kirsher /* Rx stats */ 283dee1ad47SJeff Kirsher u64 hw_csum_err; 284dee1ad47SJeff Kirsher u64 hw_csum_good; 285dee1ad47SJeff Kirsher u64 rx_hdr_split; 286dee1ad47SJeff Kirsher u32 gorc; 287dee1ad47SJeff Kirsher u64 gorc_old; 288dee1ad47SJeff Kirsher u32 alloc_rx_buff_failed; 289dee1ad47SJeff Kirsher u32 rx_dma_failed; 290b67e1913SBruce Allan u32 rx_hwtstamp_cleared; 291dee1ad47SJeff Kirsher 292dee1ad47SJeff Kirsher unsigned int rx_ps_pages; 293dee1ad47SJeff Kirsher u16 rx_ps_bsize0; 294dee1ad47SJeff Kirsher u32 max_frame_size; 295dee1ad47SJeff Kirsher u32 min_frame_size; 296dee1ad47SJeff Kirsher 297dee1ad47SJeff Kirsher /* OS defined structs */ 298dee1ad47SJeff Kirsher struct net_device *netdev; 299dee1ad47SJeff Kirsher struct pci_dev *pdev; 300dee1ad47SJeff Kirsher 301dee1ad47SJeff Kirsher /* structs defined in e1000_hw.h */ 302dee1ad47SJeff Kirsher struct e1000_hw hw; 303dee1ad47SJeff Kirsher 3049d57088bSBruce Allan spinlock_t stats64_lock; /* protects statistics counters */ 305dee1ad47SJeff Kirsher struct e1000_hw_stats stats; 306dee1ad47SJeff Kirsher struct e1000_phy_info phy_info; 307dee1ad47SJeff Kirsher struct e1000_phy_stats phy_stats; 308dee1ad47SJeff Kirsher 309dee1ad47SJeff Kirsher /* Snapshot of PHY registers */ 310dee1ad47SJeff Kirsher struct e1000_phy_regs phy_regs; 311dee1ad47SJeff Kirsher 312dee1ad47SJeff Kirsher struct e1000_ring test_tx_ring; 313dee1ad47SJeff Kirsher struct e1000_ring test_rx_ring; 314dee1ad47SJeff Kirsher u32 test_icr; 315dee1ad47SJeff Kirsher 316dee1ad47SJeff Kirsher u32 msg_enable; 317dee1ad47SJeff Kirsher unsigned int num_vectors; 318dee1ad47SJeff Kirsher struct msix_entry *msix_entries; 319dee1ad47SJeff Kirsher int int_mode; 320dee1ad47SJeff Kirsher u32 eiac_mask; 321dee1ad47SJeff Kirsher 322dee1ad47SJeff Kirsher u32 eeprom_wol; 323dee1ad47SJeff Kirsher u32 wol; 324dee1ad47SJeff Kirsher u32 pba; 325dee1ad47SJeff Kirsher u32 max_hw_frame_size; 326dee1ad47SJeff Kirsher 327dee1ad47SJeff Kirsher bool fc_autoneg; 328dee1ad47SJeff Kirsher 329dee1ad47SJeff Kirsher unsigned int flags; 330dee1ad47SJeff Kirsher unsigned int flags2; 331dee1ad47SJeff Kirsher struct work_struct downshift_task; 332dee1ad47SJeff Kirsher struct work_struct update_phy_task; 333dee1ad47SJeff Kirsher struct work_struct print_hang_task; 334dee1ad47SJeff Kirsher 335dee1ad47SJeff Kirsher int phy_hang_count; 33655aa6985SBruce Allan 33755aa6985SBruce Allan u16 tx_ring_count; 33855aa6985SBruce Allan u16 rx_ring_count; 339b67e1913SBruce Allan 340b67e1913SBruce Allan struct hwtstamp_config hwtstamp_config; 341b67e1913SBruce Allan struct delayed_work systim_overflow_work; 342b67e1913SBruce Allan struct sk_buff *tx_hwtstamp_skb; 34359c871c5SJakub Kicinski unsigned long tx_hwtstamp_start; 344b67e1913SBruce Allan struct work_struct tx_hwtstamp_work; 345b67e1913SBruce Allan spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 346b67e1913SBruce Allan struct cyclecounter cc; 347b67e1913SBruce Allan struct timecounter tc; 348d89777bfSBruce Allan struct ptp_clock *ptp_clock; 349d89777bfSBruce Allan struct ptp_clock_info ptp_clock_info; 350e2c65448SThomas Graf struct pm_qos_request pm_qos_req; 351aa524b66SJacob Keller s32 ptp_delta; 352d495bcb8SBruce Allan 353d495bcb8SBruce Allan u16 eee_advert; 354dee1ad47SJeff Kirsher }; 355dee1ad47SJeff Kirsher 356dee1ad47SJeff Kirsher struct e1000_info { 357dee1ad47SJeff Kirsher enum e1000_mac_type mac; 358dee1ad47SJeff Kirsher unsigned int flags; 359dee1ad47SJeff Kirsher unsigned int flags2; 360dee1ad47SJeff Kirsher u32 pba; 361dee1ad47SJeff Kirsher u32 max_hw_frame_size; 362dee1ad47SJeff Kirsher s32 (*get_variants)(struct e1000_adapter *); 3638ce9d6c7SJeff Kirsher const struct e1000_mac_operations *mac_ops; 3648ce9d6c7SJeff Kirsher const struct e1000_phy_operations *phy_ops; 3658ce9d6c7SJeff Kirsher const struct e1000_nvm_operations *nvm_ops; 366dee1ad47SJeff Kirsher }; 367dee1ad47SJeff Kirsher 368d89777bfSBruce Allan s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 369d89777bfSBruce Allan 370b67e1913SBruce Allan /* The system time is maintained by a 64-bit counter comprised of the 32-bit 371b67e1913SBruce Allan * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 372b67e1913SBruce Allan * its resolution) is based on the contents of the TIMINCA register - it 373b67e1913SBruce Allan * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 374b67e1913SBruce Allan * For the best accuracy, the incperiod should be as small as possible. The 375b67e1913SBruce Allan * incvalue is scaled by a factor as large as possible (while still fitting 376b67e1913SBruce Allan * in bits 23:0) so that relatively small clock corrections can be made. 377b67e1913SBruce Allan * 378b67e1913SBruce Allan * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 379b67e1913SBruce Allan * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 380b67e1913SBruce Allan * bits to count nanoseconds leaving the rest for fractional nonseconds. 381b67e1913SBruce Allan */ 382*68fe1d5dSSasha Neftin #define INCVALUE_96MHZ 125 383*68fe1d5dSSasha Neftin #define INCVALUE_SHIFT_96MHZ 17 384*68fe1d5dSSasha Neftin #define INCPERIOD_SHIFT_96MHZ 2 385*68fe1d5dSSasha Neftin #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ) 386b67e1913SBruce Allan 387*68fe1d5dSSasha Neftin #define INCVALUE_25MHZ 40 388*68fe1d5dSSasha Neftin #define INCVALUE_SHIFT_25MHZ 18 389*68fe1d5dSSasha Neftin #define INCPERIOD_25MHZ 1 390b67e1913SBruce Allan 391*68fe1d5dSSasha Neftin #define INCVALUE_24MHZ 125 392*68fe1d5dSSasha Neftin #define INCVALUE_SHIFT_24MHZ 14 393*68fe1d5dSSasha Neftin #define INCPERIOD_24MHZ 3 394*68fe1d5dSSasha Neftin 395*68fe1d5dSSasha Neftin #define INCVALUE_38400KHZ 26 396*68fe1d5dSSasha Neftin #define INCVALUE_SHIFT_38400KHZ 19 397*68fe1d5dSSasha Neftin #define INCPERIOD_38400KHZ 1 39883129b37SYanir Lubetkin 399b67e1913SBruce Allan /* Another drawback of scaling the incvalue by a large factor is the 400b67e1913SBruce Allan * 64-bit SYSTIM register overflows more quickly. This is dealt with 401b67e1913SBruce Allan * by simply reading the clock before it overflows. 402b67e1913SBruce Allan * 403b67e1913SBruce Allan * Clock ns bits Overflows after 404b67e1913SBruce Allan * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 405b67e1913SBruce Allan * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 406b67e1913SBruce Allan * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 407b67e1913SBruce Allan */ 408b67e1913SBruce Allan #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 4095e7ff970STodd Fujinaka #define E1000_MAX_82574_SYSTIM_REREADS 50 4105e7ff970STodd Fujinaka #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 411b67e1913SBruce Allan 412dee1ad47SJeff Kirsher /* hardware capability, feature, and workaround flags */ 41318dd2392SJacob Keller #define FLAG_HAS_AMT BIT(0) 41418dd2392SJacob Keller #define FLAG_HAS_FLASH BIT(1) 41518dd2392SJacob Keller #define FLAG_HAS_HW_VLAN_FILTER BIT(2) 41618dd2392SJacob Keller #define FLAG_HAS_WOL BIT(3) 41718dd2392SJacob Keller /* reserved BIT(4) */ 41818dd2392SJacob Keller #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) 41918dd2392SJacob Keller #define FLAG_HAS_SWSM_ON_LOAD BIT(6) 42018dd2392SJacob Keller #define FLAG_HAS_JUMBO_FRAMES BIT(7) 42118dd2392SJacob Keller #define FLAG_READ_ONLY_NVM BIT(8) 42218dd2392SJacob Keller #define FLAG_IS_ICH BIT(9) 42318dd2392SJacob Keller #define FLAG_HAS_MSIX BIT(10) 42418dd2392SJacob Keller #define FLAG_HAS_SMART_POWER_DOWN BIT(11) 42518dd2392SJacob Keller #define FLAG_IS_QUAD_PORT_A BIT(12) 42618dd2392SJacob Keller #define FLAG_IS_QUAD_PORT BIT(13) 42718dd2392SJacob Keller #define FLAG_HAS_HW_TIMESTAMP BIT(14) 42818dd2392SJacob Keller #define FLAG_APME_IN_WUC BIT(15) 42918dd2392SJacob Keller #define FLAG_APME_IN_CTRL3 BIT(16) 43018dd2392SJacob Keller #define FLAG_APME_CHECK_PORT_B BIT(17) 43118dd2392SJacob Keller #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) 43218dd2392SJacob Keller #define FLAG_NO_WAKE_UCAST BIT(19) 43318dd2392SJacob Keller #define FLAG_MNG_PT_ENABLED BIT(20) 43418dd2392SJacob Keller #define FLAG_RESET_OVERWRITES_LAA BIT(21) 43518dd2392SJacob Keller #define FLAG_TARC_SPEED_MODE_BIT BIT(22) 43618dd2392SJacob Keller #define FLAG_TARC_SET_BIT_ZERO BIT(23) 43718dd2392SJacob Keller #define FLAG_RX_NEEDS_RESTART BIT(24) 43818dd2392SJacob Keller #define FLAG_LSC_GIG_SPEED_DROP BIT(25) 43918dd2392SJacob Keller #define FLAG_SMART_POWER_DOWN BIT(26) 44018dd2392SJacob Keller #define FLAG_MSI_ENABLED BIT(27) 44118dd2392SJacob Keller /* reserved BIT(28) */ 44218dd2392SJacob Keller #define FLAG_TSO_FORCE BIT(29) 44318dd2392SJacob Keller #define FLAG_RESTART_NOW BIT(30) 44418dd2392SJacob Keller #define FLAG_MSI_TEST_FAILED BIT(31) 445dee1ad47SJeff Kirsher 44618dd2392SJacob Keller #define FLAG2_CRC_STRIPPING BIT(0) 44718dd2392SJacob Keller #define FLAG2_HAS_PHY_WAKEUP BIT(1) 44818dd2392SJacob Keller #define FLAG2_IS_DISCARDING BIT(2) 44918dd2392SJacob Keller #define FLAG2_DISABLE_ASPM_L1 BIT(3) 45018dd2392SJacob Keller #define FLAG2_HAS_PHY_STATS BIT(4) 45118dd2392SJacob Keller #define FLAG2_HAS_EEE BIT(5) 45218dd2392SJacob Keller #define FLAG2_DMA_BURST BIT(6) 45318dd2392SJacob Keller #define FLAG2_DISABLE_ASPM_L0S BIT(7) 45418dd2392SJacob Keller #define FLAG2_DISABLE_AIM BIT(8) 45518dd2392SJacob Keller #define FLAG2_CHECK_PHY_HANG BIT(9) 45618dd2392SJacob Keller #define FLAG2_NO_DISABLE_RX BIT(10) 45718dd2392SJacob Keller #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) 45818dd2392SJacob Keller #define FLAG2_DFLT_CRC_STRIPPING BIT(12) 45918dd2392SJacob Keller #define FLAG2_CHECK_RX_HWTSTAMP BIT(13) 4600be5b96cSJarod Wilson #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14) 461dee1ad47SJeff Kirsher 462dee1ad47SJeff Kirsher #define E1000_RX_DESC_PS(R, i) \ 463dee1ad47SJeff Kirsher (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 4645f450212SBruce Allan #define E1000_RX_DESC_EXT(R, i) \ 4655f450212SBruce Allan (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 466dee1ad47SJeff Kirsher #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 467dee1ad47SJeff Kirsher #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 468dee1ad47SJeff Kirsher #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 469dee1ad47SJeff Kirsher 470dee1ad47SJeff Kirsher enum e1000_state_t { 471dee1ad47SJeff Kirsher __E1000_TESTING, 472dee1ad47SJeff Kirsher __E1000_RESETTING, 473a90b412cSBruce Allan __E1000_ACCESS_SHARED_RESOURCE, 474dee1ad47SJeff Kirsher __E1000_DOWN 475dee1ad47SJeff Kirsher }; 476dee1ad47SJeff Kirsher 477dee1ad47SJeff Kirsher enum latency_range { 478dee1ad47SJeff Kirsher lowest_latency = 0, 479dee1ad47SJeff Kirsher low_latency = 1, 480dee1ad47SJeff Kirsher bulk_latency = 2, 481dee1ad47SJeff Kirsher latency_invalid = 255 482dee1ad47SJeff Kirsher }; 483dee1ad47SJeff Kirsher 484dee1ad47SJeff Kirsher extern char e1000e_driver_name[]; 485dee1ad47SJeff Kirsher extern const char e1000e_driver_version[]; 486dee1ad47SJeff Kirsher 4875ccc921aSJoe Perches void e1000e_check_options(struct e1000_adapter *adapter); 4885ccc921aSJoe Perches void e1000e_set_ethtool_ops(struct net_device *netdev); 489dee1ad47SJeff Kirsher 490d5ea45daSStefan Assmann int e1000e_open(struct net_device *netdev); 491d5ea45daSStefan Assmann int e1000e_close(struct net_device *netdev); 492386164d9SAlexander Duyck void e1000e_up(struct e1000_adapter *adapter); 49328002099SDavid Ertman void e1000e_down(struct e1000_adapter *adapter, bool reset); 4945ccc921aSJoe Perches void e1000e_reinit_locked(struct e1000_adapter *adapter); 4955ccc921aSJoe Perches void e1000e_reset(struct e1000_adapter *adapter); 4965ccc921aSJoe Perches void e1000e_power_up_phy(struct e1000_adapter *adapter); 4975ccc921aSJoe Perches int e1000e_setup_rx_resources(struct e1000_ring *ring); 4985ccc921aSJoe Perches int e1000e_setup_tx_resources(struct e1000_ring *ring); 4995ccc921aSJoe Perches void e1000e_free_rx_resources(struct e1000_ring *ring); 5005ccc921aSJoe Perches void e1000e_free_tx_resources(struct e1000_ring *ring); 501bc1f4470Sstephen hemminger void e1000e_get_stats64(struct net_device *netdev, 5025ccc921aSJoe Perches struct rtnl_link_stats64 *stats); 5035ccc921aSJoe Perches void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 5045ccc921aSJoe Perches void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 5055ccc921aSJoe Perches void e1000e_get_hw_control(struct e1000_adapter *adapter); 5065ccc921aSJoe Perches void e1000e_release_hw_control(struct e1000_adapter *adapter); 5075ccc921aSJoe Perches void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 508dee1ad47SJeff Kirsher 509dee1ad47SJeff Kirsher extern unsigned int copybreak; 510dee1ad47SJeff Kirsher 5118ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_82571_info; 5128ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_82572_info; 5138ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_82573_info; 5148ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_82574_info; 5158ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_82583_info; 5168ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_ich8_info; 5178ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_ich9_info; 5188ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_ich10_info; 5198ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_pch_info; 5208ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_pch2_info; 5212fbe4526SBruce Allan extern const struct e1000_info e1000_pch_lpt_info; 52279849ebcSDavid Ertman extern const struct e1000_info e1000_pch_spt_info; 5233a3173b9SSasha Neftin extern const struct e1000_info e1000_pch_cnp_info; 5248ce9d6c7SJeff Kirsher extern const struct e1000_info e1000_es2_info; 525dee1ad47SJeff Kirsher 5265ccc921aSJoe Perches void e1000e_ptp_init(struct e1000_adapter *adapter); 5275ccc921aSJoe Perches void e1000e_ptp_remove(struct e1000_adapter *adapter); 528dee1ad47SJeff Kirsher 529dee1ad47SJeff Kirsher static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 530dee1ad47SJeff Kirsher { 531dee1ad47SJeff Kirsher return hw->phy.ops.reset(hw); 532dee1ad47SJeff Kirsher } 533dee1ad47SJeff Kirsher 534dee1ad47SJeff Kirsher static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 535dee1ad47SJeff Kirsher { 536dee1ad47SJeff Kirsher return hw->phy.ops.read_reg(hw, offset, data); 537dee1ad47SJeff Kirsher } 538dee1ad47SJeff Kirsher 539f1430d69SBruce Allan static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 540f1430d69SBruce Allan { 541f1430d69SBruce Allan return hw->phy.ops.read_reg_locked(hw, offset, data); 542f1430d69SBruce Allan } 543f1430d69SBruce Allan 544dee1ad47SJeff Kirsher static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 545dee1ad47SJeff Kirsher { 546dee1ad47SJeff Kirsher return hw->phy.ops.write_reg(hw, offset, data); 547dee1ad47SJeff Kirsher } 548dee1ad47SJeff Kirsher 549f1430d69SBruce Allan static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 550f1430d69SBruce Allan { 551f1430d69SBruce Allan return hw->phy.ops.write_reg_locked(hw, offset, data); 552f1430d69SBruce Allan } 553f1430d69SBruce Allan 5545ccc921aSJoe Perches void e1000e_reload_nvm_generic(struct e1000_hw *hw); 555dee1ad47SJeff Kirsher 556dee1ad47SJeff Kirsher static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 557dee1ad47SJeff Kirsher { 558dee1ad47SJeff Kirsher if (hw->mac.ops.read_mac_addr) 559dee1ad47SJeff Kirsher return hw->mac.ops.read_mac_addr(hw); 560dee1ad47SJeff Kirsher 561dee1ad47SJeff Kirsher return e1000_read_mac_addr_generic(hw); 562dee1ad47SJeff Kirsher } 563dee1ad47SJeff Kirsher 564dee1ad47SJeff Kirsher static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 565dee1ad47SJeff Kirsher { 566dee1ad47SJeff Kirsher return hw->nvm.ops.validate(hw); 567dee1ad47SJeff Kirsher } 568dee1ad47SJeff Kirsher 569dee1ad47SJeff Kirsher static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 570dee1ad47SJeff Kirsher { 571dee1ad47SJeff Kirsher return hw->nvm.ops.update(hw); 572dee1ad47SJeff Kirsher } 573dee1ad47SJeff Kirsher 574c29c3ba5SBruce Allan static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 575c29c3ba5SBruce Allan u16 *data) 576dee1ad47SJeff Kirsher { 577dee1ad47SJeff Kirsher return hw->nvm.ops.read(hw, offset, words, data); 578dee1ad47SJeff Kirsher } 579dee1ad47SJeff Kirsher 580c29c3ba5SBruce Allan static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 581c29c3ba5SBruce Allan u16 *data) 582dee1ad47SJeff Kirsher { 583dee1ad47SJeff Kirsher return hw->nvm.ops.write(hw, offset, words, data); 584dee1ad47SJeff Kirsher } 585dee1ad47SJeff Kirsher 586dee1ad47SJeff Kirsher static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 587dee1ad47SJeff Kirsher { 588dee1ad47SJeff Kirsher return hw->phy.ops.get_info(hw); 589dee1ad47SJeff Kirsher } 590dee1ad47SJeff Kirsher 591dee1ad47SJeff Kirsher static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 592dee1ad47SJeff Kirsher { 593dee1ad47SJeff Kirsher return readl(hw->hw_addr + reg); 594dee1ad47SJeff Kirsher } 595dee1ad47SJeff Kirsher 596bdc125f7SBruce Allan #define er32(reg) __er32(hw, E1000_##reg) 597bdc125f7SBruce Allan 598c6f3148cSAndi Kleen s32 __ew32_prepare(struct e1000_hw *hw); 599c6f3148cSAndi Kleen void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 600dee1ad47SJeff Kirsher 601bdc125f7SBruce Allan #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 602bdc125f7SBruce Allan 603bdc125f7SBruce Allan #define e1e_flush() er32(STATUS) 604bdc125f7SBruce Allan 605bdc125f7SBruce Allan #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 606bdc125f7SBruce Allan (__ew32((a), (reg + ((offset) << 2)), (value))) 607bdc125f7SBruce Allan 608bdc125f7SBruce Allan #define E1000_READ_REG_ARRAY(a, reg, offset) \ 609bdc125f7SBruce Allan (readl((a)->hw_addr + reg + ((offset) << 2))) 610bdc125f7SBruce Allan 611dee1ad47SJeff Kirsher #endif /* _E1000_H_ */ 612