1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2511e6bc0Shuangdaode /* 3511e6bc0Shuangdaode * Copyright (c) 2014-2015 Hisilicon Limited. 4511e6bc0Shuangdaode */ 5511e6bc0Shuangdaode 6511e6bc0Shuangdaode #ifndef _HNS_GMAC_H 7511e6bc0Shuangdaode #define _HNS_GMAC_H 8511e6bc0Shuangdaode 9511e6bc0Shuangdaode #include "hns_dsaf_mac.h" 10511e6bc0Shuangdaode 11511e6bc0Shuangdaode enum hns_port_mode { 12511e6bc0Shuangdaode GMAC_10M_MII = 0, 13511e6bc0Shuangdaode GMAC_100M_MII, 14511e6bc0Shuangdaode GMAC_1000M_GMII, 15511e6bc0Shuangdaode GMAC_10M_RGMII, 16511e6bc0Shuangdaode GMAC_100M_RGMII, 17511e6bc0Shuangdaode GMAC_1000M_RGMII, 18511e6bc0Shuangdaode GMAC_10M_SGMII, 19511e6bc0Shuangdaode GMAC_100M_SGMII, 20511e6bc0Shuangdaode GMAC_1000M_SGMII, 21511e6bc0Shuangdaode GMAC_10000M_SGMII /* 10GE */ 22511e6bc0Shuangdaode }; 23511e6bc0Shuangdaode 24511e6bc0Shuangdaode enum hns_gmac_duplex_mdoe { 25511e6bc0Shuangdaode GMAC_HALF_DUPLEX_MODE = 0, 26511e6bc0Shuangdaode GMAC_FULL_DUPLEX_MODE 27511e6bc0Shuangdaode }; 28511e6bc0Shuangdaode 29511e6bc0Shuangdaode struct hns_gmac_port_mode_cfg { 30511e6bc0Shuangdaode enum hns_port_mode port_mode; 31511e6bc0Shuangdaode u32 max_frm_size; 32511e6bc0Shuangdaode u32 short_runts_thr; 33511e6bc0Shuangdaode u32 pad_enable; 34511e6bc0Shuangdaode u32 crc_add; 35511e6bc0Shuangdaode u32 an_enable; /*auto-nego enable */ 36511e6bc0Shuangdaode u32 runt_pkt_en; 37511e6bc0Shuangdaode u32 strip_pad_en; 38511e6bc0Shuangdaode }; 39511e6bc0Shuangdaode 40511e6bc0Shuangdaode #define ETH_GMAC_DUMP_NUM 96 41511e6bc0Shuangdaode #endif /* __HNS_GMAC_H__ */ 42