1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ec21e2ecSJeff Kirsher #ifndef FS_ENET_FEC_H 3ec21e2ecSJeff Kirsher #define FS_ENET_FEC_H 4ec21e2ecSJeff Kirsher 5ec21e2ecSJeff Kirsher #define FEC_MAX_MULTICAST_ADDRS 64 6ec21e2ecSJeff Kirsher 7ec21e2ecSJeff Kirsher /* Interrupt events/masks. 8ec21e2ecSJeff Kirsher */ 9ec21e2ecSJeff Kirsher #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */ 10ec21e2ecSJeff Kirsher #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */ 11ec21e2ecSJeff Kirsher #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */ 12ec21e2ecSJeff Kirsher #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */ 13ec21e2ecSJeff Kirsher #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */ 14ec21e2ecSJeff Kirsher #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */ 15ec21e2ecSJeff Kirsher #define FEC_ENET_RXF 0x02000000U /* Full frame received */ 16ec21e2ecSJeff Kirsher #define FEC_ENET_RXB 0x01000000U /* A buffer was received */ 17ec21e2ecSJeff Kirsher #define FEC_ENET_MII 0x00800000U /* MII interrupt */ 18ec21e2ecSJeff Kirsher #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */ 19ec21e2ecSJeff Kirsher 20ec21e2ecSJeff Kirsher #define FEC_ECNTRL_PINMUX 0x00000004 21ec21e2ecSJeff Kirsher #define FEC_ECNTRL_ETHER_EN 0x00000002 22ec21e2ecSJeff Kirsher #define FEC_ECNTRL_RESET 0x00000001 23ec21e2ecSJeff Kirsher 24ba568335SVladimir Ermakov /* RMII mode enabled only when MII_MODE bit is set too. */ 25ba568335SVladimir Ermakov #define FEC_RCNTRL_RMII_MODE (0x00000100 | \ 26ba568335SVladimir Ermakov FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE) 27ba568335SVladimir Ermakov #define FEC_RCNTRL_FCE 0x00000020 28ec21e2ecSJeff Kirsher #define FEC_RCNTRL_BC_REJ 0x00000010 29ec21e2ecSJeff Kirsher #define FEC_RCNTRL_PROM 0x00000008 30ec21e2ecSJeff Kirsher #define FEC_RCNTRL_MII_MODE 0x00000004 31ec21e2ecSJeff Kirsher #define FEC_RCNTRL_DRT 0x00000002 32ec21e2ecSJeff Kirsher #define FEC_RCNTRL_LOOP 0x00000001 33ec21e2ecSJeff Kirsher 34ec21e2ecSJeff Kirsher #define FEC_TCNTRL_FDEN 0x00000004 35ec21e2ecSJeff Kirsher #define FEC_TCNTRL_HBC 0x00000002 36ec21e2ecSJeff Kirsher #define FEC_TCNTRL_GTS 0x00000001 37ec21e2ecSJeff Kirsher 38ec21e2ecSJeff Kirsher /* 39ec21e2ecSJeff Kirsher * Delay to wait for FEC reset command to complete (in us) 40ec21e2ecSJeff Kirsher */ 41ec21e2ecSJeff Kirsher #define FEC_RESET_DELAY 50 42ec21e2ecSJeff Kirsher #endif 43