14ec4762dSRahul Lakkireddy /* SPDX-License-Identifier: GPL-2.0-only */ 24ec4762dSRahul Lakkireddy /* Copyright (C) 2019 Chelsio Communications. All rights reserved. */ 34ec4762dSRahul Lakkireddy 44ec4762dSRahul Lakkireddy #ifndef __CXGB4_TC_MATCHALL_H__ 54ec4762dSRahul Lakkireddy #define __CXGB4_TC_MATCHALL_H__ 64ec4762dSRahul Lakkireddy 74ec4762dSRahul Lakkireddy #include <net/pkt_cls.h> 84ec4762dSRahul Lakkireddy 94ec4762dSRahul Lakkireddy enum cxgb4_matchall_state { 104ec4762dSRahul Lakkireddy CXGB4_MATCHALL_STATE_DISABLED = 0, 114ec4762dSRahul Lakkireddy CXGB4_MATCHALL_STATE_ENABLED, 124ec4762dSRahul Lakkireddy }; 134ec4762dSRahul Lakkireddy 144ec4762dSRahul Lakkireddy struct cxgb4_matchall_egress_entry { 154ec4762dSRahul Lakkireddy enum cxgb4_matchall_state state; /* Current MATCHALL offload state */ 164ec4762dSRahul Lakkireddy u8 hwtc; /* Traffic class bound to port */ 174ec4762dSRahul Lakkireddy u64 cookie; /* Used to identify the MATCHALL rule offloaded */ 184ec4762dSRahul Lakkireddy }; 194ec4762dSRahul Lakkireddy 2021c4c60bSRahul Lakkireddy struct cxgb4_matchall_ingress_entry { 2121c4c60bSRahul Lakkireddy enum cxgb4_matchall_state state; /* Current MATCHALL offload state */ 22*59b328cfSRahul Lakkireddy u32 tid[CXGB4_FILTER_TYPE_MAX]; /* Index to hardware filter entries */ 23*59b328cfSRahul Lakkireddy /* Filter entries */ 24*59b328cfSRahul Lakkireddy struct ch_filter_specification fs[CXGB4_FILTER_TYPE_MAX]; 25fd2261d8SRahul Lakkireddy u16 viid_mirror; /* Identifier for allocated Mirror VI */ 2621c4c60bSRahul Lakkireddy u64 bytes; /* # of bytes hitting the filter */ 2721c4c60bSRahul Lakkireddy u64 packets; /* # of packets hitting the filter */ 2821c4c60bSRahul Lakkireddy u64 last_used; /* Last updated jiffies time */ 2921c4c60bSRahul Lakkireddy }; 3021c4c60bSRahul Lakkireddy 314ec4762dSRahul Lakkireddy struct cxgb4_tc_port_matchall { 324ec4762dSRahul Lakkireddy struct cxgb4_matchall_egress_entry egress; /* Egress offload info */ 3321c4c60bSRahul Lakkireddy struct cxgb4_matchall_ingress_entry ingress; /* Ingress offload info */ 344ec4762dSRahul Lakkireddy }; 354ec4762dSRahul Lakkireddy 364ec4762dSRahul Lakkireddy struct cxgb4_tc_matchall { 374ec4762dSRahul Lakkireddy struct cxgb4_tc_port_matchall *port_matchall; /* Per port entry */ 384ec4762dSRahul Lakkireddy }; 394ec4762dSRahul Lakkireddy 404ec4762dSRahul Lakkireddy int cxgb4_tc_matchall_replace(struct net_device *dev, 4121c4c60bSRahul Lakkireddy struct tc_cls_matchall_offload *cls_matchall, 4221c4c60bSRahul Lakkireddy bool ingress); 434ec4762dSRahul Lakkireddy int cxgb4_tc_matchall_destroy(struct net_device *dev, 4421c4c60bSRahul Lakkireddy struct tc_cls_matchall_offload *cls_matchall, 4521c4c60bSRahul Lakkireddy bool ingress); 4621c4c60bSRahul Lakkireddy int cxgb4_tc_matchall_stats(struct net_device *dev, 474ec4762dSRahul Lakkireddy struct tc_cls_matchall_offload *cls_matchall); 484ec4762dSRahul Lakkireddy 494ec4762dSRahul Lakkireddy int cxgb4_init_tc_matchall(struct adapter *adap); 504ec4762dSRahul Lakkireddy void cxgb4_cleanup_tc_matchall(struct adapter *adap); 514ec4762dSRahul Lakkireddy #endif /* __CXGB4_TC_MATCHALL_H__ */ 52