1f21fb3edSRaghu Vatsavayi /********************************************************************** 2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc. 3f21fb3edSRaghu Vatsavayi * 4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com 5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject. 6f21fb3edSRaghu Vatsavayi * 7*50579d3dSRaghu Vatsavayi * Copyright (c) 2003-2016 Cavium, Inc. 8f21fb3edSRaghu Vatsavayi * 9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation. 12f21fb3edSRaghu Vatsavayi * 13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16*50579d3dSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more details. 17*50579d3dSRaghu Vatsavayi ***********************************************************************/ 18f21fb3edSRaghu Vatsavayi /*! \file cn68xx_regs.h 19f21fb3edSRaghu Vatsavayi * \brief Host Driver: Register Address and Register Mask values for 20f21fb3edSRaghu Vatsavayi * Octeon CN68XX devices. The register map for CN66XX is the same 21f21fb3edSRaghu Vatsavayi * for most registers. This file has the other registers that are 22f21fb3edSRaghu Vatsavayi * 68XX-specific. 23f21fb3edSRaghu Vatsavayi */ 24f21fb3edSRaghu Vatsavayi 25f21fb3edSRaghu Vatsavayi #ifndef __CN68XX_REGS_H__ 26f21fb3edSRaghu Vatsavayi #define __CN68XX_REGS_H__ 27f21fb3edSRaghu Vatsavayi 28f21fb3edSRaghu Vatsavayi /*###################### REQUEST QUEUE #########################*/ 29f21fb3edSRaghu Vatsavayi 30f21fb3edSRaghu Vatsavayi #define CN68XX_SLI_IQ_PORT0_PKIND 0x0800 31f21fb3edSRaghu Vatsavayi 32f21fb3edSRaghu Vatsavayi #define CN68XX_SLI_IQ_PORT_PKIND(iq) \ 33f21fb3edSRaghu Vatsavayi (CN68XX_SLI_IQ_PORT0_PKIND + ((iq) * CN6XXX_IQ_OFFSET)) 34f21fb3edSRaghu Vatsavayi 35f21fb3edSRaghu Vatsavayi /*############################ OUTPUT QUEUE #########################*/ 36f21fb3edSRaghu Vatsavayi 37f21fb3edSRaghu Vatsavayi /* Starting pipe number and number of pipes used by the SLI packet output. */ 38f21fb3edSRaghu Vatsavayi #define CN68XX_SLI_TX_PIPE 0x1230 39f21fb3edSRaghu Vatsavayi 40f21fb3edSRaghu Vatsavayi /*######################## INTERRUPTS #########################*/ 41f21fb3edSRaghu Vatsavayi 42f21fb3edSRaghu Vatsavayi /*------------------ Interrupt Masks ----------------*/ 43f21fb3edSRaghu Vatsavayi #define CN68XX_INTR_PIPE_ERR BIT_ULL(61) 44f21fb3edSRaghu Vatsavayi 45f21fb3edSRaghu Vatsavayi #endif 46