xref: /openbmc/linux/drivers/net/ethernet/brocade/bna/bfi.h (revision 1bf9fd70dd7411372e80fdb8b4b3d5c36236e7b7)
1f844a0eaSJeff Kirsher /*
2f844a0eaSJeff Kirsher  * Linux network driver for Brocade Converged Network Adapter.
3f844a0eaSJeff Kirsher  *
4f844a0eaSJeff Kirsher  * This program is free software; you can redistribute it and/or modify it
5f844a0eaSJeff Kirsher  * under the terms of the GNU General Public License (GPL) Version 2 as
6f844a0eaSJeff Kirsher  * published by the Free Software Foundation
7f844a0eaSJeff Kirsher  *
8f844a0eaSJeff Kirsher  * This program is distributed in the hope that it will be useful, but
9f844a0eaSJeff Kirsher  * WITHOUT ANY WARRANTY; without even the implied warranty of
10f844a0eaSJeff Kirsher  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
11f844a0eaSJeff Kirsher  * General Public License for more details.
12f844a0eaSJeff Kirsher  */
13f844a0eaSJeff Kirsher /*
14f844a0eaSJeff Kirsher  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15f844a0eaSJeff Kirsher  * All rights reserved
16f844a0eaSJeff Kirsher  * www.brocade.com
17f844a0eaSJeff Kirsher  */
18f844a0eaSJeff Kirsher #ifndef __BFI_H__
19f844a0eaSJeff Kirsher #define __BFI_H__
20f844a0eaSJeff Kirsher 
21f844a0eaSJeff Kirsher #include "bfa_defs.h"
22f844a0eaSJeff Kirsher 
23f844a0eaSJeff Kirsher #pragma pack(1)
24f844a0eaSJeff Kirsher 
25f844a0eaSJeff Kirsher /**
26f844a0eaSJeff Kirsher  * BFI FW image type
27f844a0eaSJeff Kirsher  */
28f844a0eaSJeff Kirsher #define	BFI_FLASH_CHUNK_SZ			256	/*!< Flash chunk size */
29f844a0eaSJeff Kirsher #define	BFI_FLASH_CHUNK_SZ_WORDS	(BFI_FLASH_CHUNK_SZ/sizeof(u32))
30f844a0eaSJeff Kirsher 
31f844a0eaSJeff Kirsher /**
32f844a0eaSJeff Kirsher  * Msg header common to all msgs
33f844a0eaSJeff Kirsher  */
34f844a0eaSJeff Kirsher struct bfi_mhdr {
35f844a0eaSJeff Kirsher 	u8		msg_class;	/*!< @ref enum bfi_mclass	    */
36f844a0eaSJeff Kirsher 	u8		msg_id;		/*!< msg opcode with in the class   */
37f844a0eaSJeff Kirsher 	union {
38f844a0eaSJeff Kirsher 		struct {
39078086f3SRasesh Mody 			u8	qid;
40078086f3SRasesh Mody 			u8	fn_lpu;	/*!< msg destination		    */
41f844a0eaSJeff Kirsher 		} h2i;
42f844a0eaSJeff Kirsher 		u16	i2htok;	/*!< token in msgs to host	    */
43f844a0eaSJeff Kirsher 	} mtag;
44f844a0eaSJeff Kirsher };
45f844a0eaSJeff Kirsher 
46078086f3SRasesh Mody #define bfi_fn_lpu(__fn, __lpu)	((__fn) << 1 | (__lpu))
47078086f3SRasesh Mody #define bfi_mhdr_2_fn(_mh)	((_mh)->mtag.h2i.fn_lpu >> 1)
48078086f3SRasesh Mody #define bfi_mhdr_2_qid(_mh)	((_mh)->mtag.h2i.qid)
49078086f3SRasesh Mody 
50078086f3SRasesh Mody #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do {		\
51f844a0eaSJeff Kirsher 	(_mh).msg_class			= (_mc);		\
52f844a0eaSJeff Kirsher 	(_mh).msg_id			= (_op);		\
53078086f3SRasesh Mody 	(_mh).mtag.h2i.fn_lpu	= (_fn_lpu);			\
54f844a0eaSJeff Kirsher } while (0)
55f844a0eaSJeff Kirsher 
56f844a0eaSJeff Kirsher #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do {		\
57f844a0eaSJeff Kirsher 	(_mh).msg_class			= (_mc);		\
58f844a0eaSJeff Kirsher 	(_mh).msg_id			= (_op);		\
59f844a0eaSJeff Kirsher 	(_mh).mtag.i2htok		= (_i2htok);		\
60f844a0eaSJeff Kirsher } while (0)
61f844a0eaSJeff Kirsher 
62f844a0eaSJeff Kirsher /*
63f844a0eaSJeff Kirsher  * Message opcodes: 0-127 to firmware, 128-255 to host
64f844a0eaSJeff Kirsher  */
65f844a0eaSJeff Kirsher #define BFI_I2H_OPCODE_BASE	128
66f844a0eaSJeff Kirsher #define BFA_I2HM(_x)			((_x) + BFI_I2H_OPCODE_BASE)
67f844a0eaSJeff Kirsher 
68f844a0eaSJeff Kirsher /**
69f844a0eaSJeff Kirsher  ****************************************************************************
70f844a0eaSJeff Kirsher  *
71f844a0eaSJeff Kirsher  * Scatter Gather Element and Page definition
72f844a0eaSJeff Kirsher  *
73f844a0eaSJeff Kirsher  ****************************************************************************
74f844a0eaSJeff Kirsher  */
75f844a0eaSJeff Kirsher 
76f844a0eaSJeff Kirsher /**
77f844a0eaSJeff Kirsher  * DMA addresses
78f844a0eaSJeff Kirsher  */
79f844a0eaSJeff Kirsher union bfi_addr_u {
80f844a0eaSJeff Kirsher 	struct {
81f844a0eaSJeff Kirsher 		u32	addr_lo;
82f844a0eaSJeff Kirsher 		u32	addr_hi;
83f844a0eaSJeff Kirsher 	} a32;
84f844a0eaSJeff Kirsher };
85f844a0eaSJeff Kirsher 
86f844a0eaSJeff Kirsher /*
87f844a0eaSJeff Kirsher  * Large Message structure - 128 Bytes size Msgs
88f844a0eaSJeff Kirsher  */
89f844a0eaSJeff Kirsher #define BFI_LMSG_SZ		128
90f844a0eaSJeff Kirsher #define BFI_LMSG_PL_WSZ	\
91f844a0eaSJeff Kirsher 			((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
92f844a0eaSJeff Kirsher 
93f844a0eaSJeff Kirsher /**
94f844a0eaSJeff Kirsher  * Mailbox message structure
95f844a0eaSJeff Kirsher  */
96f844a0eaSJeff Kirsher #define BFI_MBMSG_SZ		7
97f844a0eaSJeff Kirsher struct bfi_mbmsg {
98f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;
99f844a0eaSJeff Kirsher 	u32		pl[BFI_MBMSG_SZ];
100f844a0eaSJeff Kirsher };
101f844a0eaSJeff Kirsher 
102f844a0eaSJeff Kirsher /**
103078086f3SRasesh Mody  * Supported PCI function class codes (personality)
104078086f3SRasesh Mody  */
105078086f3SRasesh Mody enum bfi_pcifn_class {
106078086f3SRasesh Mody 	BFI_PCIFN_CLASS_FC	= 0x0c04,
107078086f3SRasesh Mody 	BFI_PCIFN_CLASS_ETH	= 0x0200,
108078086f3SRasesh Mody };
109078086f3SRasesh Mody 
110078086f3SRasesh Mody /**
111f844a0eaSJeff Kirsher  * Message Classes
112f844a0eaSJeff Kirsher  */
113f844a0eaSJeff Kirsher enum bfi_mclass {
114f844a0eaSJeff Kirsher 	BFI_MC_IOC		= 1,	/*!< IO Controller (IOC)	    */
115f844a0eaSJeff Kirsher 	BFI_MC_DIAG		= 2,	/*!< Diagnostic Msgs		    */
116f844a0eaSJeff Kirsher 	BFI_MC_FLASH		= 3,	/*!< Flash message class	    */
117f844a0eaSJeff Kirsher 	BFI_MC_CEE		= 4,	/*!< CEE			    */
118f844a0eaSJeff Kirsher 	BFI_MC_FCPORT		= 5,	/*!< FC port			    */
119f844a0eaSJeff Kirsher 	BFI_MC_IOCFC		= 6,	/*!< FC - IO Controller (IOC)	    */
120f844a0eaSJeff Kirsher 	BFI_MC_LL		= 7,	/*!< Link Layer			    */
121f844a0eaSJeff Kirsher 	BFI_MC_UF		= 8,	/*!< Unsolicited frame receive	    */
122f844a0eaSJeff Kirsher 	BFI_MC_FCXP		= 9,	/*!< FC Transport		    */
123f844a0eaSJeff Kirsher 	BFI_MC_LPS		= 10,	/*!< lport fc login services	    */
124f844a0eaSJeff Kirsher 	BFI_MC_RPORT		= 11,	/*!< Remote port		    */
125f844a0eaSJeff Kirsher 	BFI_MC_ITNIM		= 12,	/*!< I-T nexus (Initiator mode)	    */
126f844a0eaSJeff Kirsher 	BFI_MC_IOIM_READ	= 13,	/*!< read IO (Initiator mode)	    */
127f844a0eaSJeff Kirsher 	BFI_MC_IOIM_WRITE	= 14,	/*!< write IO (Initiator mode)	    */
128f844a0eaSJeff Kirsher 	BFI_MC_IOIM_IO		= 15,	/*!< IO (Initiator mode)	    */
129f844a0eaSJeff Kirsher 	BFI_MC_IOIM		= 16,	/*!< IO (Initiator mode)	    */
130f844a0eaSJeff Kirsher 	BFI_MC_IOIM_IOCOM	= 17,	/*!< good IO completion		    */
131f844a0eaSJeff Kirsher 	BFI_MC_TSKIM		= 18,	/*!< Initiator Task management	    */
132f844a0eaSJeff Kirsher 	BFI_MC_SBOOT		= 19,	/*!< SAN boot services		    */
133f844a0eaSJeff Kirsher 	BFI_MC_IPFC		= 20,	/*!< IP over FC Msgs		    */
134f844a0eaSJeff Kirsher 	BFI_MC_PORT		= 21,	/*!< Physical port		    */
135f844a0eaSJeff Kirsher 	BFI_MC_SFP		= 22,	/*!< SFP module			    */
136f844a0eaSJeff Kirsher 	BFI_MC_MSGQ		= 23,	/*!< MSGQ			    */
137f844a0eaSJeff Kirsher 	BFI_MC_ENET		= 24,	/*!< ENET commands/responses	    */
138f844a0eaSJeff Kirsher 	BFI_MC_MAX		= 32
139f844a0eaSJeff Kirsher };
140f844a0eaSJeff Kirsher 
141f844a0eaSJeff Kirsher #define BFI_IOC_MAX_CQS		4
142f844a0eaSJeff Kirsher #define BFI_IOC_MAX_CQS_ASIC	8
143f844a0eaSJeff Kirsher #define BFI_IOC_MSGLEN_MAX	32	/* 32 bytes */
144f844a0eaSJeff Kirsher 
145af027a34SRasesh Mody #define BFI_FWBOOT_ENV_OS		0
146af027a34SRasesh Mody 
147f844a0eaSJeff Kirsher #define BFI_BOOT_MEMTEST_RES_ADDR   0x900
148f844a0eaSJeff Kirsher #define BFI_BOOT_MEMTEST_RES_SIG    0xA0A1A2A3
149f844a0eaSJeff Kirsher 
150f844a0eaSJeff Kirsher /**
151f844a0eaSJeff Kirsher  *----------------------------------------------------------------------
152f844a0eaSJeff Kirsher  *				IOC
153f844a0eaSJeff Kirsher  *----------------------------------------------------------------------
154f844a0eaSJeff Kirsher  */
155f844a0eaSJeff Kirsher 
156078086f3SRasesh Mody /**
157078086f3SRasesh Mody  * Different asic generations
158078086f3SRasesh Mody  */
159078086f3SRasesh Mody enum bfi_asic_gen {
160078086f3SRasesh Mody 	BFI_ASIC_GEN_CB		= 1,
161078086f3SRasesh Mody 	BFI_ASIC_GEN_CT		= 2,
162*1bf9fd70SRasesh Mody 	BFI_ASIC_GEN_CT2	= 3,
163078086f3SRasesh Mody };
164078086f3SRasesh Mody 
165078086f3SRasesh Mody enum bfi_asic_mode {
166078086f3SRasesh Mody 	BFI_ASIC_MODE_FC	= 1,	/* FC upto 8G speed		*/
167078086f3SRasesh Mody 	BFI_ASIC_MODE_FC16	= 2,	/* FC upto 16G speed		*/
168078086f3SRasesh Mody 	BFI_ASIC_MODE_ETH	= 3,	/* Ethernet ports		*/
169078086f3SRasesh Mody 	BFI_ASIC_MODE_COMBO	= 4,	/* FC 16G and Ethernet 10G port	*/
170078086f3SRasesh Mody };
171078086f3SRasesh Mody 
172f844a0eaSJeff Kirsher enum bfi_ioc_h2i_msgs {
173f844a0eaSJeff Kirsher 	BFI_IOC_H2I_ENABLE_REQ		= 1,
174f844a0eaSJeff Kirsher 	BFI_IOC_H2I_DISABLE_REQ		= 2,
175f844a0eaSJeff Kirsher 	BFI_IOC_H2I_GETATTR_REQ		= 3,
176f844a0eaSJeff Kirsher 	BFI_IOC_H2I_DBG_SYNC		= 4,
177f844a0eaSJeff Kirsher 	BFI_IOC_H2I_DBG_DUMP		= 5,
178f844a0eaSJeff Kirsher };
179f844a0eaSJeff Kirsher 
180f844a0eaSJeff Kirsher enum bfi_ioc_i2h_msgs {
181f844a0eaSJeff Kirsher 	BFI_IOC_I2H_ENABLE_REPLY	= BFA_I2HM(1),
182f844a0eaSJeff Kirsher 	BFI_IOC_I2H_DISABLE_REPLY	= BFA_I2HM(2),
183f844a0eaSJeff Kirsher 	BFI_IOC_I2H_GETATTR_REPLY	= BFA_I2HM(3),
184078086f3SRasesh Mody 	BFI_IOC_I2H_HBEAT		= BFA_I2HM(4),
185f844a0eaSJeff Kirsher };
186f844a0eaSJeff Kirsher 
187f844a0eaSJeff Kirsher /**
188f844a0eaSJeff Kirsher  * BFI_IOC_H2I_GETATTR_REQ message
189f844a0eaSJeff Kirsher  */
190f844a0eaSJeff Kirsher struct bfi_ioc_getattr_req {
191f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;
192f844a0eaSJeff Kirsher 	union bfi_addr_u	attr_addr;
193f844a0eaSJeff Kirsher };
194f844a0eaSJeff Kirsher 
195f844a0eaSJeff Kirsher struct bfi_ioc_attr {
196f844a0eaSJeff Kirsher 	u64		mfg_pwwn;	/*!< Mfg port wwn	   */
197f844a0eaSJeff Kirsher 	u64		mfg_nwwn;	/*!< Mfg node wwn	   */
198f844a0eaSJeff Kirsher 	mac_t		mfg_mac;	/*!< Mfg mac		   */
199078086f3SRasesh Mody 	u8		port_mode;	/* enum bfi_port_mode	   */
200078086f3SRasesh Mody 	u8		rsvd_a;
201f844a0eaSJeff Kirsher 	u64		pwwn;
202f844a0eaSJeff Kirsher 	u64		nwwn;
203f844a0eaSJeff Kirsher 	mac_t		mac;		/*!< PBC or Mfg mac	   */
204f844a0eaSJeff Kirsher 	u16	rsvd_b;
205f844a0eaSJeff Kirsher 	mac_t		fcoe_mac;
206f844a0eaSJeff Kirsher 	u16	rsvd_c;
207f844a0eaSJeff Kirsher 	char		brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
208f844a0eaSJeff Kirsher 	u8		pcie_gen;
209f844a0eaSJeff Kirsher 	u8		pcie_lanes_orig;
210f844a0eaSJeff Kirsher 	u8		pcie_lanes;
211f844a0eaSJeff Kirsher 	u8		rx_bbcredit;	/*!< receive buffer credits */
212f844a0eaSJeff Kirsher 	u32	adapter_prop;	/*!< adapter properties     */
213f844a0eaSJeff Kirsher 	u16	maxfrsize;	/*!< max receive frame size */
214f844a0eaSJeff Kirsher 	char		asic_rev;
215f844a0eaSJeff Kirsher 	u8		rsvd_d;
216f844a0eaSJeff Kirsher 	char		fw_version[BFA_VERSION_LEN];
217f844a0eaSJeff Kirsher 	char		optrom_version[BFA_VERSION_LEN];
218f844a0eaSJeff Kirsher 	struct bfa_mfg_vpd vpd;
219f844a0eaSJeff Kirsher 	u32	card_type;	/*!< card type			*/
220f844a0eaSJeff Kirsher };
221f844a0eaSJeff Kirsher 
222f844a0eaSJeff Kirsher /**
223f844a0eaSJeff Kirsher  * BFI_IOC_I2H_GETATTR_REPLY message
224f844a0eaSJeff Kirsher  */
225f844a0eaSJeff Kirsher struct bfi_ioc_getattr_reply {
226f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;	/*!< Common msg header		*/
227f844a0eaSJeff Kirsher 	u8			status;	/*!< cfg reply status		*/
228f844a0eaSJeff Kirsher 	u8			rsvd[3];
229f844a0eaSJeff Kirsher };
230f844a0eaSJeff Kirsher 
231f844a0eaSJeff Kirsher /**
232f844a0eaSJeff Kirsher  * Firmware memory page offsets
233f844a0eaSJeff Kirsher  */
234f844a0eaSJeff Kirsher #define BFI_IOC_SMEM_PG0_CB	(0x40)
235f844a0eaSJeff Kirsher #define BFI_IOC_SMEM_PG0_CT	(0x180)
236f844a0eaSJeff Kirsher 
237f844a0eaSJeff Kirsher /**
238f844a0eaSJeff Kirsher  * Firmware statistic offset
239f844a0eaSJeff Kirsher  */
240f844a0eaSJeff Kirsher #define BFI_IOC_FWSTATS_OFF	(0x6B40)
241f844a0eaSJeff Kirsher #define BFI_IOC_FWSTATS_SZ	(4096)
242f844a0eaSJeff Kirsher 
243f844a0eaSJeff Kirsher /**
244f844a0eaSJeff Kirsher  * Firmware trace offset
245f844a0eaSJeff Kirsher  */
246f844a0eaSJeff Kirsher #define BFI_IOC_TRC_OFF		(0x4b00)
247f844a0eaSJeff Kirsher #define BFI_IOC_TRC_ENTS	256
248f844a0eaSJeff Kirsher 
249f844a0eaSJeff Kirsher #define BFI_IOC_FW_SIGNATURE	(0xbfadbfad)
250f844a0eaSJeff Kirsher #define BFI_IOC_MD5SUM_SZ	4
251f844a0eaSJeff Kirsher struct bfi_ioc_image_hdr {
252f844a0eaSJeff Kirsher 	u32	signature;	/*!< constant signature */
253078086f3SRasesh Mody 	u8	asic_gen;	/*!< asic generation */
254078086f3SRasesh Mody 	u8	asic_mode;
255078086f3SRasesh Mody 	u8	port0_mode;	/*!< device mode for port 0 */
256078086f3SRasesh Mody 	u8	port1_mode;	/*!< device mode for port 1 */
257f844a0eaSJeff Kirsher 	u32	exec;		/*!< exec vector	*/
258078086f3SRasesh Mody 	u32	bootenv;	/*!< firmware boot env */
259f844a0eaSJeff Kirsher 	u32	rsvd_b[4];
260f844a0eaSJeff Kirsher 	u32	md5sum[BFI_IOC_MD5SUM_SZ];
261f844a0eaSJeff Kirsher };
262f844a0eaSJeff Kirsher 
263078086f3SRasesh Mody #define BFI_FWBOOT_DEVMODE_OFF		4
264078086f3SRasesh Mody #define BFI_FWBOOT_TYPE_OFF		8
265078086f3SRasesh Mody #define BFI_FWBOOT_ENV_OFF		12
266078086f3SRasesh Mody #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
267078086f3SRasesh Mody 	(((u32)(__asic_gen)) << 24 |	\
268078086f3SRasesh Mody 	 ((u32)(__asic_mode)) << 16 |	\
269078086f3SRasesh Mody 	 ((u32)(__p0_mode)) << 8 |	\
270078086f3SRasesh Mody 	 ((u32)(__p1_mode)))
271078086f3SRasesh Mody 
272f844a0eaSJeff Kirsher enum bfi_fwboot_type {
273f844a0eaSJeff Kirsher 	BFI_FWBOOT_TYPE_NORMAL	= 0,
274f844a0eaSJeff Kirsher 	BFI_FWBOOT_TYPE_FLASH	= 1,
275f844a0eaSJeff Kirsher 	BFI_FWBOOT_TYPE_MEMTEST	= 2,
276f844a0eaSJeff Kirsher };
277f844a0eaSJeff Kirsher 
278078086f3SRasesh Mody enum bfi_port_mode {
279078086f3SRasesh Mody 	BFI_PORT_MODE_FC	= 1,
280078086f3SRasesh Mody 	BFI_PORT_MODE_ETH	= 2,
281078086f3SRasesh Mody };
282078086f3SRasesh Mody 
283f844a0eaSJeff Kirsher /**
284f844a0eaSJeff Kirsher  *  BFI_IOC_I2H_READY_EVENT message
285f844a0eaSJeff Kirsher  */
286f844a0eaSJeff Kirsher struct bfi_ioc_hbeat {
287f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;		/*!< common msg header		*/
288f844a0eaSJeff Kirsher 	u32	   hb_count;	/*!< current heart beat count	*/
289f844a0eaSJeff Kirsher };
290f844a0eaSJeff Kirsher 
291f844a0eaSJeff Kirsher /**
292f844a0eaSJeff Kirsher  * IOC hardware/firmware state
293f844a0eaSJeff Kirsher  */
294f844a0eaSJeff Kirsher enum bfi_ioc_state {
295f844a0eaSJeff Kirsher 	BFI_IOC_UNINIT		= 0,	/*!< not initialized		     */
296f844a0eaSJeff Kirsher 	BFI_IOC_INITING		= 1,	/*!< h/w is being initialized	     */
297f844a0eaSJeff Kirsher 	BFI_IOC_HWINIT		= 2,	/*!< h/w is initialized		     */
298f844a0eaSJeff Kirsher 	BFI_IOC_CFG		= 3,	/*!< IOC configuration in progress   */
299f844a0eaSJeff Kirsher 	BFI_IOC_OP		= 4,	/*!< IOC is operational		     */
300f844a0eaSJeff Kirsher 	BFI_IOC_DISABLING	= 5,	/*!< IOC is being disabled	     */
301f844a0eaSJeff Kirsher 	BFI_IOC_DISABLED	= 6,	/*!< IOC is disabled		     */
302f844a0eaSJeff Kirsher 	BFI_IOC_CFG_DISABLED	= 7,	/*!< IOC is being disabled;transient */
303f844a0eaSJeff Kirsher 	BFI_IOC_FAIL		= 8,	/*!< IOC heart-beat failure	     */
304f844a0eaSJeff Kirsher 	BFI_IOC_MEMTEST		= 9,	/*!< IOC is doing memtest	     */
305f844a0eaSJeff Kirsher };
306f844a0eaSJeff Kirsher 
307f844a0eaSJeff Kirsher #define BFI_IOC_ENDIAN_SIG  0x12345678
308f844a0eaSJeff Kirsher 
309f844a0eaSJeff Kirsher enum {
310f844a0eaSJeff Kirsher 	BFI_ADAPTER_TYPE_FC	= 0x01,		/*!< FC adapters	   */
311f844a0eaSJeff Kirsher 	BFI_ADAPTER_TYPE_MK	= 0x0f0000,	/*!< adapter type mask     */
312f844a0eaSJeff Kirsher 	BFI_ADAPTER_TYPE_SH	= 16,	        /*!< adapter type shift    */
313f844a0eaSJeff Kirsher 	BFI_ADAPTER_NPORTS_MK	= 0xff00,	/*!< number of ports mask  */
314f844a0eaSJeff Kirsher 	BFI_ADAPTER_NPORTS_SH	= 8,	        /*!< number of ports shift */
315f844a0eaSJeff Kirsher 	BFI_ADAPTER_SPEED_MK	= 0xff,		/*!< adapter speed mask    */
316f844a0eaSJeff Kirsher 	BFI_ADAPTER_SPEED_SH	= 0,	        /*!< adapter speed shift   */
317f844a0eaSJeff Kirsher 	BFI_ADAPTER_PROTO	= 0x100000,	/*!< prototype adapaters   */
318f844a0eaSJeff Kirsher 	BFI_ADAPTER_TTV		= 0x200000,	/*!< TTV debug capable     */
319f844a0eaSJeff Kirsher 	BFI_ADAPTER_UNSUPP	= 0x400000,	/*!< unknown adapter type  */
320f844a0eaSJeff Kirsher };
321f844a0eaSJeff Kirsher 
322f844a0eaSJeff Kirsher #define BFI_ADAPTER_GETP(__prop, __adap_prop)			\
323f844a0eaSJeff Kirsher 	(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >>	\
324f844a0eaSJeff Kirsher 		BFI_ADAPTER_ ## __prop ## _SH)
325f844a0eaSJeff Kirsher #define BFI_ADAPTER_SETP(__prop, __val)				\
326f844a0eaSJeff Kirsher 	((__val) << BFI_ADAPTER_ ## __prop ## _SH)
327f844a0eaSJeff Kirsher #define BFI_ADAPTER_IS_PROTO(__adap_type)			\
328f844a0eaSJeff Kirsher 	((__adap_type) & BFI_ADAPTER_PROTO)
329f844a0eaSJeff Kirsher #define BFI_ADAPTER_IS_TTV(__adap_type)				\
330f844a0eaSJeff Kirsher 	((__adap_type) & BFI_ADAPTER_TTV)
331f844a0eaSJeff Kirsher #define BFI_ADAPTER_IS_UNSUPP(__adap_type)			\
332f844a0eaSJeff Kirsher 	((__adap_type) & BFI_ADAPTER_UNSUPP)
333f844a0eaSJeff Kirsher #define BFI_ADAPTER_IS_SPECIAL(__adap_type)			\
334f844a0eaSJeff Kirsher 	((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO |	\
335f844a0eaSJeff Kirsher 			BFI_ADAPTER_UNSUPP))
336f844a0eaSJeff Kirsher 
337f844a0eaSJeff Kirsher /**
338f844a0eaSJeff Kirsher  * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
339f844a0eaSJeff Kirsher  */
340f844a0eaSJeff Kirsher struct bfi_ioc_ctrl_req {
341f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;
342078086f3SRasesh Mody 	u16			clscode;
343078086f3SRasesh Mody 	u16			rsvd;
344f844a0eaSJeff Kirsher 	u32		tv_sec;
345f844a0eaSJeff Kirsher };
346f844a0eaSJeff Kirsher 
347f844a0eaSJeff Kirsher /**
348f844a0eaSJeff Kirsher  * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
349f844a0eaSJeff Kirsher  */
350f844a0eaSJeff Kirsher struct bfi_ioc_ctrl_reply {
351f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;			/*!< Common msg header     */
352f844a0eaSJeff Kirsher 	u8			status;		/*!< enable/disable status */
353078086f3SRasesh Mody 	u8			port_mode;	/*!< enum bfa_mode */
354078086f3SRasesh Mody 	u8			cap_bm;		/*!< capability bit mask */
355078086f3SRasesh Mody 	u8			rsvd;
356f844a0eaSJeff Kirsher };
357f844a0eaSJeff Kirsher 
358f844a0eaSJeff Kirsher #define BFI_IOC_MSGSZ   8
359f844a0eaSJeff Kirsher /**
360f844a0eaSJeff Kirsher  * H2I Messages
361f844a0eaSJeff Kirsher  */
362f844a0eaSJeff Kirsher union bfi_ioc_h2i_msg_u {
363f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;
364f844a0eaSJeff Kirsher 	struct bfi_ioc_ctrl_req enable_req;
365f844a0eaSJeff Kirsher 	struct bfi_ioc_ctrl_req disable_req;
366f844a0eaSJeff Kirsher 	struct bfi_ioc_getattr_req getattr_req;
367f844a0eaSJeff Kirsher 	u32			mboxmsg[BFI_IOC_MSGSZ];
368f844a0eaSJeff Kirsher };
369f844a0eaSJeff Kirsher 
370f844a0eaSJeff Kirsher /**
371f844a0eaSJeff Kirsher  * I2H Messages
372f844a0eaSJeff Kirsher  */
373f844a0eaSJeff Kirsher union bfi_ioc_i2h_msg_u {
374f844a0eaSJeff Kirsher 	struct bfi_mhdr mh;
375078086f3SRasesh Mody 	struct bfi_ioc_ctrl_reply fw_event;
376f844a0eaSJeff Kirsher 	u32			mboxmsg[BFI_IOC_MSGSZ];
377f844a0eaSJeff Kirsher };
378f844a0eaSJeff Kirsher 
379af027a34SRasesh Mody /**
380af027a34SRasesh Mody  *----------------------------------------------------------------------
381af027a34SRasesh Mody  *				MSGQ
382af027a34SRasesh Mody  *----------------------------------------------------------------------
383af027a34SRasesh Mody  */
384af027a34SRasesh Mody 
385af027a34SRasesh Mody enum bfi_msgq_h2i_msgs {
386af027a34SRasesh Mody 	BFI_MSGQ_H2I_INIT_REQ	   = 1,
387af027a34SRasesh Mody 	BFI_MSGQ_H2I_DOORBELL_PI	= 2,
388af027a34SRasesh Mody 	BFI_MSGQ_H2I_DOORBELL_CI	= 3,
389af027a34SRasesh Mody 	BFI_MSGQ_H2I_CMDQ_COPY_RSP      = 4,
390af027a34SRasesh Mody };
391af027a34SRasesh Mody 
392af027a34SRasesh Mody enum bfi_msgq_i2h_msgs {
393af027a34SRasesh Mody 	BFI_MSGQ_I2H_INIT_RSP	   = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
394af027a34SRasesh Mody 	BFI_MSGQ_I2H_DOORBELL_PI	= BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
395af027a34SRasesh Mody 	BFI_MSGQ_I2H_DOORBELL_CI	= BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
396af027a34SRasesh Mody 	BFI_MSGQ_I2H_CMDQ_COPY_REQ      = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
397af027a34SRasesh Mody };
398af027a34SRasesh Mody 
399af027a34SRasesh Mody /* Messages(commands/responsed/AENS will have the following header */
400af027a34SRasesh Mody struct bfi_msgq_mhdr {
401af027a34SRasesh Mody 	u8	msg_class;
402af027a34SRasesh Mody 	u8	msg_id;
403af027a34SRasesh Mody 	u16	msg_token;
404af027a34SRasesh Mody 	u16	num_entries;
405af027a34SRasesh Mody 	u8	enet_id;
406af027a34SRasesh Mody 	u8	rsvd[1];
407af027a34SRasesh Mody };
408af027a34SRasesh Mody 
409af027a34SRasesh Mody #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do {	\
410af027a34SRasesh Mody 	(_mh).msg_class	 = (_mc);	\
411af027a34SRasesh Mody 	(_mh).msg_id	    = (_mid);       \
412af027a34SRasesh Mody 	(_mh).msg_token	 = (_tok);       \
413af027a34SRasesh Mody 	(_mh).enet_id	   = (_enet_id);   \
414af027a34SRasesh Mody } while (0)
415af027a34SRasesh Mody 
416af027a34SRasesh Mody /*
417af027a34SRasesh Mody  * Mailbox  for messaging interface
418af027a34SRasesh Mody  */
419af027a34SRasesh Mody #define BFI_MSGQ_CMD_ENTRY_SIZE	 (64)    /* TBD */
420af027a34SRasesh Mody #define BFI_MSGQ_RSP_ENTRY_SIZE	 (64)    /* TBD */
421af027a34SRasesh Mody 
422af027a34SRasesh Mody #define bfi_msgq_num_cmd_entries(_size)				 \
423af027a34SRasesh Mody 	(((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
424af027a34SRasesh Mody 
425af027a34SRasesh Mody struct bfi_msgq {
426af027a34SRasesh Mody 	union bfi_addr_u addr;
427af027a34SRasesh Mody 	u16 q_depth;     /* Total num of entries in the queue */
428af027a34SRasesh Mody 	u8 rsvd[2];
429af027a34SRasesh Mody };
430af027a34SRasesh Mody 
431af027a34SRasesh Mody /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
432af027a34SRasesh Mody struct bfi_msgq_cfg_req {
433af027a34SRasesh Mody 	struct bfi_mhdr mh;
434af027a34SRasesh Mody 	struct bfi_msgq cmdq;
435af027a34SRasesh Mody 	struct bfi_msgq rspq;
436af027a34SRasesh Mody };
437af027a34SRasesh Mody 
438af027a34SRasesh Mody /* BFI_ENET_MSGQ_CFG_RSP */
439af027a34SRasesh Mody struct bfi_msgq_cfg_rsp {
440af027a34SRasesh Mody 	struct bfi_mhdr mh;
441af027a34SRasesh Mody 	u8 cmd_status;
442af027a34SRasesh Mody 	u8 rsvd[3];
443af027a34SRasesh Mody };
444af027a34SRasesh Mody 
445af027a34SRasesh Mody /* BFI_MSGQ_H2I_DOORBELL */
446af027a34SRasesh Mody struct bfi_msgq_h2i_db {
447af027a34SRasesh Mody 	struct bfi_mhdr mh;
448af027a34SRasesh Mody 	union {
449af027a34SRasesh Mody 		u16 cmdq_pi;
450af027a34SRasesh Mody 		u16 rspq_ci;
451af027a34SRasesh Mody 	} idx;
452af027a34SRasesh Mody };
453af027a34SRasesh Mody 
454af027a34SRasesh Mody /* BFI_MSGQ_I2H_DOORBELL */
455af027a34SRasesh Mody struct bfi_msgq_i2h_db {
456af027a34SRasesh Mody 	struct bfi_mhdr mh;
457af027a34SRasesh Mody 	union {
458af027a34SRasesh Mody 		u16 rspq_pi;
459af027a34SRasesh Mody 		u16 cmdq_ci;
460af027a34SRasesh Mody 	} idx;
461af027a34SRasesh Mody };
462af027a34SRasesh Mody 
463af027a34SRasesh Mody #define BFI_CMD_COPY_SZ 28
464af027a34SRasesh Mody 
465af027a34SRasesh Mody /* BFI_MSGQ_H2I_CMD_COPY_RSP */
466af027a34SRasesh Mody struct bfi_msgq_h2i_cmdq_copy_rsp {
467af027a34SRasesh Mody 	struct bfi_mhdr mh;
468af027a34SRasesh Mody 	u8	      data[BFI_CMD_COPY_SZ];
469af027a34SRasesh Mody };
470af027a34SRasesh Mody 
471af027a34SRasesh Mody /* BFI_MSGQ_I2H_CMD_COPY_REQ */
472af027a34SRasesh Mody struct bfi_msgq_i2h_cmdq_copy_req {
473af027a34SRasesh Mody 	struct bfi_mhdr mh;
474af027a34SRasesh Mody 	u16     offset;
475af027a34SRasesh Mody 	u16     len;
476af027a34SRasesh Mody };
477af027a34SRasesh Mody 
478f844a0eaSJeff Kirsher #pragma pack()
479f844a0eaSJeff Kirsher 
480f844a0eaSJeff Kirsher #endif /* __BFI_H__ */
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