1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2020 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 #include <linux/platform_data/bcmgenet.h> 39 40 #include <asm/unaligned.h> 41 42 #include "bcmgenet.h" 43 44 /* Maximum number of hardware queues, downsized if needed */ 45 #define GENET_MAX_MQ_CNT 4 46 47 /* Default highest priority queue for multi queue support */ 48 #define GENET_Q0_PRIORITY 0 49 50 #define GENET_Q16_RX_BD_CNT \ 51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 52 #define GENET_Q16_TX_BD_CNT \ 53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 54 55 #define RX_BUF_LENGTH 2048 56 #define SKB_ALIGNMENT 32 57 58 /* Tx/Rx DMA register offset, skip 256 descriptors */ 59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 61 62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 66 TOTAL_DESC * DMA_DESC_SIZE) 67 68 /* Forward declarations */ 69 static void bcmgenet_set_rx_mode(struct net_device *dev); 70 71 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 72 { 73 /* MIPS chips strapped for BE will automagically configure the 74 * peripheral registers for CPU-native byte order. 75 */ 76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 77 __raw_writel(value, offset); 78 else 79 writel_relaxed(value, offset); 80 } 81 82 static inline u32 bcmgenet_readl(void __iomem *offset) 83 { 84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 85 return __raw_readl(offset); 86 else 87 return readl_relaxed(offset); 88 } 89 90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 91 void __iomem *d, u32 value) 92 { 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 94 } 95 96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 97 void __iomem *d, 98 dma_addr_t addr) 99 { 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 101 102 /* Register writes to GISB bus can take couple hundred nanoseconds 103 * and are done for each packet, save these expensive writes unless 104 * the platform is explicitly configured for 64-bits/LPAE. 105 */ 106 #ifdef CONFIG_PHYS_ADDR_T_64BIT 107 if (priv->hw_params->flags & GENET_HAS_40BITS) 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 109 #endif 110 } 111 112 /* Combined address + length/status setter */ 113 static inline void dmadesc_set(struct bcmgenet_priv *priv, 114 void __iomem *d, dma_addr_t addr, u32 val) 115 { 116 dmadesc_set_addr(priv, d, addr); 117 dmadesc_set_length_status(priv, d, val); 118 } 119 120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 121 void __iomem *d) 122 { 123 dma_addr_t addr; 124 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 126 127 /* Register writes to GISB bus can take couple hundred nanoseconds 128 * and are done for each packet, save these expensive writes unless 129 * the platform is explicitly configured for 64-bits/LPAE. 130 */ 131 #ifdef CONFIG_PHYS_ADDR_T_64BIT 132 if (priv->hw_params->flags & GENET_HAS_40BITS) 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 134 #endif 135 return addr; 136 } 137 138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 139 140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 141 NETIF_MSG_LINK) 142 143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 144 { 145 if (GENET_IS_V1(priv)) 146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 147 else 148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 149 } 150 151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152 { 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 155 else 156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 /* These macros are defined to deal with register map change 160 * between GENET1.1 and GENET2. Only those currently being used 161 * by driver are defined. 162 */ 163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 164 { 165 if (GENET_IS_V1(priv)) 166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 167 else 168 return bcmgenet_readl(priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 173 { 174 if (GENET_IS_V1(priv)) 175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 176 else 177 bcmgenet_writel(val, priv->base + 178 priv->hw_params->tbuf_offset + TBUF_CTRL); 179 } 180 181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 182 { 183 if (GENET_IS_V1(priv)) 184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 185 else 186 return bcmgenet_readl(priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 191 { 192 if (GENET_IS_V1(priv)) 193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 194 else 195 bcmgenet_writel(val, priv->base + 196 priv->hw_params->tbuf_offset + TBUF_BP_MC); 197 } 198 199 /* RX/TX DMA register accessors */ 200 enum dma_reg { 201 DMA_RING_CFG = 0, 202 DMA_CTRL, 203 DMA_STATUS, 204 DMA_SCB_BURST_SIZE, 205 DMA_ARB_CTRL, 206 DMA_PRIORITY_0, 207 DMA_PRIORITY_1, 208 DMA_PRIORITY_2, 209 DMA_INDEX2RING_0, 210 DMA_INDEX2RING_1, 211 DMA_INDEX2RING_2, 212 DMA_INDEX2RING_3, 213 DMA_INDEX2RING_4, 214 DMA_INDEX2RING_5, 215 DMA_INDEX2RING_6, 216 DMA_INDEX2RING_7, 217 DMA_RING0_TIMEOUT, 218 DMA_RING1_TIMEOUT, 219 DMA_RING2_TIMEOUT, 220 DMA_RING3_TIMEOUT, 221 DMA_RING4_TIMEOUT, 222 DMA_RING5_TIMEOUT, 223 DMA_RING6_TIMEOUT, 224 DMA_RING7_TIMEOUT, 225 DMA_RING8_TIMEOUT, 226 DMA_RING9_TIMEOUT, 227 DMA_RING10_TIMEOUT, 228 DMA_RING11_TIMEOUT, 229 DMA_RING12_TIMEOUT, 230 DMA_RING13_TIMEOUT, 231 DMA_RING14_TIMEOUT, 232 DMA_RING15_TIMEOUT, 233 DMA_RING16_TIMEOUT, 234 }; 235 236 static const u8 bcmgenet_dma_regs_v3plus[] = { 237 [DMA_RING_CFG] = 0x00, 238 [DMA_CTRL] = 0x04, 239 [DMA_STATUS] = 0x08, 240 [DMA_SCB_BURST_SIZE] = 0x0C, 241 [DMA_ARB_CTRL] = 0x2C, 242 [DMA_PRIORITY_0] = 0x30, 243 [DMA_PRIORITY_1] = 0x34, 244 [DMA_PRIORITY_2] = 0x38, 245 [DMA_RING0_TIMEOUT] = 0x2C, 246 [DMA_RING1_TIMEOUT] = 0x30, 247 [DMA_RING2_TIMEOUT] = 0x34, 248 [DMA_RING3_TIMEOUT] = 0x38, 249 [DMA_RING4_TIMEOUT] = 0x3c, 250 [DMA_RING5_TIMEOUT] = 0x40, 251 [DMA_RING6_TIMEOUT] = 0x44, 252 [DMA_RING7_TIMEOUT] = 0x48, 253 [DMA_RING8_TIMEOUT] = 0x4c, 254 [DMA_RING9_TIMEOUT] = 0x50, 255 [DMA_RING10_TIMEOUT] = 0x54, 256 [DMA_RING11_TIMEOUT] = 0x58, 257 [DMA_RING12_TIMEOUT] = 0x5c, 258 [DMA_RING13_TIMEOUT] = 0x60, 259 [DMA_RING14_TIMEOUT] = 0x64, 260 [DMA_RING15_TIMEOUT] = 0x68, 261 [DMA_RING16_TIMEOUT] = 0x6C, 262 [DMA_INDEX2RING_0] = 0x70, 263 [DMA_INDEX2RING_1] = 0x74, 264 [DMA_INDEX2RING_2] = 0x78, 265 [DMA_INDEX2RING_3] = 0x7C, 266 [DMA_INDEX2RING_4] = 0x80, 267 [DMA_INDEX2RING_5] = 0x84, 268 [DMA_INDEX2RING_6] = 0x88, 269 [DMA_INDEX2RING_7] = 0x8C, 270 }; 271 272 static const u8 bcmgenet_dma_regs_v2[] = { 273 [DMA_RING_CFG] = 0x00, 274 [DMA_CTRL] = 0x04, 275 [DMA_STATUS] = 0x08, 276 [DMA_SCB_BURST_SIZE] = 0x0C, 277 [DMA_ARB_CTRL] = 0x30, 278 [DMA_PRIORITY_0] = 0x34, 279 [DMA_PRIORITY_1] = 0x38, 280 [DMA_PRIORITY_2] = 0x3C, 281 [DMA_RING0_TIMEOUT] = 0x2C, 282 [DMA_RING1_TIMEOUT] = 0x30, 283 [DMA_RING2_TIMEOUT] = 0x34, 284 [DMA_RING3_TIMEOUT] = 0x38, 285 [DMA_RING4_TIMEOUT] = 0x3c, 286 [DMA_RING5_TIMEOUT] = 0x40, 287 [DMA_RING6_TIMEOUT] = 0x44, 288 [DMA_RING7_TIMEOUT] = 0x48, 289 [DMA_RING8_TIMEOUT] = 0x4c, 290 [DMA_RING9_TIMEOUT] = 0x50, 291 [DMA_RING10_TIMEOUT] = 0x54, 292 [DMA_RING11_TIMEOUT] = 0x58, 293 [DMA_RING12_TIMEOUT] = 0x5c, 294 [DMA_RING13_TIMEOUT] = 0x60, 295 [DMA_RING14_TIMEOUT] = 0x64, 296 [DMA_RING15_TIMEOUT] = 0x68, 297 [DMA_RING16_TIMEOUT] = 0x6C, 298 }; 299 300 static const u8 bcmgenet_dma_regs_v1[] = { 301 [DMA_CTRL] = 0x00, 302 [DMA_STATUS] = 0x04, 303 [DMA_SCB_BURST_SIZE] = 0x0C, 304 [DMA_ARB_CTRL] = 0x30, 305 [DMA_PRIORITY_0] = 0x34, 306 [DMA_PRIORITY_1] = 0x38, 307 [DMA_PRIORITY_2] = 0x3C, 308 [DMA_RING0_TIMEOUT] = 0x2C, 309 [DMA_RING1_TIMEOUT] = 0x30, 310 [DMA_RING2_TIMEOUT] = 0x34, 311 [DMA_RING3_TIMEOUT] = 0x38, 312 [DMA_RING4_TIMEOUT] = 0x3c, 313 [DMA_RING5_TIMEOUT] = 0x40, 314 [DMA_RING6_TIMEOUT] = 0x44, 315 [DMA_RING7_TIMEOUT] = 0x48, 316 [DMA_RING8_TIMEOUT] = 0x4c, 317 [DMA_RING9_TIMEOUT] = 0x50, 318 [DMA_RING10_TIMEOUT] = 0x54, 319 [DMA_RING11_TIMEOUT] = 0x58, 320 [DMA_RING12_TIMEOUT] = 0x5c, 321 [DMA_RING13_TIMEOUT] = 0x60, 322 [DMA_RING14_TIMEOUT] = 0x64, 323 [DMA_RING15_TIMEOUT] = 0x68, 324 [DMA_RING16_TIMEOUT] = 0x6C, 325 }; 326 327 /* Set at runtime once bcmgenet version is known */ 328 static const u8 *bcmgenet_dma_regs; 329 330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 331 { 332 return netdev_priv(dev_get_drvdata(dev)); 333 } 334 335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 336 enum dma_reg r) 337 { 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340 } 341 342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 343 u32 val, enum dma_reg r) 344 { 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347 } 348 349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 350 enum dma_reg r) 351 { 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354 } 355 356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 357 u32 val, enum dma_reg r) 358 { 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361 } 362 363 /* RDMA/TDMA ring registers and accessors 364 * we merge the common fields and just prefix with T/D the registers 365 * having different meaning depending on the direction 366 */ 367 enum dma_ring_reg { 368 TDMA_READ_PTR = 0, 369 RDMA_WRITE_PTR = TDMA_READ_PTR, 370 TDMA_READ_PTR_HI, 371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 372 TDMA_CONS_INDEX, 373 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 374 TDMA_PROD_INDEX, 375 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 376 DMA_RING_BUF_SIZE, 377 DMA_START_ADDR, 378 DMA_START_ADDR_HI, 379 DMA_END_ADDR, 380 DMA_END_ADDR_HI, 381 DMA_MBUF_DONE_THRESH, 382 TDMA_FLOW_PERIOD, 383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 384 TDMA_WRITE_PTR, 385 RDMA_READ_PTR = TDMA_WRITE_PTR, 386 TDMA_WRITE_PTR_HI, 387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 388 }; 389 390 /* GENET v4 supports 40-bits pointer addressing 391 * for obvious reasons the LO and HI word parts 392 * are contiguous, but this offsets the other 393 * registers. 394 */ 395 static const u8 genet_dma_ring_regs_v4[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_READ_PTR_HI] = 0x04, 398 [TDMA_CONS_INDEX] = 0x08, 399 [TDMA_PROD_INDEX] = 0x0C, 400 [DMA_RING_BUF_SIZE] = 0x10, 401 [DMA_START_ADDR] = 0x14, 402 [DMA_START_ADDR_HI] = 0x18, 403 [DMA_END_ADDR] = 0x1C, 404 [DMA_END_ADDR_HI] = 0x20, 405 [DMA_MBUF_DONE_THRESH] = 0x24, 406 [TDMA_FLOW_PERIOD] = 0x28, 407 [TDMA_WRITE_PTR] = 0x2C, 408 [TDMA_WRITE_PTR_HI] = 0x30, 409 }; 410 411 static const u8 genet_dma_ring_regs_v123[] = { 412 [TDMA_READ_PTR] = 0x00, 413 [TDMA_CONS_INDEX] = 0x04, 414 [TDMA_PROD_INDEX] = 0x08, 415 [DMA_RING_BUF_SIZE] = 0x0C, 416 [DMA_START_ADDR] = 0x10, 417 [DMA_END_ADDR] = 0x14, 418 [DMA_MBUF_DONE_THRESH] = 0x18, 419 [TDMA_FLOW_PERIOD] = 0x1C, 420 [TDMA_WRITE_PTR] = 0x20, 421 }; 422 423 /* Set at runtime once GENET version is known */ 424 static const u8 *genet_dma_ring_regs; 425 426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 427 unsigned int ring, 428 enum dma_ring_reg r) 429 { 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 436 unsigned int ring, u32 val, 437 enum dma_ring_reg r) 438 { 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 445 unsigned int ring, 446 enum dma_ring_reg r) 447 { 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 454 unsigned int ring, u32 val, 455 enum dma_ring_reg r) 456 { 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 458 (DMA_RING_SIZE * ring) + 459 genet_dma_ring_regs[r]); 460 } 461 462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 463 { 464 u32 offset; 465 u32 reg; 466 467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 468 reg = bcmgenet_hfb_reg_readl(priv, offset); 469 reg |= (1 << (f_index % 32)); 470 bcmgenet_hfb_reg_writel(priv, reg, offset); 471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 472 reg |= RBUF_HFB_EN; 473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 474 } 475 476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 477 { 478 u32 offset, reg, reg1; 479 480 offset = HFB_FLT_ENABLE_V3PLUS; 481 reg = bcmgenet_hfb_reg_readl(priv, offset); 482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 483 if (f_index < 32) { 484 reg1 &= ~(1 << (f_index % 32)); 485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 486 } else { 487 reg &= ~(1 << (f_index % 32)); 488 bcmgenet_hfb_reg_writel(priv, reg, offset); 489 } 490 if (!reg && !reg1) { 491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 492 reg &= ~RBUF_HFB_EN; 493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 494 } 495 } 496 497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 498 u32 f_index, u32 rx_queue) 499 { 500 u32 offset; 501 u32 reg; 502 503 offset = f_index / 8; 504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 505 reg &= ~(0xF << (4 * (f_index % 8))); 506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 508 } 509 510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 511 u32 f_index, u32 f_length) 512 { 513 u32 offset; 514 u32 reg; 515 516 offset = HFB_FLT_LEN_V3PLUS + 517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 518 sizeof(u32); 519 reg = bcmgenet_hfb_reg_readl(priv, offset); 520 reg &= ~(0xFF << (8 * (f_index % 4))); 521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 522 bcmgenet_hfb_reg_writel(priv, reg, offset); 523 } 524 525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 526 { 527 while (size) { 528 switch (*(unsigned char *)mask++) { 529 case 0x00: 530 case 0x0f: 531 case 0xf0: 532 case 0xff: 533 size--; 534 continue; 535 default: 536 return -EINVAL; 537 } 538 } 539 540 return 0; 541 } 542 543 #define VALIDATE_MASK(x) \ 544 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 545 546 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 547 u32 offset, void *val, void *mask, 548 size_t size) 549 { 550 u32 index, tmp; 551 552 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 553 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 554 555 while (size--) { 556 if (offset++ & 1) { 557 tmp &= ~0x300FF; 558 tmp |= (*(unsigned char *)val++); 559 switch ((*(unsigned char *)mask++)) { 560 case 0xFF: 561 tmp |= 0x30000; 562 break; 563 case 0xF0: 564 tmp |= 0x20000; 565 break; 566 case 0x0F: 567 tmp |= 0x10000; 568 break; 569 } 570 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 571 if (size) 572 tmp = bcmgenet_hfb_readl(priv, 573 index * sizeof(u32)); 574 } else { 575 tmp &= ~0xCFF00; 576 tmp |= (*(unsigned char *)val++) << 8; 577 switch ((*(unsigned char *)mask++)) { 578 case 0xFF: 579 tmp |= 0xC0000; 580 break; 581 case 0xF0: 582 tmp |= 0x80000; 583 break; 584 case 0x0F: 585 tmp |= 0x40000; 586 break; 587 } 588 if (!size) 589 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 590 } 591 } 592 593 return 0; 594 } 595 596 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 597 struct bcmgenet_rxnfc_rule *rule) 598 { 599 struct ethtool_rx_flow_spec *fs = &rule->fs; 600 u32 offset = 0, f_length = 0, f; 601 u8 val_8, mask_8; 602 __be16 val_16; 603 u16 mask_16; 604 size_t size; 605 606 f = fs->location; 607 if (fs->flow_type & FLOW_MAC_EXT) { 608 bcmgenet_hfb_insert_data(priv, f, 0, 609 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 610 sizeof(fs->h_ext.h_dest)); 611 } 612 613 if (fs->flow_type & FLOW_EXT) { 614 if (fs->m_ext.vlan_etype || 615 fs->m_ext.vlan_tci) { 616 bcmgenet_hfb_insert_data(priv, f, 12, 617 &fs->h_ext.vlan_etype, 618 &fs->m_ext.vlan_etype, 619 sizeof(fs->h_ext.vlan_etype)); 620 bcmgenet_hfb_insert_data(priv, f, 14, 621 &fs->h_ext.vlan_tci, 622 &fs->m_ext.vlan_tci, 623 sizeof(fs->h_ext.vlan_tci)); 624 offset += VLAN_HLEN; 625 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 626 } 627 } 628 629 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 630 case ETHER_FLOW: 631 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 632 bcmgenet_hfb_insert_data(priv, f, 0, 633 &fs->h_u.ether_spec.h_dest, 634 &fs->m_u.ether_spec.h_dest, 635 sizeof(fs->h_u.ether_spec.h_dest)); 636 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 637 &fs->h_u.ether_spec.h_source, 638 &fs->m_u.ether_spec.h_source, 639 sizeof(fs->h_u.ether_spec.h_source)); 640 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 641 &fs->h_u.ether_spec.h_proto, 642 &fs->m_u.ether_spec.h_proto, 643 sizeof(fs->h_u.ether_spec.h_proto)); 644 break; 645 case IP_USER_FLOW: 646 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 647 /* Specify IP Ether Type */ 648 val_16 = htons(ETH_P_IP); 649 mask_16 = 0xFFFF; 650 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 651 &val_16, &mask_16, sizeof(val_16)); 652 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 653 &fs->h_u.usr_ip4_spec.tos, 654 &fs->m_u.usr_ip4_spec.tos, 655 sizeof(fs->h_u.usr_ip4_spec.tos)); 656 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 657 &fs->h_u.usr_ip4_spec.proto, 658 &fs->m_u.usr_ip4_spec.proto, 659 sizeof(fs->h_u.usr_ip4_spec.proto)); 660 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 661 &fs->h_u.usr_ip4_spec.ip4src, 662 &fs->m_u.usr_ip4_spec.ip4src, 663 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 664 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 665 &fs->h_u.usr_ip4_spec.ip4dst, 666 &fs->m_u.usr_ip4_spec.ip4dst, 667 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 668 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 669 break; 670 671 /* Only supports 20 byte IPv4 header */ 672 val_8 = 0x45; 673 mask_8 = 0xFF; 674 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 675 &val_8, &mask_8, 676 sizeof(val_8)); 677 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 678 bcmgenet_hfb_insert_data(priv, f, 679 ETH_HLEN + 20 + offset, 680 &fs->h_u.usr_ip4_spec.l4_4_bytes, 681 &fs->m_u.usr_ip4_spec.l4_4_bytes, 682 size); 683 f_length += DIV_ROUND_UP(size, 2); 684 break; 685 } 686 687 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 688 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) { 689 /* Ring 0 flows can be handled by the default Descriptor Ring 690 * We'll map them to ring 0, but don't enable the filter 691 */ 692 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0); 693 rule->state = BCMGENET_RXNFC_STATE_DISABLED; 694 } else { 695 /* Other Rx rings are direct mapped here */ 696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 697 fs->ring_cookie); 698 bcmgenet_hfb_enable_filter(priv, f); 699 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 700 } 701 } 702 703 /* bcmgenet_hfb_clear 704 * 705 * Clear Hardware Filter Block and disable all filtering. 706 */ 707 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 708 { 709 u32 base, i; 710 711 base = f_index * priv->hw_params->hfb_filter_size; 712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 714 } 715 716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 717 { 718 u32 i; 719 720 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 721 return; 722 723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 724 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 725 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 726 727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 728 bcmgenet_rdma_writel(priv, 0x0, i); 729 730 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 731 bcmgenet_hfb_reg_writel(priv, 0x0, 732 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 733 734 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 735 bcmgenet_hfb_clear_filter(priv, i); 736 } 737 738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 739 { 740 int i; 741 742 INIT_LIST_HEAD(&priv->rxnfc_list); 743 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 744 return; 745 746 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 747 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 748 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 749 } 750 751 bcmgenet_hfb_clear(priv); 752 } 753 754 static int bcmgenet_begin(struct net_device *dev) 755 { 756 struct bcmgenet_priv *priv = netdev_priv(dev); 757 758 /* Turn on the clock */ 759 return clk_prepare_enable(priv->clk); 760 } 761 762 static void bcmgenet_complete(struct net_device *dev) 763 { 764 struct bcmgenet_priv *priv = netdev_priv(dev); 765 766 /* Turn off the clock */ 767 clk_disable_unprepare(priv->clk); 768 } 769 770 static int bcmgenet_get_link_ksettings(struct net_device *dev, 771 struct ethtool_link_ksettings *cmd) 772 { 773 if (!netif_running(dev)) 774 return -EINVAL; 775 776 if (!dev->phydev) 777 return -ENODEV; 778 779 phy_ethtool_ksettings_get(dev->phydev, cmd); 780 781 return 0; 782 } 783 784 static int bcmgenet_set_link_ksettings(struct net_device *dev, 785 const struct ethtool_link_ksettings *cmd) 786 { 787 if (!netif_running(dev)) 788 return -EINVAL; 789 790 if (!dev->phydev) 791 return -ENODEV; 792 793 return phy_ethtool_ksettings_set(dev->phydev, cmd); 794 } 795 796 static int bcmgenet_set_features(struct net_device *dev, 797 netdev_features_t features) 798 { 799 struct bcmgenet_priv *priv = netdev_priv(dev); 800 u32 reg; 801 int ret; 802 803 ret = clk_prepare_enable(priv->clk); 804 if (ret) 805 return ret; 806 807 /* Make sure we reflect the value of CRC_CMD_FWD */ 808 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 809 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 810 811 clk_disable_unprepare(priv->clk); 812 813 return ret; 814 } 815 816 static u32 bcmgenet_get_msglevel(struct net_device *dev) 817 { 818 struct bcmgenet_priv *priv = netdev_priv(dev); 819 820 return priv->msg_enable; 821 } 822 823 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 824 { 825 struct bcmgenet_priv *priv = netdev_priv(dev); 826 827 priv->msg_enable = level; 828 } 829 830 static int bcmgenet_get_coalesce(struct net_device *dev, 831 struct ethtool_coalesce *ec, 832 struct kernel_ethtool_coalesce *kernel_coal, 833 struct netlink_ext_ack *extack) 834 { 835 struct bcmgenet_priv *priv = netdev_priv(dev); 836 struct bcmgenet_rx_ring *ring; 837 unsigned int i; 838 839 ec->tx_max_coalesced_frames = 840 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 841 DMA_MBUF_DONE_THRESH); 842 ec->rx_max_coalesced_frames = 843 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 844 DMA_MBUF_DONE_THRESH); 845 ec->rx_coalesce_usecs = 846 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 847 848 for (i = 0; i < priv->hw_params->rx_queues; i++) { 849 ring = &priv->rx_rings[i]; 850 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 851 } 852 ring = &priv->rx_rings[DESC_INDEX]; 853 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 854 855 return 0; 856 } 857 858 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 859 u32 usecs, u32 pkts) 860 { 861 struct bcmgenet_priv *priv = ring->priv; 862 unsigned int i = ring->index; 863 u32 reg; 864 865 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 866 867 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 868 reg &= ~DMA_TIMEOUT_MASK; 869 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 870 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 871 } 872 873 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 874 struct ethtool_coalesce *ec) 875 { 876 struct dim_cq_moder moder; 877 u32 usecs, pkts; 878 879 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 880 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 881 usecs = ring->rx_coalesce_usecs; 882 pkts = ring->rx_max_coalesced_frames; 883 884 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 885 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 886 usecs = moder.usec; 887 pkts = moder.pkts; 888 } 889 890 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 891 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 892 } 893 894 static int bcmgenet_set_coalesce(struct net_device *dev, 895 struct ethtool_coalesce *ec, 896 struct kernel_ethtool_coalesce *kernel_coal, 897 struct netlink_ext_ack *extack) 898 { 899 struct bcmgenet_priv *priv = netdev_priv(dev); 900 unsigned int i; 901 902 /* Base system clock is 125Mhz, DMA timeout is this reference clock 903 * divided by 1024, which yields roughly 8.192us, our maximum value 904 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 905 */ 906 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 907 ec->tx_max_coalesced_frames == 0 || 908 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 909 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 910 return -EINVAL; 911 912 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 913 return -EINVAL; 914 915 /* GENET TDMA hardware does not support a configurable timeout, but will 916 * always generate an interrupt either after MBDONE packets have been 917 * transmitted, or when the ring is empty. 918 */ 919 920 /* Program all TX queues with the same values, as there is no 921 * ethtool knob to do coalescing on a per-queue basis 922 */ 923 for (i = 0; i < priv->hw_params->tx_queues; i++) 924 bcmgenet_tdma_ring_writel(priv, i, 925 ec->tx_max_coalesced_frames, 926 DMA_MBUF_DONE_THRESH); 927 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 928 ec->tx_max_coalesced_frames, 929 DMA_MBUF_DONE_THRESH); 930 931 for (i = 0; i < priv->hw_params->rx_queues; i++) 932 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 933 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 934 935 return 0; 936 } 937 938 static void bcmgenet_get_pauseparam(struct net_device *dev, 939 struct ethtool_pauseparam *epause) 940 { 941 struct bcmgenet_priv *priv; 942 u32 umac_cmd; 943 944 priv = netdev_priv(dev); 945 946 epause->autoneg = priv->autoneg_pause; 947 948 if (netif_carrier_ok(dev)) { 949 /* report active state when link is up */ 950 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD); 951 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE); 952 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE); 953 } else { 954 /* otherwise report stored settings */ 955 epause->tx_pause = priv->tx_pause; 956 epause->rx_pause = priv->rx_pause; 957 } 958 } 959 960 static int bcmgenet_set_pauseparam(struct net_device *dev, 961 struct ethtool_pauseparam *epause) 962 { 963 struct bcmgenet_priv *priv = netdev_priv(dev); 964 965 if (!dev->phydev) 966 return -ENODEV; 967 968 if (!phy_validate_pause(dev->phydev, epause)) 969 return -EINVAL; 970 971 priv->autoneg_pause = !!epause->autoneg; 972 priv->tx_pause = !!epause->tx_pause; 973 priv->rx_pause = !!epause->rx_pause; 974 975 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 976 977 return 0; 978 } 979 980 /* standard ethtool support functions. */ 981 enum bcmgenet_stat_type { 982 BCMGENET_STAT_NETDEV = -1, 983 BCMGENET_STAT_MIB_RX, 984 BCMGENET_STAT_MIB_TX, 985 BCMGENET_STAT_RUNT, 986 BCMGENET_STAT_MISC, 987 BCMGENET_STAT_SOFT, 988 }; 989 990 struct bcmgenet_stats { 991 char stat_string[ETH_GSTRING_LEN]; 992 int stat_sizeof; 993 int stat_offset; 994 enum bcmgenet_stat_type type; 995 /* reg offset from UMAC base for misc counters */ 996 u16 reg_offset; 997 }; 998 999 #define STAT_NETDEV(m) { \ 1000 .stat_string = __stringify(m), \ 1001 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 1002 .stat_offset = offsetof(struct net_device_stats, m), \ 1003 .type = BCMGENET_STAT_NETDEV, \ 1004 } 1005 1006 #define STAT_GENET_MIB(str, m, _type) { \ 1007 .stat_string = str, \ 1008 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1009 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1010 .type = _type, \ 1011 } 1012 1013 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1014 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1015 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1016 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1017 1018 #define STAT_GENET_MISC(str, m, offset) { \ 1019 .stat_string = str, \ 1020 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1021 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1022 .type = BCMGENET_STAT_MISC, \ 1023 .reg_offset = offset, \ 1024 } 1025 1026 #define STAT_GENET_Q(num) \ 1027 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 1028 tx_rings[num].packets), \ 1029 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 1030 tx_rings[num].bytes), \ 1031 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 1032 rx_rings[num].bytes), \ 1033 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 1034 rx_rings[num].packets), \ 1035 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 1036 rx_rings[num].errors), \ 1037 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 1038 rx_rings[num].dropped) 1039 1040 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1041 * between the end of TX stats and the beginning of the RX RUNT 1042 */ 1043 #define BCMGENET_STAT_OFFSET 0xc 1044 1045 /* Hardware counters must be kept in sync because the order/offset 1046 * is important here (order in structure declaration = order in hardware) 1047 */ 1048 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1049 /* general stats */ 1050 STAT_NETDEV(rx_packets), 1051 STAT_NETDEV(tx_packets), 1052 STAT_NETDEV(rx_bytes), 1053 STAT_NETDEV(tx_bytes), 1054 STAT_NETDEV(rx_errors), 1055 STAT_NETDEV(tx_errors), 1056 STAT_NETDEV(rx_dropped), 1057 STAT_NETDEV(tx_dropped), 1058 STAT_NETDEV(multicast), 1059 /* UniMAC RSV counters */ 1060 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1061 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1062 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1063 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1064 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1065 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1066 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1067 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1068 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1069 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1070 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1071 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1072 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1073 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1074 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1075 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1076 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1077 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1078 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1079 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1080 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1081 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1082 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1083 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1084 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1085 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1086 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1087 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1088 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1089 /* UniMAC TSV counters */ 1090 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1091 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1092 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1093 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1094 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1095 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1096 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1097 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1098 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1099 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1100 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1101 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1102 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1103 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1104 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1105 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1106 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1107 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1108 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1109 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1110 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1111 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1112 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1113 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1114 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1115 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1116 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1117 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1118 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1119 /* UniMAC RUNT counters */ 1120 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1121 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1122 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1123 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1124 /* Misc UniMAC counters */ 1125 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1126 UMAC_RBUF_OVFL_CNT_V1), 1127 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1128 UMAC_RBUF_ERR_CNT_V1), 1129 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1130 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1131 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1132 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1133 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1134 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1135 mib.tx_realloc_tsb_failed), 1136 /* Per TX queues */ 1137 STAT_GENET_Q(0), 1138 STAT_GENET_Q(1), 1139 STAT_GENET_Q(2), 1140 STAT_GENET_Q(3), 1141 STAT_GENET_Q(16), 1142 }; 1143 1144 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1145 1146 static void bcmgenet_get_drvinfo(struct net_device *dev, 1147 struct ethtool_drvinfo *info) 1148 { 1149 strscpy(info->driver, "bcmgenet", sizeof(info->driver)); 1150 } 1151 1152 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1153 { 1154 switch (string_set) { 1155 case ETH_SS_STATS: 1156 return BCMGENET_STATS_LEN; 1157 default: 1158 return -EOPNOTSUPP; 1159 } 1160 } 1161 1162 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1163 u8 *data) 1164 { 1165 int i; 1166 1167 switch (stringset) { 1168 case ETH_SS_STATS: 1169 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1170 memcpy(data + i * ETH_GSTRING_LEN, 1171 bcmgenet_gstrings_stats[i].stat_string, 1172 ETH_GSTRING_LEN); 1173 } 1174 break; 1175 } 1176 } 1177 1178 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1179 { 1180 u16 new_offset; 1181 u32 val; 1182 1183 switch (offset) { 1184 case UMAC_RBUF_OVFL_CNT_V1: 1185 if (GENET_IS_V2(priv)) 1186 new_offset = RBUF_OVFL_CNT_V2; 1187 else 1188 new_offset = RBUF_OVFL_CNT_V3PLUS; 1189 1190 val = bcmgenet_rbuf_readl(priv, new_offset); 1191 /* clear if overflowed */ 1192 if (val == ~0) 1193 bcmgenet_rbuf_writel(priv, 0, new_offset); 1194 break; 1195 case UMAC_RBUF_ERR_CNT_V1: 1196 if (GENET_IS_V2(priv)) 1197 new_offset = RBUF_ERR_CNT_V2; 1198 else 1199 new_offset = RBUF_ERR_CNT_V3PLUS; 1200 1201 val = bcmgenet_rbuf_readl(priv, new_offset); 1202 /* clear if overflowed */ 1203 if (val == ~0) 1204 bcmgenet_rbuf_writel(priv, 0, new_offset); 1205 break; 1206 default: 1207 val = bcmgenet_umac_readl(priv, offset); 1208 /* clear if overflowed */ 1209 if (val == ~0) 1210 bcmgenet_umac_writel(priv, 0, offset); 1211 break; 1212 } 1213 1214 return val; 1215 } 1216 1217 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1218 { 1219 int i, j = 0; 1220 1221 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1222 const struct bcmgenet_stats *s; 1223 u8 offset = 0; 1224 u32 val = 0; 1225 char *p; 1226 1227 s = &bcmgenet_gstrings_stats[i]; 1228 switch (s->type) { 1229 case BCMGENET_STAT_NETDEV: 1230 case BCMGENET_STAT_SOFT: 1231 continue; 1232 case BCMGENET_STAT_RUNT: 1233 offset += BCMGENET_STAT_OFFSET; 1234 fallthrough; 1235 case BCMGENET_STAT_MIB_TX: 1236 offset += BCMGENET_STAT_OFFSET; 1237 fallthrough; 1238 case BCMGENET_STAT_MIB_RX: 1239 val = bcmgenet_umac_readl(priv, 1240 UMAC_MIB_START + j + offset); 1241 offset = 0; /* Reset Offset */ 1242 break; 1243 case BCMGENET_STAT_MISC: 1244 if (GENET_IS_V1(priv)) { 1245 val = bcmgenet_umac_readl(priv, s->reg_offset); 1246 /* clear if overflowed */ 1247 if (val == ~0) 1248 bcmgenet_umac_writel(priv, 0, 1249 s->reg_offset); 1250 } else { 1251 val = bcmgenet_update_stat_misc(priv, 1252 s->reg_offset); 1253 } 1254 break; 1255 } 1256 1257 j += s->stat_sizeof; 1258 p = (char *)priv + s->stat_offset; 1259 *(u32 *)p = val; 1260 } 1261 } 1262 1263 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1264 struct ethtool_stats *stats, 1265 u64 *data) 1266 { 1267 struct bcmgenet_priv *priv = netdev_priv(dev); 1268 int i; 1269 1270 if (netif_running(dev)) 1271 bcmgenet_update_mib_counters(priv); 1272 1273 dev->netdev_ops->ndo_get_stats(dev); 1274 1275 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1276 const struct bcmgenet_stats *s; 1277 char *p; 1278 1279 s = &bcmgenet_gstrings_stats[i]; 1280 if (s->type == BCMGENET_STAT_NETDEV) 1281 p = (char *)&dev->stats; 1282 else 1283 p = (char *)priv; 1284 p += s->stat_offset; 1285 if (sizeof(unsigned long) != sizeof(u32) && 1286 s->stat_sizeof == sizeof(unsigned long)) 1287 data[i] = *(unsigned long *)p; 1288 else 1289 data[i] = *(u32 *)p; 1290 } 1291 } 1292 1293 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1294 { 1295 struct bcmgenet_priv *priv = netdev_priv(dev); 1296 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1297 u32 reg; 1298 1299 if (enable && !priv->clk_eee_enabled) { 1300 clk_prepare_enable(priv->clk_eee); 1301 priv->clk_eee_enabled = true; 1302 } 1303 1304 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1305 if (enable) 1306 reg |= EEE_EN; 1307 else 1308 reg &= ~EEE_EN; 1309 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1310 1311 /* Enable EEE and switch to a 27Mhz clock automatically */ 1312 reg = bcmgenet_readl(priv->base + off); 1313 if (enable) 1314 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1315 else 1316 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1317 bcmgenet_writel(reg, priv->base + off); 1318 1319 /* Do the same for thing for RBUF */ 1320 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1321 if (enable) 1322 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1323 else 1324 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1325 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1326 1327 if (!enable && priv->clk_eee_enabled) { 1328 clk_disable_unprepare(priv->clk_eee); 1329 priv->clk_eee_enabled = false; 1330 } 1331 1332 priv->eee.eee_enabled = enable; 1333 priv->eee.eee_active = enable; 1334 } 1335 1336 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1337 { 1338 struct bcmgenet_priv *priv = netdev_priv(dev); 1339 struct ethtool_eee *p = &priv->eee; 1340 1341 if (GENET_IS_V1(priv)) 1342 return -EOPNOTSUPP; 1343 1344 if (!dev->phydev) 1345 return -ENODEV; 1346 1347 e->eee_enabled = p->eee_enabled; 1348 e->eee_active = p->eee_active; 1349 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1350 1351 return phy_ethtool_get_eee(dev->phydev, e); 1352 } 1353 1354 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1355 { 1356 struct bcmgenet_priv *priv = netdev_priv(dev); 1357 struct ethtool_eee *p = &priv->eee; 1358 int ret = 0; 1359 1360 if (GENET_IS_V1(priv)) 1361 return -EOPNOTSUPP; 1362 1363 if (!dev->phydev) 1364 return -ENODEV; 1365 1366 p->eee_enabled = e->eee_enabled; 1367 1368 if (!p->eee_enabled) { 1369 bcmgenet_eee_enable_set(dev, false); 1370 } else { 1371 ret = phy_init_eee(dev->phydev, false); 1372 if (ret) { 1373 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1374 return ret; 1375 } 1376 1377 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1378 bcmgenet_eee_enable_set(dev, true); 1379 } 1380 1381 return phy_ethtool_set_eee(dev->phydev, e); 1382 } 1383 1384 static int bcmgenet_validate_flow(struct net_device *dev, 1385 struct ethtool_rxnfc *cmd) 1386 { 1387 struct ethtool_usrip4_spec *l4_mask; 1388 struct ethhdr *eth_mask; 1389 1390 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES && 1391 cmd->fs.location != RX_CLS_LOC_ANY) { 1392 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1393 cmd->fs.location); 1394 return -EINVAL; 1395 } 1396 1397 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1398 case IP_USER_FLOW: 1399 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1400 /* don't allow mask which isn't valid */ 1401 if (VALIDATE_MASK(l4_mask->ip4src) || 1402 VALIDATE_MASK(l4_mask->ip4dst) || 1403 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1404 VALIDATE_MASK(l4_mask->proto) || 1405 VALIDATE_MASK(l4_mask->ip_ver) || 1406 VALIDATE_MASK(l4_mask->tos)) { 1407 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1408 return -EINVAL; 1409 } 1410 break; 1411 case ETHER_FLOW: 1412 eth_mask = &cmd->fs.m_u.ether_spec; 1413 /* don't allow mask which isn't valid */ 1414 if (VALIDATE_MASK(eth_mask->h_dest) || 1415 VALIDATE_MASK(eth_mask->h_source) || 1416 VALIDATE_MASK(eth_mask->h_proto)) { 1417 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1418 return -EINVAL; 1419 } 1420 break; 1421 default: 1422 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1423 cmd->fs.flow_type); 1424 return -EINVAL; 1425 } 1426 1427 if ((cmd->fs.flow_type & FLOW_EXT)) { 1428 /* don't allow mask which isn't valid */ 1429 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1430 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1431 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1432 return -EINVAL; 1433 } 1434 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1435 netdev_err(dev, "rxnfc: user-def not supported\n"); 1436 return -EINVAL; 1437 } 1438 } 1439 1440 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1441 /* don't allow mask which isn't valid */ 1442 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1443 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1444 return -EINVAL; 1445 } 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int bcmgenet_insert_flow(struct net_device *dev, 1452 struct ethtool_rxnfc *cmd) 1453 { 1454 struct bcmgenet_priv *priv = netdev_priv(dev); 1455 struct bcmgenet_rxnfc_rule *loc_rule; 1456 int err, i; 1457 1458 if (priv->hw_params->hfb_filter_size < 128) { 1459 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1460 return -EINVAL; 1461 } 1462 1463 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1464 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) { 1465 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1466 cmd->fs.ring_cookie); 1467 return -EINVAL; 1468 } 1469 1470 err = bcmgenet_validate_flow(dev, cmd); 1471 if (err) 1472 return err; 1473 1474 if (cmd->fs.location == RX_CLS_LOC_ANY) { 1475 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) { 1476 cmd->fs.location = loc_rule->fs.location; 1477 err = memcmp(&loc_rule->fs, &cmd->fs, 1478 sizeof(struct ethtool_rx_flow_spec)); 1479 if (!err) 1480 /* rule exists so return current location */ 1481 return 0; 1482 } 1483 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1484 loc_rule = &priv->rxnfc_rules[i]; 1485 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1486 cmd->fs.location = i; 1487 break; 1488 } 1489 } 1490 if (i == MAX_NUM_OF_FS_RULES) { 1491 cmd->fs.location = RX_CLS_LOC_ANY; 1492 return -ENOSPC; 1493 } 1494 } else { 1495 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1496 } 1497 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1498 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1499 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1500 list_del(&loc_rule->list); 1501 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1502 } 1503 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1504 memcpy(&loc_rule->fs, &cmd->fs, 1505 sizeof(struct ethtool_rx_flow_spec)); 1506 1507 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1508 1509 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1510 1511 return 0; 1512 } 1513 1514 static int bcmgenet_delete_flow(struct net_device *dev, 1515 struct ethtool_rxnfc *cmd) 1516 { 1517 struct bcmgenet_priv *priv = netdev_priv(dev); 1518 struct bcmgenet_rxnfc_rule *rule; 1519 int err = 0; 1520 1521 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1522 return -EINVAL; 1523 1524 rule = &priv->rxnfc_rules[cmd->fs.location]; 1525 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1526 err = -ENOENT; 1527 goto out; 1528 } 1529 1530 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1531 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1532 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1533 list_del(&rule->list); 1534 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1535 } 1536 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1537 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1538 1539 out: 1540 return err; 1541 } 1542 1543 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1544 { 1545 struct bcmgenet_priv *priv = netdev_priv(dev); 1546 int err = 0; 1547 1548 switch (cmd->cmd) { 1549 case ETHTOOL_SRXCLSRLINS: 1550 err = bcmgenet_insert_flow(dev, cmd); 1551 break; 1552 case ETHTOOL_SRXCLSRLDEL: 1553 err = bcmgenet_delete_flow(dev, cmd); 1554 break; 1555 default: 1556 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1557 cmd->cmd); 1558 return -EINVAL; 1559 } 1560 1561 return err; 1562 } 1563 1564 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1565 int loc) 1566 { 1567 struct bcmgenet_priv *priv = netdev_priv(dev); 1568 struct bcmgenet_rxnfc_rule *rule; 1569 int err = 0; 1570 1571 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1572 return -EINVAL; 1573 1574 rule = &priv->rxnfc_rules[loc]; 1575 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1576 err = -ENOENT; 1577 else 1578 memcpy(&cmd->fs, &rule->fs, 1579 sizeof(struct ethtool_rx_flow_spec)); 1580 1581 return err; 1582 } 1583 1584 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1585 { 1586 struct list_head *pos; 1587 int res = 0; 1588 1589 list_for_each(pos, &priv->rxnfc_list) 1590 res++; 1591 1592 return res; 1593 } 1594 1595 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1596 u32 *rule_locs) 1597 { 1598 struct bcmgenet_priv *priv = netdev_priv(dev); 1599 struct bcmgenet_rxnfc_rule *rule; 1600 int err = 0; 1601 int i = 0; 1602 1603 switch (cmd->cmd) { 1604 case ETHTOOL_GRXRINGS: 1605 cmd->data = priv->hw_params->rx_queues ?: 1; 1606 break; 1607 case ETHTOOL_GRXCLSRLCNT: 1608 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1609 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL; 1610 break; 1611 case ETHTOOL_GRXCLSRULE: 1612 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1613 break; 1614 case ETHTOOL_GRXCLSRLALL: 1615 list_for_each_entry(rule, &priv->rxnfc_list, list) 1616 if (i < cmd->rule_cnt) 1617 rule_locs[i++] = rule->fs.location; 1618 cmd->rule_cnt = i; 1619 cmd->data = MAX_NUM_OF_FS_RULES; 1620 break; 1621 default: 1622 err = -EOPNOTSUPP; 1623 break; 1624 } 1625 1626 return err; 1627 } 1628 1629 /* standard ethtool support functions. */ 1630 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1631 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1632 ETHTOOL_COALESCE_MAX_FRAMES | 1633 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1634 .begin = bcmgenet_begin, 1635 .complete = bcmgenet_complete, 1636 .get_strings = bcmgenet_get_strings, 1637 .get_sset_count = bcmgenet_get_sset_count, 1638 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1639 .get_drvinfo = bcmgenet_get_drvinfo, 1640 .get_link = ethtool_op_get_link, 1641 .get_msglevel = bcmgenet_get_msglevel, 1642 .set_msglevel = bcmgenet_set_msglevel, 1643 .get_wol = bcmgenet_get_wol, 1644 .set_wol = bcmgenet_set_wol, 1645 .get_eee = bcmgenet_get_eee, 1646 .set_eee = bcmgenet_set_eee, 1647 .nway_reset = phy_ethtool_nway_reset, 1648 .get_coalesce = bcmgenet_get_coalesce, 1649 .set_coalesce = bcmgenet_set_coalesce, 1650 .get_link_ksettings = bcmgenet_get_link_ksettings, 1651 .set_link_ksettings = bcmgenet_set_link_ksettings, 1652 .get_ts_info = ethtool_op_get_ts_info, 1653 .get_rxnfc = bcmgenet_get_rxnfc, 1654 .set_rxnfc = bcmgenet_set_rxnfc, 1655 .get_pauseparam = bcmgenet_get_pauseparam, 1656 .set_pauseparam = bcmgenet_set_pauseparam, 1657 }; 1658 1659 /* Power down the unimac, based on mode. */ 1660 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1661 enum bcmgenet_power_mode mode) 1662 { 1663 int ret = 0; 1664 u32 reg; 1665 1666 switch (mode) { 1667 case GENET_POWER_CABLE_SENSE: 1668 phy_detach(priv->dev->phydev); 1669 break; 1670 1671 case GENET_POWER_WOL_MAGIC: 1672 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1673 break; 1674 1675 case GENET_POWER_PASSIVE: 1676 /* Power down LED */ 1677 if (priv->hw_params->flags & GENET_HAS_EXT) { 1678 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1679 if (GENET_IS_V5(priv) && !priv->ephy_16nm) 1680 reg |= EXT_PWR_DOWN_PHY_EN | 1681 EXT_PWR_DOWN_PHY_RD | 1682 EXT_PWR_DOWN_PHY_SD | 1683 EXT_PWR_DOWN_PHY_RX | 1684 EXT_PWR_DOWN_PHY_TX | 1685 EXT_IDDQ_GLBL_PWR; 1686 else 1687 reg |= EXT_PWR_DOWN_PHY; 1688 1689 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1690 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1691 1692 bcmgenet_phy_power_set(priv->dev, false); 1693 } 1694 break; 1695 default: 1696 break; 1697 } 1698 1699 return ret; 1700 } 1701 1702 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1703 enum bcmgenet_power_mode mode) 1704 { 1705 u32 reg; 1706 1707 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1708 return; 1709 1710 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1711 1712 switch (mode) { 1713 case GENET_POWER_PASSIVE: 1714 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1715 EXT_ENERGY_DET_MASK); 1716 if (GENET_IS_V5(priv) && !priv->ephy_16nm) { 1717 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1718 EXT_PWR_DOWN_PHY_RD | 1719 EXT_PWR_DOWN_PHY_SD | 1720 EXT_PWR_DOWN_PHY_RX | 1721 EXT_PWR_DOWN_PHY_TX | 1722 EXT_IDDQ_GLBL_PWR); 1723 reg |= EXT_PHY_RESET; 1724 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1725 mdelay(1); 1726 1727 reg &= ~EXT_PHY_RESET; 1728 } else { 1729 reg &= ~EXT_PWR_DOWN_PHY; 1730 reg |= EXT_PWR_DN_EN_LD; 1731 } 1732 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1733 bcmgenet_phy_power_set(priv->dev, true); 1734 break; 1735 1736 case GENET_POWER_CABLE_SENSE: 1737 /* enable APD */ 1738 if (!GENET_IS_V5(priv)) { 1739 reg |= EXT_PWR_DN_EN_LD; 1740 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1741 } 1742 break; 1743 case GENET_POWER_WOL_MAGIC: 1744 bcmgenet_wol_power_up_cfg(priv, mode); 1745 return; 1746 default: 1747 break; 1748 } 1749 } 1750 1751 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1752 struct bcmgenet_tx_ring *ring) 1753 { 1754 struct enet_cb *tx_cb_ptr; 1755 1756 tx_cb_ptr = ring->cbs; 1757 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1758 1759 /* Advancing local write pointer */ 1760 if (ring->write_ptr == ring->end_ptr) 1761 ring->write_ptr = ring->cb_ptr; 1762 else 1763 ring->write_ptr++; 1764 1765 return tx_cb_ptr; 1766 } 1767 1768 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1769 struct bcmgenet_tx_ring *ring) 1770 { 1771 struct enet_cb *tx_cb_ptr; 1772 1773 tx_cb_ptr = ring->cbs; 1774 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1775 1776 /* Rewinding local write pointer */ 1777 if (ring->write_ptr == ring->cb_ptr) 1778 ring->write_ptr = ring->end_ptr; 1779 else 1780 ring->write_ptr--; 1781 1782 return tx_cb_ptr; 1783 } 1784 1785 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1786 { 1787 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1788 INTRL2_CPU_MASK_SET); 1789 } 1790 1791 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1792 { 1793 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1794 INTRL2_CPU_MASK_CLEAR); 1795 } 1796 1797 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1798 { 1799 bcmgenet_intrl2_1_writel(ring->priv, 1800 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1801 INTRL2_CPU_MASK_SET); 1802 } 1803 1804 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1805 { 1806 bcmgenet_intrl2_1_writel(ring->priv, 1807 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1808 INTRL2_CPU_MASK_CLEAR); 1809 } 1810 1811 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1812 { 1813 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1814 INTRL2_CPU_MASK_SET); 1815 } 1816 1817 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1818 { 1819 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1820 INTRL2_CPU_MASK_CLEAR); 1821 } 1822 1823 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1824 { 1825 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1826 INTRL2_CPU_MASK_CLEAR); 1827 } 1828 1829 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1830 { 1831 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1832 INTRL2_CPU_MASK_SET); 1833 } 1834 1835 /* Simple helper to free a transmit control block's resources 1836 * Returns an skb when the last transmit control block associated with the 1837 * skb is freed. The skb should be freed by the caller if necessary. 1838 */ 1839 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1840 struct enet_cb *cb) 1841 { 1842 struct sk_buff *skb; 1843 1844 skb = cb->skb; 1845 1846 if (skb) { 1847 cb->skb = NULL; 1848 if (cb == GENET_CB(skb)->first_cb) 1849 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1850 dma_unmap_len(cb, dma_len), 1851 DMA_TO_DEVICE); 1852 else 1853 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1854 dma_unmap_len(cb, dma_len), 1855 DMA_TO_DEVICE); 1856 dma_unmap_addr_set(cb, dma_addr, 0); 1857 1858 if (cb == GENET_CB(skb)->last_cb) 1859 return skb; 1860 1861 } else if (dma_unmap_addr(cb, dma_addr)) { 1862 dma_unmap_page(dev, 1863 dma_unmap_addr(cb, dma_addr), 1864 dma_unmap_len(cb, dma_len), 1865 DMA_TO_DEVICE); 1866 dma_unmap_addr_set(cb, dma_addr, 0); 1867 } 1868 1869 return NULL; 1870 } 1871 1872 /* Simple helper to free a receive control block's resources */ 1873 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1874 struct enet_cb *cb) 1875 { 1876 struct sk_buff *skb; 1877 1878 skb = cb->skb; 1879 cb->skb = NULL; 1880 1881 if (dma_unmap_addr(cb, dma_addr)) { 1882 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1883 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1884 dma_unmap_addr_set(cb, dma_addr, 0); 1885 } 1886 1887 return skb; 1888 } 1889 1890 /* Unlocked version of the reclaim routine */ 1891 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1892 struct bcmgenet_tx_ring *ring) 1893 { 1894 struct bcmgenet_priv *priv = netdev_priv(dev); 1895 unsigned int txbds_processed = 0; 1896 unsigned int bytes_compl = 0; 1897 unsigned int pkts_compl = 0; 1898 unsigned int txbds_ready; 1899 unsigned int c_index; 1900 struct sk_buff *skb; 1901 1902 /* Clear status before servicing to reduce spurious interrupts */ 1903 if (ring->index == DESC_INDEX) 1904 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1905 INTRL2_CPU_CLEAR); 1906 else 1907 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1908 INTRL2_CPU_CLEAR); 1909 1910 /* Compute how many buffers are transmitted since last xmit call */ 1911 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1912 & DMA_C_INDEX_MASK; 1913 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1914 1915 netif_dbg(priv, tx_done, dev, 1916 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1917 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1918 1919 /* Reclaim transmitted buffers */ 1920 while (txbds_processed < txbds_ready) { 1921 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1922 &priv->tx_cbs[ring->clean_ptr]); 1923 if (skb) { 1924 pkts_compl++; 1925 bytes_compl += GENET_CB(skb)->bytes_sent; 1926 dev_consume_skb_any(skb); 1927 } 1928 1929 txbds_processed++; 1930 if (likely(ring->clean_ptr < ring->end_ptr)) 1931 ring->clean_ptr++; 1932 else 1933 ring->clean_ptr = ring->cb_ptr; 1934 } 1935 1936 ring->free_bds += txbds_processed; 1937 ring->c_index = c_index; 1938 1939 ring->packets += pkts_compl; 1940 ring->bytes += bytes_compl; 1941 1942 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1943 pkts_compl, bytes_compl); 1944 1945 return txbds_processed; 1946 } 1947 1948 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1949 struct bcmgenet_tx_ring *ring) 1950 { 1951 unsigned int released; 1952 1953 spin_lock_bh(&ring->lock); 1954 released = __bcmgenet_tx_reclaim(dev, ring); 1955 spin_unlock_bh(&ring->lock); 1956 1957 return released; 1958 } 1959 1960 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1961 { 1962 struct bcmgenet_tx_ring *ring = 1963 container_of(napi, struct bcmgenet_tx_ring, napi); 1964 unsigned int work_done = 0; 1965 struct netdev_queue *txq; 1966 1967 spin_lock(&ring->lock); 1968 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1969 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1970 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1971 netif_tx_wake_queue(txq); 1972 } 1973 spin_unlock(&ring->lock); 1974 1975 if (work_done == 0) { 1976 napi_complete(napi); 1977 ring->int_enable(ring); 1978 1979 return 0; 1980 } 1981 1982 return budget; 1983 } 1984 1985 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1986 { 1987 struct bcmgenet_priv *priv = netdev_priv(dev); 1988 int i; 1989 1990 if (netif_is_multiqueue(dev)) { 1991 for (i = 0; i < priv->hw_params->tx_queues; i++) 1992 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1993 } 1994 1995 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1996 } 1997 1998 /* Reallocate the SKB to put enough headroom in front of it and insert 1999 * the transmit checksum offsets in the descriptors 2000 */ 2001 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2002 struct sk_buff *skb) 2003 { 2004 struct bcmgenet_priv *priv = netdev_priv(dev); 2005 struct status_64 *status = NULL; 2006 struct sk_buff *new_skb; 2007 u16 offset; 2008 u8 ip_proto; 2009 __be16 ip_ver; 2010 u32 tx_csum_info; 2011 2012 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2013 /* If 64 byte status block enabled, must make sure skb has 2014 * enough headroom for us to insert 64B status block. 2015 */ 2016 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2017 if (!new_skb) { 2018 dev_kfree_skb_any(skb); 2019 priv->mib.tx_realloc_tsb_failed++; 2020 dev->stats.tx_dropped++; 2021 return NULL; 2022 } 2023 dev_consume_skb_any(skb); 2024 skb = new_skb; 2025 priv->mib.tx_realloc_tsb++; 2026 } 2027 2028 skb_push(skb, sizeof(*status)); 2029 status = (struct status_64 *)skb->data; 2030 2031 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2032 ip_ver = skb->protocol; 2033 switch (ip_ver) { 2034 case htons(ETH_P_IP): 2035 ip_proto = ip_hdr(skb)->protocol; 2036 break; 2037 case htons(ETH_P_IPV6): 2038 ip_proto = ipv6_hdr(skb)->nexthdr; 2039 break; 2040 default: 2041 /* don't use UDP flag */ 2042 ip_proto = 0; 2043 break; 2044 } 2045 2046 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2047 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2048 (offset + skb->csum_offset) | 2049 STATUS_TX_CSUM_LV; 2050 2051 /* Set the special UDP flag for UDP */ 2052 if (ip_proto == IPPROTO_UDP) 2053 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2054 2055 status->tx_csum_info = tx_csum_info; 2056 } 2057 2058 return skb; 2059 } 2060 2061 static void bcmgenet_hide_tsb(struct sk_buff *skb) 2062 { 2063 __skb_pull(skb, sizeof(struct status_64)); 2064 } 2065 2066 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2067 { 2068 struct bcmgenet_priv *priv = netdev_priv(dev); 2069 struct device *kdev = &priv->pdev->dev; 2070 struct bcmgenet_tx_ring *ring = NULL; 2071 struct enet_cb *tx_cb_ptr; 2072 struct netdev_queue *txq; 2073 int nr_frags, index; 2074 dma_addr_t mapping; 2075 unsigned int size; 2076 skb_frag_t *frag; 2077 u32 len_stat; 2078 int ret; 2079 int i; 2080 2081 index = skb_get_queue_mapping(skb); 2082 /* Mapping strategy: 2083 * queue_mapping = 0, unclassified, packet xmited through ring16 2084 * queue_mapping = 1, goes to ring 0. (highest priority queue 2085 * queue_mapping = 2, goes to ring 1. 2086 * queue_mapping = 3, goes to ring 2. 2087 * queue_mapping = 4, goes to ring 3. 2088 */ 2089 if (index == 0) 2090 index = DESC_INDEX; 2091 else 2092 index -= 1; 2093 2094 ring = &priv->tx_rings[index]; 2095 txq = netdev_get_tx_queue(dev, ring->queue); 2096 2097 nr_frags = skb_shinfo(skb)->nr_frags; 2098 2099 spin_lock(&ring->lock); 2100 if (ring->free_bds <= (nr_frags + 1)) { 2101 if (!netif_tx_queue_stopped(txq)) { 2102 netif_tx_stop_queue(txq); 2103 netdev_err(dev, 2104 "%s: tx ring %d full when queue %d awake\n", 2105 __func__, index, ring->queue); 2106 } 2107 ret = NETDEV_TX_BUSY; 2108 goto out; 2109 } 2110 2111 /* Retain how many bytes will be sent on the wire, without TSB inserted 2112 * by transmit checksum offload 2113 */ 2114 GENET_CB(skb)->bytes_sent = skb->len; 2115 2116 /* add the Transmit Status Block */ 2117 skb = bcmgenet_add_tsb(dev, skb); 2118 if (!skb) { 2119 ret = NETDEV_TX_OK; 2120 goto out; 2121 } 2122 2123 for (i = 0; i <= nr_frags; i++) { 2124 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2125 2126 BUG_ON(!tx_cb_ptr); 2127 2128 if (!i) { 2129 /* Transmit single SKB or head of fragment list */ 2130 GENET_CB(skb)->first_cb = tx_cb_ptr; 2131 size = skb_headlen(skb); 2132 mapping = dma_map_single(kdev, skb->data, size, 2133 DMA_TO_DEVICE); 2134 } else { 2135 /* xmit fragment */ 2136 frag = &skb_shinfo(skb)->frags[i - 1]; 2137 size = skb_frag_size(frag); 2138 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2139 DMA_TO_DEVICE); 2140 } 2141 2142 ret = dma_mapping_error(kdev, mapping); 2143 if (ret) { 2144 priv->mib.tx_dma_failed++; 2145 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2146 ret = NETDEV_TX_OK; 2147 goto out_unmap_frags; 2148 } 2149 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2150 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2151 2152 tx_cb_ptr->skb = skb; 2153 2154 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2155 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2156 2157 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2158 * will need to restore software padding of "runt" packets 2159 */ 2160 if (!i) { 2161 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 2162 if (skb->ip_summed == CHECKSUM_PARTIAL) 2163 len_stat |= DMA_TX_DO_CSUM; 2164 } 2165 if (i == nr_frags) 2166 len_stat |= DMA_EOP; 2167 2168 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2169 } 2170 2171 GENET_CB(skb)->last_cb = tx_cb_ptr; 2172 2173 bcmgenet_hide_tsb(skb); 2174 skb_tx_timestamp(skb); 2175 2176 /* Decrement total BD count and advance our write pointer */ 2177 ring->free_bds -= nr_frags + 1; 2178 ring->prod_index += nr_frags + 1; 2179 ring->prod_index &= DMA_P_INDEX_MASK; 2180 2181 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2182 2183 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2184 netif_tx_stop_queue(txq); 2185 2186 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2187 /* Packets are ready, update producer index */ 2188 bcmgenet_tdma_ring_writel(priv, ring->index, 2189 ring->prod_index, TDMA_PROD_INDEX); 2190 out: 2191 spin_unlock(&ring->lock); 2192 2193 return ret; 2194 2195 out_unmap_frags: 2196 /* Back up for failed control block mapping */ 2197 bcmgenet_put_txcb(priv, ring); 2198 2199 /* Unmap successfully mapped control blocks */ 2200 while (i-- > 0) { 2201 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2202 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2203 } 2204 2205 dev_kfree_skb(skb); 2206 goto out; 2207 } 2208 2209 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2210 struct enet_cb *cb) 2211 { 2212 struct device *kdev = &priv->pdev->dev; 2213 struct sk_buff *skb; 2214 struct sk_buff *rx_skb; 2215 dma_addr_t mapping; 2216 2217 /* Allocate a new Rx skb */ 2218 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2219 GFP_ATOMIC | __GFP_NOWARN); 2220 if (!skb) { 2221 priv->mib.alloc_rx_buff_failed++; 2222 netif_err(priv, rx_err, priv->dev, 2223 "%s: Rx skb allocation failed\n", __func__); 2224 return NULL; 2225 } 2226 2227 /* DMA-map the new Rx skb */ 2228 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2229 DMA_FROM_DEVICE); 2230 if (dma_mapping_error(kdev, mapping)) { 2231 priv->mib.rx_dma_failed++; 2232 dev_kfree_skb_any(skb); 2233 netif_err(priv, rx_err, priv->dev, 2234 "%s: Rx skb DMA mapping failed\n", __func__); 2235 return NULL; 2236 } 2237 2238 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2239 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2240 2241 /* Put the new Rx skb on the ring */ 2242 cb->skb = skb; 2243 dma_unmap_addr_set(cb, dma_addr, mapping); 2244 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2245 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2246 2247 /* Return the current Rx skb to caller */ 2248 return rx_skb; 2249 } 2250 2251 /* bcmgenet_desc_rx - descriptor based rx process. 2252 * this could be called from bottom half, or from NAPI polling method. 2253 */ 2254 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2255 unsigned int budget) 2256 { 2257 struct bcmgenet_priv *priv = ring->priv; 2258 struct net_device *dev = priv->dev; 2259 struct enet_cb *cb; 2260 struct sk_buff *skb; 2261 u32 dma_length_status; 2262 unsigned long dma_flag; 2263 int len; 2264 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2265 unsigned int bytes_processed = 0; 2266 unsigned int p_index, mask; 2267 unsigned int discards; 2268 2269 /* Clear status before servicing to reduce spurious interrupts */ 2270 if (ring->index == DESC_INDEX) { 2271 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 2272 INTRL2_CPU_CLEAR); 2273 } else { 2274 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2275 bcmgenet_intrl2_1_writel(priv, 2276 mask, 2277 INTRL2_CPU_CLEAR); 2278 } 2279 2280 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2281 2282 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2283 DMA_P_INDEX_DISCARD_CNT_MASK; 2284 if (discards > ring->old_discards) { 2285 discards = discards - ring->old_discards; 2286 ring->errors += discards; 2287 ring->old_discards += discards; 2288 2289 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2290 if (ring->old_discards >= 0xC000) { 2291 ring->old_discards = 0; 2292 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2293 RDMA_PROD_INDEX); 2294 } 2295 } 2296 2297 p_index &= DMA_P_INDEX_MASK; 2298 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2299 2300 netif_dbg(priv, rx_status, dev, 2301 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2302 2303 while ((rxpktprocessed < rxpkttoprocess) && 2304 (rxpktprocessed < budget)) { 2305 struct status_64 *status; 2306 __be16 rx_csum; 2307 2308 cb = &priv->rx_cbs[ring->read_ptr]; 2309 skb = bcmgenet_rx_refill(priv, cb); 2310 2311 if (unlikely(!skb)) { 2312 ring->dropped++; 2313 goto next; 2314 } 2315 2316 status = (struct status_64 *)skb->data; 2317 dma_length_status = status->length_status; 2318 if (dev->features & NETIF_F_RXCSUM) { 2319 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2320 if (rx_csum) { 2321 skb->csum = (__force __wsum)ntohs(rx_csum); 2322 skb->ip_summed = CHECKSUM_COMPLETE; 2323 } 2324 } 2325 2326 /* DMA flags and length are still valid no matter how 2327 * we got the Receive Status Vector (64B RSB or register) 2328 */ 2329 dma_flag = dma_length_status & 0xffff; 2330 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2331 2332 netif_dbg(priv, rx_status, dev, 2333 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2334 __func__, p_index, ring->c_index, 2335 ring->read_ptr, dma_length_status); 2336 2337 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2338 netif_err(priv, rx_status, dev, 2339 "dropping fragmented packet!\n"); 2340 ring->errors++; 2341 dev_kfree_skb_any(skb); 2342 goto next; 2343 } 2344 2345 /* report errors */ 2346 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2347 DMA_RX_OV | 2348 DMA_RX_NO | 2349 DMA_RX_LG | 2350 DMA_RX_RXER))) { 2351 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2352 (unsigned int)dma_flag); 2353 if (dma_flag & DMA_RX_CRC_ERROR) 2354 dev->stats.rx_crc_errors++; 2355 if (dma_flag & DMA_RX_OV) 2356 dev->stats.rx_over_errors++; 2357 if (dma_flag & DMA_RX_NO) 2358 dev->stats.rx_frame_errors++; 2359 if (dma_flag & DMA_RX_LG) 2360 dev->stats.rx_length_errors++; 2361 dev->stats.rx_errors++; 2362 dev_kfree_skb_any(skb); 2363 goto next; 2364 } /* error packet */ 2365 2366 skb_put(skb, len); 2367 2368 /* remove RSB and hardware 2bytes added for IP alignment */ 2369 skb_pull(skb, 66); 2370 len -= 66; 2371 2372 if (priv->crc_fwd_en) { 2373 skb_trim(skb, len - ETH_FCS_LEN); 2374 len -= ETH_FCS_LEN; 2375 } 2376 2377 bytes_processed += len; 2378 2379 /*Finish setting up the received SKB and send it to the kernel*/ 2380 skb->protocol = eth_type_trans(skb, priv->dev); 2381 ring->packets++; 2382 ring->bytes += len; 2383 if (dma_flag & DMA_RX_MULT) 2384 dev->stats.multicast++; 2385 2386 /* Notify kernel */ 2387 napi_gro_receive(&ring->napi, skb); 2388 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2389 2390 next: 2391 rxpktprocessed++; 2392 if (likely(ring->read_ptr < ring->end_ptr)) 2393 ring->read_ptr++; 2394 else 2395 ring->read_ptr = ring->cb_ptr; 2396 2397 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2398 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2399 } 2400 2401 ring->dim.bytes = bytes_processed; 2402 ring->dim.packets = rxpktprocessed; 2403 2404 return rxpktprocessed; 2405 } 2406 2407 /* Rx NAPI polling method */ 2408 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2409 { 2410 struct bcmgenet_rx_ring *ring = container_of(napi, 2411 struct bcmgenet_rx_ring, napi); 2412 struct dim_sample dim_sample = {}; 2413 unsigned int work_done; 2414 2415 work_done = bcmgenet_desc_rx(ring, budget); 2416 2417 if (work_done < budget) { 2418 napi_complete_done(napi, work_done); 2419 ring->int_enable(ring); 2420 } 2421 2422 if (ring->dim.use_dim) { 2423 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2424 ring->dim.bytes, &dim_sample); 2425 net_dim(&ring->dim.dim, dim_sample); 2426 } 2427 2428 return work_done; 2429 } 2430 2431 static void bcmgenet_dim_work(struct work_struct *work) 2432 { 2433 struct dim *dim = container_of(work, struct dim, work); 2434 struct bcmgenet_net_dim *ndim = 2435 container_of(dim, struct bcmgenet_net_dim, dim); 2436 struct bcmgenet_rx_ring *ring = 2437 container_of(ndim, struct bcmgenet_rx_ring, dim); 2438 struct dim_cq_moder cur_profile = 2439 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2440 2441 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2442 dim->state = DIM_START_MEASURE; 2443 } 2444 2445 /* Assign skb to RX DMA descriptor. */ 2446 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2447 struct bcmgenet_rx_ring *ring) 2448 { 2449 struct enet_cb *cb; 2450 struct sk_buff *skb; 2451 int i; 2452 2453 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2454 2455 /* loop here for each buffer needing assign */ 2456 for (i = 0; i < ring->size; i++) { 2457 cb = ring->cbs + i; 2458 skb = bcmgenet_rx_refill(priv, cb); 2459 if (skb) 2460 dev_consume_skb_any(skb); 2461 if (!cb->skb) 2462 return -ENOMEM; 2463 } 2464 2465 return 0; 2466 } 2467 2468 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2469 { 2470 struct sk_buff *skb; 2471 struct enet_cb *cb; 2472 int i; 2473 2474 for (i = 0; i < priv->num_rx_bds; i++) { 2475 cb = &priv->rx_cbs[i]; 2476 2477 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2478 if (skb) 2479 dev_consume_skb_any(skb); 2480 } 2481 } 2482 2483 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2484 { 2485 u32 reg; 2486 2487 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2488 if (reg & CMD_SW_RESET) 2489 return; 2490 if (enable) 2491 reg |= mask; 2492 else 2493 reg &= ~mask; 2494 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2495 2496 /* UniMAC stops on a packet boundary, wait for a full-size packet 2497 * to be processed 2498 */ 2499 if (enable == 0) 2500 usleep_range(1000, 2000); 2501 } 2502 2503 static void reset_umac(struct bcmgenet_priv *priv) 2504 { 2505 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2506 bcmgenet_rbuf_ctrl_set(priv, 0); 2507 udelay(10); 2508 2509 /* issue soft reset and disable MAC while updating its registers */ 2510 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2511 udelay(2); 2512 } 2513 2514 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2515 { 2516 /* Mask all interrupts.*/ 2517 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2518 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2519 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2520 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2521 } 2522 2523 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2524 { 2525 u32 int0_enable = 0; 2526 2527 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2528 * and MoCA PHY 2529 */ 2530 if (priv->internal_phy) { 2531 int0_enable |= UMAC_IRQ_LINK_EVENT; 2532 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2533 int0_enable |= UMAC_IRQ_PHY_DET_R; 2534 } else if (priv->ext_phy) { 2535 int0_enable |= UMAC_IRQ_LINK_EVENT; 2536 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2537 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2538 int0_enable |= UMAC_IRQ_LINK_EVENT; 2539 } 2540 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2541 } 2542 2543 static void init_umac(struct bcmgenet_priv *priv) 2544 { 2545 struct device *kdev = &priv->pdev->dev; 2546 u32 reg; 2547 u32 int0_enable = 0; 2548 2549 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2550 2551 reset_umac(priv); 2552 2553 /* clear tx/rx counter */ 2554 bcmgenet_umac_writel(priv, 2555 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2556 UMAC_MIB_CTRL); 2557 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2558 2559 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2560 2561 /* init tx registers, enable TSB */ 2562 reg = bcmgenet_tbuf_ctrl_get(priv); 2563 reg |= TBUF_64B_EN; 2564 bcmgenet_tbuf_ctrl_set(priv, reg); 2565 2566 /* init rx registers, enable ip header optimization and RSB */ 2567 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2568 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2569 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2570 2571 /* enable rx checksumming */ 2572 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2573 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2574 /* If UniMAC forwards CRC, we need to skip over it to get 2575 * a valid CHK bit to be set in the per-packet status word 2576 */ 2577 if (priv->crc_fwd_en) 2578 reg |= RBUF_SKIP_FCS; 2579 else 2580 reg &= ~RBUF_SKIP_FCS; 2581 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2582 2583 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2584 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2585 2586 bcmgenet_intr_disable(priv); 2587 2588 /* Configure backpressure vectors for MoCA */ 2589 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2590 reg = bcmgenet_bp_mc_get(priv); 2591 reg |= BIT(priv->hw_params->bp_in_en_shift); 2592 2593 /* bp_mask: back pressure mask */ 2594 if (netif_is_multiqueue(priv->dev)) 2595 reg |= priv->hw_params->bp_in_mask; 2596 else 2597 reg &= ~priv->hw_params->bp_in_mask; 2598 bcmgenet_bp_mc_set(priv, reg); 2599 } 2600 2601 /* Enable MDIO interrupts on GENET v3+ */ 2602 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2603 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2604 2605 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2606 2607 dev_dbg(kdev, "done init umac\n"); 2608 } 2609 2610 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2611 void (*cb)(struct work_struct *work)) 2612 { 2613 struct bcmgenet_net_dim *dim = &ring->dim; 2614 2615 INIT_WORK(&dim->dim.work, cb); 2616 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2617 dim->event_ctr = 0; 2618 dim->packets = 0; 2619 dim->bytes = 0; 2620 } 2621 2622 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2623 { 2624 struct bcmgenet_net_dim *dim = &ring->dim; 2625 struct dim_cq_moder moder; 2626 u32 usecs, pkts; 2627 2628 usecs = ring->rx_coalesce_usecs; 2629 pkts = ring->rx_max_coalesced_frames; 2630 2631 /* If DIM was enabled, re-apply default parameters */ 2632 if (dim->use_dim) { 2633 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2634 usecs = moder.usec; 2635 pkts = moder.pkts; 2636 } 2637 2638 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2639 } 2640 2641 /* Initialize a Tx ring along with corresponding hardware registers */ 2642 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2643 unsigned int index, unsigned int size, 2644 unsigned int start_ptr, unsigned int end_ptr) 2645 { 2646 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2647 u32 words_per_bd = WORDS_PER_BD(priv); 2648 u32 flow_period_val = 0; 2649 2650 spin_lock_init(&ring->lock); 2651 ring->priv = priv; 2652 ring->index = index; 2653 if (index == DESC_INDEX) { 2654 ring->queue = 0; 2655 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2656 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2657 } else { 2658 ring->queue = index + 1; 2659 ring->int_enable = bcmgenet_tx_ring_int_enable; 2660 ring->int_disable = bcmgenet_tx_ring_int_disable; 2661 } 2662 ring->cbs = priv->tx_cbs + start_ptr; 2663 ring->size = size; 2664 ring->clean_ptr = start_ptr; 2665 ring->c_index = 0; 2666 ring->free_bds = size; 2667 ring->write_ptr = start_ptr; 2668 ring->cb_ptr = start_ptr; 2669 ring->end_ptr = end_ptr - 1; 2670 ring->prod_index = 0; 2671 2672 /* Set flow period for ring != 16 */ 2673 if (index != DESC_INDEX) 2674 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2675 2676 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2677 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2678 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2679 /* Disable rate control for now */ 2680 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2681 TDMA_FLOW_PERIOD); 2682 bcmgenet_tdma_ring_writel(priv, index, 2683 ((size << DMA_RING_SIZE_SHIFT) | 2684 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2685 2686 /* Set start and end address, read and write pointers */ 2687 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2688 DMA_START_ADDR); 2689 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2690 TDMA_READ_PTR); 2691 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2692 TDMA_WRITE_PTR); 2693 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2694 DMA_END_ADDR); 2695 2696 /* Initialize Tx NAPI */ 2697 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll); 2698 } 2699 2700 /* Initialize a RDMA ring */ 2701 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2702 unsigned int index, unsigned int size, 2703 unsigned int start_ptr, unsigned int end_ptr) 2704 { 2705 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2706 u32 words_per_bd = WORDS_PER_BD(priv); 2707 int ret; 2708 2709 ring->priv = priv; 2710 ring->index = index; 2711 if (index == DESC_INDEX) { 2712 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2713 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2714 } else { 2715 ring->int_enable = bcmgenet_rx_ring_int_enable; 2716 ring->int_disable = bcmgenet_rx_ring_int_disable; 2717 } 2718 ring->cbs = priv->rx_cbs + start_ptr; 2719 ring->size = size; 2720 ring->c_index = 0; 2721 ring->read_ptr = start_ptr; 2722 ring->cb_ptr = start_ptr; 2723 ring->end_ptr = end_ptr - 1; 2724 2725 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2726 if (ret) 2727 return ret; 2728 2729 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2730 bcmgenet_init_rx_coalesce(ring); 2731 2732 /* Initialize Rx NAPI */ 2733 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll); 2734 2735 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2736 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2737 bcmgenet_rdma_ring_writel(priv, index, 2738 ((size << DMA_RING_SIZE_SHIFT) | 2739 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2740 bcmgenet_rdma_ring_writel(priv, index, 2741 (DMA_FC_THRESH_LO << 2742 DMA_XOFF_THRESHOLD_SHIFT) | 2743 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2744 2745 /* Set start and end address, read and write pointers */ 2746 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2747 DMA_START_ADDR); 2748 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2749 RDMA_READ_PTR); 2750 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2751 RDMA_WRITE_PTR); 2752 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2753 DMA_END_ADDR); 2754 2755 return ret; 2756 } 2757 2758 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2759 { 2760 unsigned int i; 2761 struct bcmgenet_tx_ring *ring; 2762 2763 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2764 ring = &priv->tx_rings[i]; 2765 napi_enable(&ring->napi); 2766 ring->int_enable(ring); 2767 } 2768 2769 ring = &priv->tx_rings[DESC_INDEX]; 2770 napi_enable(&ring->napi); 2771 ring->int_enable(ring); 2772 } 2773 2774 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2775 { 2776 unsigned int i; 2777 struct bcmgenet_tx_ring *ring; 2778 2779 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2780 ring = &priv->tx_rings[i]; 2781 napi_disable(&ring->napi); 2782 } 2783 2784 ring = &priv->tx_rings[DESC_INDEX]; 2785 napi_disable(&ring->napi); 2786 } 2787 2788 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2789 { 2790 unsigned int i; 2791 struct bcmgenet_tx_ring *ring; 2792 2793 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2794 ring = &priv->tx_rings[i]; 2795 netif_napi_del(&ring->napi); 2796 } 2797 2798 ring = &priv->tx_rings[DESC_INDEX]; 2799 netif_napi_del(&ring->napi); 2800 } 2801 2802 /* Initialize Tx queues 2803 * 2804 * Queues 0-3 are priority-based, each one has 32 descriptors, 2805 * with queue 0 being the highest priority queue. 2806 * 2807 * Queue 16 is the default Tx queue with 2808 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2809 * 2810 * The transmit control block pool is then partitioned as follows: 2811 * - Tx queue 0 uses tx_cbs[0..31] 2812 * - Tx queue 1 uses tx_cbs[32..63] 2813 * - Tx queue 2 uses tx_cbs[64..95] 2814 * - Tx queue 3 uses tx_cbs[96..127] 2815 * - Tx queue 16 uses tx_cbs[128..255] 2816 */ 2817 static void bcmgenet_init_tx_queues(struct net_device *dev) 2818 { 2819 struct bcmgenet_priv *priv = netdev_priv(dev); 2820 u32 i, dma_enable; 2821 u32 dma_ctrl, ring_cfg; 2822 u32 dma_priority[3] = {0, 0, 0}; 2823 2824 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2825 dma_enable = dma_ctrl & DMA_EN; 2826 dma_ctrl &= ~DMA_EN; 2827 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2828 2829 dma_ctrl = 0; 2830 ring_cfg = 0; 2831 2832 /* Enable strict priority arbiter mode */ 2833 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2834 2835 /* Initialize Tx priority queues */ 2836 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2837 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2838 i * priv->hw_params->tx_bds_per_q, 2839 (i + 1) * priv->hw_params->tx_bds_per_q); 2840 ring_cfg |= (1 << i); 2841 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2842 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2843 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2844 } 2845 2846 /* Initialize Tx default queue 16 */ 2847 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2848 priv->hw_params->tx_queues * 2849 priv->hw_params->tx_bds_per_q, 2850 TOTAL_DESC); 2851 ring_cfg |= (1 << DESC_INDEX); 2852 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2853 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2854 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2855 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2856 2857 /* Set Tx queue priorities */ 2858 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2859 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2860 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2861 2862 /* Enable Tx queues */ 2863 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2864 2865 /* Enable Tx DMA */ 2866 if (dma_enable) 2867 dma_ctrl |= DMA_EN; 2868 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2869 } 2870 2871 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2872 { 2873 unsigned int i; 2874 struct bcmgenet_rx_ring *ring; 2875 2876 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2877 ring = &priv->rx_rings[i]; 2878 napi_enable(&ring->napi); 2879 ring->int_enable(ring); 2880 } 2881 2882 ring = &priv->rx_rings[DESC_INDEX]; 2883 napi_enable(&ring->napi); 2884 ring->int_enable(ring); 2885 } 2886 2887 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2888 { 2889 unsigned int i; 2890 struct bcmgenet_rx_ring *ring; 2891 2892 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2893 ring = &priv->rx_rings[i]; 2894 napi_disable(&ring->napi); 2895 cancel_work_sync(&ring->dim.dim.work); 2896 } 2897 2898 ring = &priv->rx_rings[DESC_INDEX]; 2899 napi_disable(&ring->napi); 2900 cancel_work_sync(&ring->dim.dim.work); 2901 } 2902 2903 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2904 { 2905 unsigned int i; 2906 struct bcmgenet_rx_ring *ring; 2907 2908 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2909 ring = &priv->rx_rings[i]; 2910 netif_napi_del(&ring->napi); 2911 } 2912 2913 ring = &priv->rx_rings[DESC_INDEX]; 2914 netif_napi_del(&ring->napi); 2915 } 2916 2917 /* Initialize Rx queues 2918 * 2919 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2920 * used to direct traffic to these queues. 2921 * 2922 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2923 */ 2924 static int bcmgenet_init_rx_queues(struct net_device *dev) 2925 { 2926 struct bcmgenet_priv *priv = netdev_priv(dev); 2927 u32 i; 2928 u32 dma_enable; 2929 u32 dma_ctrl; 2930 u32 ring_cfg; 2931 int ret; 2932 2933 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2934 dma_enable = dma_ctrl & DMA_EN; 2935 dma_ctrl &= ~DMA_EN; 2936 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2937 2938 dma_ctrl = 0; 2939 ring_cfg = 0; 2940 2941 /* Initialize Rx priority queues */ 2942 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2943 ret = bcmgenet_init_rx_ring(priv, i, 2944 priv->hw_params->rx_bds_per_q, 2945 i * priv->hw_params->rx_bds_per_q, 2946 (i + 1) * 2947 priv->hw_params->rx_bds_per_q); 2948 if (ret) 2949 return ret; 2950 2951 ring_cfg |= (1 << i); 2952 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2953 } 2954 2955 /* Initialize Rx default queue 16 */ 2956 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2957 priv->hw_params->rx_queues * 2958 priv->hw_params->rx_bds_per_q, 2959 TOTAL_DESC); 2960 if (ret) 2961 return ret; 2962 2963 ring_cfg |= (1 << DESC_INDEX); 2964 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2965 2966 /* Enable rings */ 2967 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2968 2969 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2970 if (dma_enable) 2971 dma_ctrl |= DMA_EN; 2972 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2973 2974 return 0; 2975 } 2976 2977 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2978 { 2979 int ret = 0; 2980 int timeout = 0; 2981 u32 reg; 2982 u32 dma_ctrl; 2983 int i; 2984 2985 /* Disable TDMA to stop add more frames in TX DMA */ 2986 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2987 reg &= ~DMA_EN; 2988 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2989 2990 /* Check TDMA status register to confirm TDMA is disabled */ 2991 while (timeout++ < DMA_TIMEOUT_VAL) { 2992 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2993 if (reg & DMA_DISABLED) 2994 break; 2995 2996 udelay(1); 2997 } 2998 2999 if (timeout == DMA_TIMEOUT_VAL) { 3000 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3001 ret = -ETIMEDOUT; 3002 } 3003 3004 /* Wait 10ms for packet drain in both tx and rx dma */ 3005 usleep_range(10000, 20000); 3006 3007 /* Disable RDMA */ 3008 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3009 reg &= ~DMA_EN; 3010 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3011 3012 timeout = 0; 3013 /* Check RDMA status register to confirm RDMA is disabled */ 3014 while (timeout++ < DMA_TIMEOUT_VAL) { 3015 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 3016 if (reg & DMA_DISABLED) 3017 break; 3018 3019 udelay(1); 3020 } 3021 3022 if (timeout == DMA_TIMEOUT_VAL) { 3023 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3024 ret = -ETIMEDOUT; 3025 } 3026 3027 dma_ctrl = 0; 3028 for (i = 0; i < priv->hw_params->rx_queues; i++) 3029 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3030 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3031 reg &= ~dma_ctrl; 3032 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3033 3034 dma_ctrl = 0; 3035 for (i = 0; i < priv->hw_params->tx_queues; i++) 3036 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3037 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3038 reg &= ~dma_ctrl; 3039 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3040 3041 return ret; 3042 } 3043 3044 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3045 { 3046 struct netdev_queue *txq; 3047 int i; 3048 3049 bcmgenet_fini_rx_napi(priv); 3050 bcmgenet_fini_tx_napi(priv); 3051 3052 for (i = 0; i < priv->num_tx_bds; i++) 3053 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 3054 priv->tx_cbs + i)); 3055 3056 for (i = 0; i < priv->hw_params->tx_queues; i++) { 3057 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 3058 netdev_tx_reset_queue(txq); 3059 } 3060 3061 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 3062 netdev_tx_reset_queue(txq); 3063 3064 bcmgenet_free_rx_buffers(priv); 3065 kfree(priv->rx_cbs); 3066 kfree(priv->tx_cbs); 3067 } 3068 3069 /* init_edma: Initialize DMA control register */ 3070 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 3071 { 3072 int ret; 3073 unsigned int i; 3074 struct enet_cb *cb; 3075 3076 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3077 3078 /* Initialize common Rx ring structures */ 3079 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3080 priv->num_rx_bds = TOTAL_DESC; 3081 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3082 GFP_KERNEL); 3083 if (!priv->rx_cbs) 3084 return -ENOMEM; 3085 3086 for (i = 0; i < priv->num_rx_bds; i++) { 3087 cb = priv->rx_cbs + i; 3088 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3089 } 3090 3091 /* Initialize common TX ring structures */ 3092 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3093 priv->num_tx_bds = TOTAL_DESC; 3094 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3095 GFP_KERNEL); 3096 if (!priv->tx_cbs) { 3097 kfree(priv->rx_cbs); 3098 return -ENOMEM; 3099 } 3100 3101 for (i = 0; i < priv->num_tx_bds; i++) { 3102 cb = priv->tx_cbs + i; 3103 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3104 } 3105 3106 /* Init rDma */ 3107 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3108 DMA_SCB_BURST_SIZE); 3109 3110 /* Initialize Rx queues */ 3111 ret = bcmgenet_init_rx_queues(priv->dev); 3112 if (ret) { 3113 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3114 bcmgenet_free_rx_buffers(priv); 3115 kfree(priv->rx_cbs); 3116 kfree(priv->tx_cbs); 3117 return ret; 3118 } 3119 3120 /* Init tDma */ 3121 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3122 DMA_SCB_BURST_SIZE); 3123 3124 /* Initialize Tx queues */ 3125 bcmgenet_init_tx_queues(priv->dev); 3126 3127 return 0; 3128 } 3129 3130 /* Interrupt bottom half */ 3131 static void bcmgenet_irq_task(struct work_struct *work) 3132 { 3133 unsigned int status; 3134 struct bcmgenet_priv *priv = container_of( 3135 work, struct bcmgenet_priv, bcmgenet_irq_work); 3136 3137 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3138 3139 spin_lock_irq(&priv->lock); 3140 status = priv->irq0_stat; 3141 priv->irq0_stat = 0; 3142 spin_unlock_irq(&priv->lock); 3143 3144 if (status & UMAC_IRQ_PHY_DET_R && 3145 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3146 phy_init_hw(priv->dev->phydev); 3147 genphy_config_aneg(priv->dev->phydev); 3148 } 3149 3150 /* Link UP/DOWN event */ 3151 if (status & UMAC_IRQ_LINK_EVENT) 3152 phy_mac_interrupt(priv->dev->phydev); 3153 3154 } 3155 3156 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 3157 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3158 { 3159 struct bcmgenet_priv *priv = dev_id; 3160 struct bcmgenet_rx_ring *rx_ring; 3161 struct bcmgenet_tx_ring *tx_ring; 3162 unsigned int index, status; 3163 3164 /* Read irq status */ 3165 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3166 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3167 3168 /* clear interrupts */ 3169 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3170 3171 netif_dbg(priv, intr, priv->dev, 3172 "%s: IRQ=0x%x\n", __func__, status); 3173 3174 /* Check Rx priority queue interrupts */ 3175 for (index = 0; index < priv->hw_params->rx_queues; index++) { 3176 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3177 continue; 3178 3179 rx_ring = &priv->rx_rings[index]; 3180 rx_ring->dim.event_ctr++; 3181 3182 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3183 rx_ring->int_disable(rx_ring); 3184 __napi_schedule_irqoff(&rx_ring->napi); 3185 } 3186 } 3187 3188 /* Check Tx priority queue interrupts */ 3189 for (index = 0; index < priv->hw_params->tx_queues; index++) { 3190 if (!(status & BIT(index))) 3191 continue; 3192 3193 tx_ring = &priv->tx_rings[index]; 3194 3195 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3196 tx_ring->int_disable(tx_ring); 3197 __napi_schedule_irqoff(&tx_ring->napi); 3198 } 3199 } 3200 3201 return IRQ_HANDLED; 3202 } 3203 3204 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 3205 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3206 { 3207 struct bcmgenet_priv *priv = dev_id; 3208 struct bcmgenet_rx_ring *rx_ring; 3209 struct bcmgenet_tx_ring *tx_ring; 3210 unsigned int status; 3211 unsigned long flags; 3212 3213 /* Read irq status */ 3214 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3215 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3216 3217 /* clear interrupts */ 3218 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3219 3220 netif_dbg(priv, intr, priv->dev, 3221 "IRQ=0x%x\n", status); 3222 3223 if (status & UMAC_IRQ_RXDMA_DONE) { 3224 rx_ring = &priv->rx_rings[DESC_INDEX]; 3225 rx_ring->dim.event_ctr++; 3226 3227 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3228 rx_ring->int_disable(rx_ring); 3229 __napi_schedule_irqoff(&rx_ring->napi); 3230 } 3231 } 3232 3233 if (status & UMAC_IRQ_TXDMA_DONE) { 3234 tx_ring = &priv->tx_rings[DESC_INDEX]; 3235 3236 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3237 tx_ring->int_disable(tx_ring); 3238 __napi_schedule_irqoff(&tx_ring->napi); 3239 } 3240 } 3241 3242 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 3243 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 3244 wake_up(&priv->wq); 3245 } 3246 3247 /* all other interested interrupts handled in bottom half */ 3248 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3249 if (status) { 3250 /* Save irq status for bottom-half processing. */ 3251 spin_lock_irqsave(&priv->lock, flags); 3252 priv->irq0_stat |= status; 3253 spin_unlock_irqrestore(&priv->lock, flags); 3254 3255 schedule_work(&priv->bcmgenet_irq_work); 3256 } 3257 3258 return IRQ_HANDLED; 3259 } 3260 3261 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3262 { 3263 /* Acknowledge the interrupt */ 3264 return IRQ_HANDLED; 3265 } 3266 3267 #ifdef CONFIG_NET_POLL_CONTROLLER 3268 static void bcmgenet_poll_controller(struct net_device *dev) 3269 { 3270 struct bcmgenet_priv *priv = netdev_priv(dev); 3271 3272 /* Invoke the main RX/TX interrupt handler */ 3273 disable_irq(priv->irq0); 3274 bcmgenet_isr0(priv->irq0, priv); 3275 enable_irq(priv->irq0); 3276 3277 /* And the interrupt handler for RX/TX priority queues */ 3278 disable_irq(priv->irq1); 3279 bcmgenet_isr1(priv->irq1, priv); 3280 enable_irq(priv->irq1); 3281 } 3282 #endif 3283 3284 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3285 { 3286 u32 reg; 3287 3288 reg = bcmgenet_rbuf_ctrl_get(priv); 3289 reg |= BIT(1); 3290 bcmgenet_rbuf_ctrl_set(priv, reg); 3291 udelay(10); 3292 3293 reg &= ~BIT(1); 3294 bcmgenet_rbuf_ctrl_set(priv, reg); 3295 udelay(10); 3296 } 3297 3298 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3299 const unsigned char *addr) 3300 { 3301 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3302 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3303 } 3304 3305 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3306 unsigned char *addr) 3307 { 3308 u32 addr_tmp; 3309 3310 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3311 put_unaligned_be32(addr_tmp, &addr[0]); 3312 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3313 put_unaligned_be16(addr_tmp, &addr[4]); 3314 } 3315 3316 /* Returns a reusable dma control register value */ 3317 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 3318 { 3319 unsigned int i; 3320 u32 reg; 3321 u32 dma_ctrl; 3322 3323 /* disable DMA */ 3324 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3325 for (i = 0; i < priv->hw_params->tx_queues; i++) 3326 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3327 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3328 reg &= ~dma_ctrl; 3329 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3330 3331 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3332 for (i = 0; i < priv->hw_params->rx_queues; i++) 3333 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3334 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3335 reg &= ~dma_ctrl; 3336 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3337 3338 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3339 udelay(10); 3340 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3341 3342 return dma_ctrl; 3343 } 3344 3345 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 3346 { 3347 u32 reg; 3348 3349 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3350 reg |= dma_ctrl; 3351 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3352 3353 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3354 reg |= dma_ctrl; 3355 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3356 } 3357 3358 static void bcmgenet_netif_start(struct net_device *dev) 3359 { 3360 struct bcmgenet_priv *priv = netdev_priv(dev); 3361 3362 /* Start the network engine */ 3363 bcmgenet_set_rx_mode(dev); 3364 bcmgenet_enable_rx_napi(priv); 3365 3366 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3367 3368 bcmgenet_enable_tx_napi(priv); 3369 3370 /* Monitor link interrupts now */ 3371 bcmgenet_link_intr_enable(priv); 3372 3373 phy_start(dev->phydev); 3374 } 3375 3376 static int bcmgenet_open(struct net_device *dev) 3377 { 3378 struct bcmgenet_priv *priv = netdev_priv(dev); 3379 unsigned long dma_ctrl; 3380 int ret; 3381 3382 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3383 3384 /* Turn on the clock */ 3385 clk_prepare_enable(priv->clk); 3386 3387 /* If this is an internal GPHY, power it back on now, before UniMAC is 3388 * brought out of reset as absolutely no UniMAC activity is allowed 3389 */ 3390 if (priv->internal_phy) 3391 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3392 3393 /* take MAC out of reset */ 3394 bcmgenet_umac_reset(priv); 3395 3396 init_umac(priv); 3397 3398 /* Apply features again in case we changed them while interface was 3399 * down 3400 */ 3401 bcmgenet_set_features(dev, dev->features); 3402 3403 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3404 3405 /* Disable RX/TX DMA and flush TX queues */ 3406 dma_ctrl = bcmgenet_dma_disable(priv); 3407 3408 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3409 ret = bcmgenet_init_dma(priv); 3410 if (ret) { 3411 netdev_err(dev, "failed to initialize DMA\n"); 3412 goto err_clk_disable; 3413 } 3414 3415 /* Always enable ring 16 - descriptor ring */ 3416 bcmgenet_enable_dma(priv, dma_ctrl); 3417 3418 /* HFB init */ 3419 bcmgenet_hfb_init(priv); 3420 3421 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3422 dev->name, priv); 3423 if (ret < 0) { 3424 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3425 goto err_fini_dma; 3426 } 3427 3428 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3429 dev->name, priv); 3430 if (ret < 0) { 3431 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3432 goto err_irq0; 3433 } 3434 3435 ret = bcmgenet_mii_probe(dev); 3436 if (ret) { 3437 netdev_err(dev, "failed to connect to PHY\n"); 3438 goto err_irq1; 3439 } 3440 3441 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 3442 3443 bcmgenet_netif_start(dev); 3444 3445 netif_tx_start_all_queues(dev); 3446 3447 return 0; 3448 3449 err_irq1: 3450 free_irq(priv->irq1, priv); 3451 err_irq0: 3452 free_irq(priv->irq0, priv); 3453 err_fini_dma: 3454 bcmgenet_dma_teardown(priv); 3455 bcmgenet_fini_dma(priv); 3456 err_clk_disable: 3457 if (priv->internal_phy) 3458 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3459 clk_disable_unprepare(priv->clk); 3460 return ret; 3461 } 3462 3463 static void bcmgenet_netif_stop(struct net_device *dev) 3464 { 3465 struct bcmgenet_priv *priv = netdev_priv(dev); 3466 3467 bcmgenet_disable_tx_napi(priv); 3468 netif_tx_disable(dev); 3469 3470 /* Disable MAC receive */ 3471 umac_enable_set(priv, CMD_RX_EN, false); 3472 3473 bcmgenet_dma_teardown(priv); 3474 3475 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3476 umac_enable_set(priv, CMD_TX_EN, false); 3477 3478 phy_stop(dev->phydev); 3479 bcmgenet_disable_rx_napi(priv); 3480 bcmgenet_intr_disable(priv); 3481 3482 /* Wait for pending work items to complete. Since interrupts are 3483 * disabled no new work will be scheduled. 3484 */ 3485 cancel_work_sync(&priv->bcmgenet_irq_work); 3486 3487 /* tx reclaim */ 3488 bcmgenet_tx_reclaim_all(dev); 3489 bcmgenet_fini_dma(priv); 3490 } 3491 3492 static int bcmgenet_close(struct net_device *dev) 3493 { 3494 struct bcmgenet_priv *priv = netdev_priv(dev); 3495 int ret = 0; 3496 3497 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3498 3499 bcmgenet_netif_stop(dev); 3500 3501 /* Really kill the PHY state machine and disconnect from it */ 3502 phy_disconnect(dev->phydev); 3503 3504 free_irq(priv->irq0, priv); 3505 free_irq(priv->irq1, priv); 3506 3507 if (priv->internal_phy) 3508 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3509 3510 clk_disable_unprepare(priv->clk); 3511 3512 return ret; 3513 } 3514 3515 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3516 { 3517 struct bcmgenet_priv *priv = ring->priv; 3518 u32 p_index, c_index, intsts, intmsk; 3519 struct netdev_queue *txq; 3520 unsigned int free_bds; 3521 bool txq_stopped; 3522 3523 if (!netif_msg_tx_err(priv)) 3524 return; 3525 3526 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3527 3528 spin_lock(&ring->lock); 3529 if (ring->index == DESC_INDEX) { 3530 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3531 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3532 } else { 3533 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3534 intmsk = 1 << ring->index; 3535 } 3536 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3537 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3538 txq_stopped = netif_tx_queue_stopped(txq); 3539 free_bds = ring->free_bds; 3540 spin_unlock(&ring->lock); 3541 3542 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3543 "TX queue status: %s, interrupts: %s\n" 3544 "(sw)free_bds: %d (sw)size: %d\n" 3545 "(sw)p_index: %d (hw)p_index: %d\n" 3546 "(sw)c_index: %d (hw)c_index: %d\n" 3547 "(sw)clean_p: %d (sw)write_p: %d\n" 3548 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3549 ring->index, ring->queue, 3550 txq_stopped ? "stopped" : "active", 3551 intsts & intmsk ? "enabled" : "disabled", 3552 free_bds, ring->size, 3553 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3554 ring->c_index, c_index & DMA_C_INDEX_MASK, 3555 ring->clean_ptr, ring->write_ptr, 3556 ring->cb_ptr, ring->end_ptr); 3557 } 3558 3559 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3560 { 3561 struct bcmgenet_priv *priv = netdev_priv(dev); 3562 u32 int0_enable = 0; 3563 u32 int1_enable = 0; 3564 unsigned int q; 3565 3566 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3567 3568 for (q = 0; q < priv->hw_params->tx_queues; q++) 3569 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3570 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3571 3572 bcmgenet_tx_reclaim_all(dev); 3573 3574 for (q = 0; q < priv->hw_params->tx_queues; q++) 3575 int1_enable |= (1 << q); 3576 3577 int0_enable = UMAC_IRQ_TXDMA_DONE; 3578 3579 /* Re-enable TX interrupts if disabled */ 3580 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3581 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3582 3583 netif_trans_update(dev); 3584 3585 dev->stats.tx_errors++; 3586 3587 netif_tx_wake_all_queues(dev); 3588 } 3589 3590 #define MAX_MDF_FILTER 17 3591 3592 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3593 const unsigned char *addr, 3594 int *i) 3595 { 3596 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3597 UMAC_MDF_ADDR + (*i * 4)); 3598 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3599 addr[4] << 8 | addr[5], 3600 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3601 *i += 2; 3602 } 3603 3604 static void bcmgenet_set_rx_mode(struct net_device *dev) 3605 { 3606 struct bcmgenet_priv *priv = netdev_priv(dev); 3607 struct netdev_hw_addr *ha; 3608 int i, nfilter; 3609 u32 reg; 3610 3611 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3612 3613 /* Number of filters needed */ 3614 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3615 3616 /* 3617 * Turn on promicuous mode for three scenarios 3618 * 1. IFF_PROMISC flag is set 3619 * 2. IFF_ALLMULTI flag is set 3620 * 3. The number of filters needed exceeds the number filters 3621 * supported by the hardware. 3622 */ 3623 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3624 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3625 (nfilter > MAX_MDF_FILTER)) { 3626 reg |= CMD_PROMISC; 3627 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3628 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3629 return; 3630 } else { 3631 reg &= ~CMD_PROMISC; 3632 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3633 } 3634 3635 /* update MDF filter */ 3636 i = 0; 3637 /* Broadcast */ 3638 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3639 /* my own address.*/ 3640 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3641 3642 /* Unicast */ 3643 netdev_for_each_uc_addr(ha, dev) 3644 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3645 3646 /* Multicast */ 3647 netdev_for_each_mc_addr(ha, dev) 3648 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3649 3650 /* Enable filters */ 3651 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3652 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3653 } 3654 3655 /* Set the hardware MAC address. */ 3656 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3657 { 3658 struct sockaddr *addr = p; 3659 3660 /* Setting the MAC address at the hardware level is not possible 3661 * without disabling the UniMAC RX/TX enable bits. 3662 */ 3663 if (netif_running(dev)) 3664 return -EBUSY; 3665 3666 eth_hw_addr_set(dev, addr->sa_data); 3667 3668 return 0; 3669 } 3670 3671 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3672 { 3673 struct bcmgenet_priv *priv = netdev_priv(dev); 3674 unsigned long tx_bytes = 0, tx_packets = 0; 3675 unsigned long rx_bytes = 0, rx_packets = 0; 3676 unsigned long rx_errors = 0, rx_dropped = 0; 3677 struct bcmgenet_tx_ring *tx_ring; 3678 struct bcmgenet_rx_ring *rx_ring; 3679 unsigned int q; 3680 3681 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3682 tx_ring = &priv->tx_rings[q]; 3683 tx_bytes += tx_ring->bytes; 3684 tx_packets += tx_ring->packets; 3685 } 3686 tx_ring = &priv->tx_rings[DESC_INDEX]; 3687 tx_bytes += tx_ring->bytes; 3688 tx_packets += tx_ring->packets; 3689 3690 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3691 rx_ring = &priv->rx_rings[q]; 3692 3693 rx_bytes += rx_ring->bytes; 3694 rx_packets += rx_ring->packets; 3695 rx_errors += rx_ring->errors; 3696 rx_dropped += rx_ring->dropped; 3697 } 3698 rx_ring = &priv->rx_rings[DESC_INDEX]; 3699 rx_bytes += rx_ring->bytes; 3700 rx_packets += rx_ring->packets; 3701 rx_errors += rx_ring->errors; 3702 rx_dropped += rx_ring->dropped; 3703 3704 dev->stats.tx_bytes = tx_bytes; 3705 dev->stats.tx_packets = tx_packets; 3706 dev->stats.rx_bytes = rx_bytes; 3707 dev->stats.rx_packets = rx_packets; 3708 dev->stats.rx_errors = rx_errors; 3709 dev->stats.rx_missed_errors = rx_errors; 3710 dev->stats.rx_dropped = rx_dropped; 3711 return &dev->stats; 3712 } 3713 3714 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3715 { 3716 struct bcmgenet_priv *priv = netdev_priv(dev); 3717 3718 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3719 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3720 return -EOPNOTSUPP; 3721 3722 if (new_carrier) 3723 netif_carrier_on(dev); 3724 else 3725 netif_carrier_off(dev); 3726 3727 return 0; 3728 } 3729 3730 static const struct net_device_ops bcmgenet_netdev_ops = { 3731 .ndo_open = bcmgenet_open, 3732 .ndo_stop = bcmgenet_close, 3733 .ndo_start_xmit = bcmgenet_xmit, 3734 .ndo_tx_timeout = bcmgenet_timeout, 3735 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3736 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3737 .ndo_eth_ioctl = phy_do_ioctl_running, 3738 .ndo_set_features = bcmgenet_set_features, 3739 #ifdef CONFIG_NET_POLL_CONTROLLER 3740 .ndo_poll_controller = bcmgenet_poll_controller, 3741 #endif 3742 .ndo_get_stats = bcmgenet_get_stats, 3743 .ndo_change_carrier = bcmgenet_change_carrier, 3744 }; 3745 3746 /* Array of GENET hardware parameters/characteristics */ 3747 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3748 [GENET_V1] = { 3749 .tx_queues = 0, 3750 .tx_bds_per_q = 0, 3751 .rx_queues = 0, 3752 .rx_bds_per_q = 0, 3753 .bp_in_en_shift = 16, 3754 .bp_in_mask = 0xffff, 3755 .hfb_filter_cnt = 16, 3756 .qtag_mask = 0x1F, 3757 .hfb_offset = 0x1000, 3758 .rdma_offset = 0x2000, 3759 .tdma_offset = 0x3000, 3760 .words_per_bd = 2, 3761 }, 3762 [GENET_V2] = { 3763 .tx_queues = 4, 3764 .tx_bds_per_q = 32, 3765 .rx_queues = 0, 3766 .rx_bds_per_q = 0, 3767 .bp_in_en_shift = 16, 3768 .bp_in_mask = 0xffff, 3769 .hfb_filter_cnt = 16, 3770 .qtag_mask = 0x1F, 3771 .tbuf_offset = 0x0600, 3772 .hfb_offset = 0x1000, 3773 .hfb_reg_offset = 0x2000, 3774 .rdma_offset = 0x3000, 3775 .tdma_offset = 0x4000, 3776 .words_per_bd = 2, 3777 .flags = GENET_HAS_EXT, 3778 }, 3779 [GENET_V3] = { 3780 .tx_queues = 4, 3781 .tx_bds_per_q = 32, 3782 .rx_queues = 0, 3783 .rx_bds_per_q = 0, 3784 .bp_in_en_shift = 17, 3785 .bp_in_mask = 0x1ffff, 3786 .hfb_filter_cnt = 48, 3787 .hfb_filter_size = 128, 3788 .qtag_mask = 0x3F, 3789 .tbuf_offset = 0x0600, 3790 .hfb_offset = 0x8000, 3791 .hfb_reg_offset = 0xfc00, 3792 .rdma_offset = 0x10000, 3793 .tdma_offset = 0x11000, 3794 .words_per_bd = 2, 3795 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3796 GENET_HAS_MOCA_LINK_DET, 3797 }, 3798 [GENET_V4] = { 3799 .tx_queues = 4, 3800 .tx_bds_per_q = 32, 3801 .rx_queues = 0, 3802 .rx_bds_per_q = 0, 3803 .bp_in_en_shift = 17, 3804 .bp_in_mask = 0x1ffff, 3805 .hfb_filter_cnt = 48, 3806 .hfb_filter_size = 128, 3807 .qtag_mask = 0x3F, 3808 .tbuf_offset = 0x0600, 3809 .hfb_offset = 0x8000, 3810 .hfb_reg_offset = 0xfc00, 3811 .rdma_offset = 0x2000, 3812 .tdma_offset = 0x4000, 3813 .words_per_bd = 3, 3814 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3815 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3816 }, 3817 [GENET_V5] = { 3818 .tx_queues = 4, 3819 .tx_bds_per_q = 32, 3820 .rx_queues = 0, 3821 .rx_bds_per_q = 0, 3822 .bp_in_en_shift = 17, 3823 .bp_in_mask = 0x1ffff, 3824 .hfb_filter_cnt = 48, 3825 .hfb_filter_size = 128, 3826 .qtag_mask = 0x3F, 3827 .tbuf_offset = 0x0600, 3828 .hfb_offset = 0x8000, 3829 .hfb_reg_offset = 0xfc00, 3830 .rdma_offset = 0x2000, 3831 .tdma_offset = 0x4000, 3832 .words_per_bd = 3, 3833 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3834 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3835 }, 3836 }; 3837 3838 /* Infer hardware parameters from the detected GENET version */ 3839 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3840 { 3841 struct bcmgenet_hw_params *params; 3842 u32 reg; 3843 u8 major; 3844 u16 gphy_rev; 3845 3846 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3847 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3848 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3849 } else if (GENET_IS_V3(priv)) { 3850 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3851 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3852 } else if (GENET_IS_V2(priv)) { 3853 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3854 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3855 } else if (GENET_IS_V1(priv)) { 3856 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3857 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3858 } 3859 3860 /* enum genet_version starts at 1 */ 3861 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3862 params = priv->hw_params; 3863 3864 /* Read GENET HW version */ 3865 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3866 major = (reg >> 24 & 0x0f); 3867 if (major == 6) 3868 major = 5; 3869 else if (major == 5) 3870 major = 4; 3871 else if (major == 0) 3872 major = 1; 3873 if (major != priv->version) { 3874 dev_err(&priv->pdev->dev, 3875 "GENET version mismatch, got: %d, configured for: %d\n", 3876 major, priv->version); 3877 } 3878 3879 /* Print the GENET core version */ 3880 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3881 major, (reg >> 16) & 0x0f, reg & 0xffff); 3882 3883 /* Store the integrated PHY revision for the MDIO probing function 3884 * to pass this information to the PHY driver. The PHY driver expects 3885 * to find the PHY major revision in bits 15:8 while the GENET register 3886 * stores that information in bits 7:0, account for that. 3887 * 3888 * On newer chips, starting with PHY revision G0, a new scheme is 3889 * deployed similar to the Starfighter 2 switch with GPHY major 3890 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3891 * is reserved as well as special value 0x01ff, we have a small 3892 * heuristic to check for the new GPHY revision and re-arrange things 3893 * so the GPHY driver is happy. 3894 */ 3895 gphy_rev = reg & 0xffff; 3896 3897 if (GENET_IS_V5(priv)) { 3898 /* The EPHY revision should come from the MDIO registers of 3899 * the PHY not from GENET. 3900 */ 3901 if (gphy_rev != 0) { 3902 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3903 gphy_rev); 3904 } 3905 /* This is reserved so should require special treatment */ 3906 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3907 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3908 return; 3909 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3910 } else if ((gphy_rev & 0xf0) != 0) { 3911 priv->gphy_rev = gphy_rev << 8; 3912 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3913 } else if ((gphy_rev & 0xff00) != 0) { 3914 priv->gphy_rev = gphy_rev; 3915 } 3916 3917 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3918 if (!(params->flags & GENET_HAS_40BITS)) 3919 pr_warn("GENET does not support 40-bits PA\n"); 3920 #endif 3921 3922 pr_debug("Configuration for version: %d\n" 3923 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3924 "BP << en: %2d, BP msk: 0x%05x\n" 3925 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3926 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3927 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3928 "Words/BD: %d\n", 3929 priv->version, 3930 params->tx_queues, params->tx_bds_per_q, 3931 params->rx_queues, params->rx_bds_per_q, 3932 params->bp_in_en_shift, params->bp_in_mask, 3933 params->hfb_filter_cnt, params->qtag_mask, 3934 params->tbuf_offset, params->hfb_offset, 3935 params->hfb_reg_offset, 3936 params->rdma_offset, params->tdma_offset, 3937 params->words_per_bd); 3938 } 3939 3940 struct bcmgenet_plat_data { 3941 enum bcmgenet_version version; 3942 u32 dma_max_burst_length; 3943 bool ephy_16nm; 3944 }; 3945 3946 static const struct bcmgenet_plat_data v1_plat_data = { 3947 .version = GENET_V1, 3948 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3949 }; 3950 3951 static const struct bcmgenet_plat_data v2_plat_data = { 3952 .version = GENET_V2, 3953 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3954 }; 3955 3956 static const struct bcmgenet_plat_data v3_plat_data = { 3957 .version = GENET_V3, 3958 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3959 }; 3960 3961 static const struct bcmgenet_plat_data v4_plat_data = { 3962 .version = GENET_V4, 3963 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3964 }; 3965 3966 static const struct bcmgenet_plat_data v5_plat_data = { 3967 .version = GENET_V5, 3968 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3969 }; 3970 3971 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3972 .version = GENET_V5, 3973 .dma_max_burst_length = 0x08, 3974 }; 3975 3976 static const struct bcmgenet_plat_data bcm7712_plat_data = { 3977 .version = GENET_V5, 3978 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3979 .ephy_16nm = true, 3980 }; 3981 3982 static const struct of_device_id bcmgenet_match[] = { 3983 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3984 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3985 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3986 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3987 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3988 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3989 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data }, 3990 { }, 3991 }; 3992 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3993 3994 static int bcmgenet_probe(struct platform_device *pdev) 3995 { 3996 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3997 const struct bcmgenet_plat_data *pdata; 3998 struct bcmgenet_priv *priv; 3999 struct net_device *dev; 4000 unsigned int i; 4001 int err = -EIO; 4002 4003 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 4004 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 4005 GENET_MAX_MQ_CNT + 1); 4006 if (!dev) { 4007 dev_err(&pdev->dev, "can't allocate net device\n"); 4008 return -ENOMEM; 4009 } 4010 4011 priv = netdev_priv(dev); 4012 priv->irq0 = platform_get_irq(pdev, 0); 4013 if (priv->irq0 < 0) { 4014 err = priv->irq0; 4015 goto err; 4016 } 4017 priv->irq1 = platform_get_irq(pdev, 1); 4018 if (priv->irq1 < 0) { 4019 err = priv->irq1; 4020 goto err; 4021 } 4022 priv->wol_irq = platform_get_irq_optional(pdev, 2); 4023 if (priv->wol_irq == -EPROBE_DEFER) { 4024 err = priv->wol_irq; 4025 goto err; 4026 } 4027 4028 priv->base = devm_platform_ioremap_resource(pdev, 0); 4029 if (IS_ERR(priv->base)) { 4030 err = PTR_ERR(priv->base); 4031 goto err; 4032 } 4033 4034 spin_lock_init(&priv->lock); 4035 4036 /* Set default pause parameters */ 4037 priv->autoneg_pause = 1; 4038 priv->tx_pause = 1; 4039 priv->rx_pause = 1; 4040 4041 SET_NETDEV_DEV(dev, &pdev->dev); 4042 dev_set_drvdata(&pdev->dev, dev); 4043 dev->watchdog_timeo = 2 * HZ; 4044 dev->ethtool_ops = &bcmgenet_ethtool_ops; 4045 dev->netdev_ops = &bcmgenet_netdev_ops; 4046 4047 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 4048 4049 /* Set default features */ 4050 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 4051 NETIF_F_RXCSUM; 4052 dev->hw_features |= dev->features; 4053 dev->vlan_features |= dev->features; 4054 4055 /* Request the WOL interrupt and advertise suspend if available */ 4056 priv->wol_irq_disabled = true; 4057 if (priv->wol_irq > 0) { 4058 err = devm_request_irq(&pdev->dev, priv->wol_irq, 4059 bcmgenet_wol_isr, 0, dev->name, priv); 4060 if (!err) 4061 device_set_wakeup_capable(&pdev->dev, 1); 4062 } 4063 4064 /* Set the needed headroom to account for any possible 4065 * features enabling/disabling at runtime 4066 */ 4067 dev->needed_headroom += 64; 4068 4069 priv->dev = dev; 4070 priv->pdev = pdev; 4071 4072 pdata = device_get_match_data(&pdev->dev); 4073 if (pdata) { 4074 priv->version = pdata->version; 4075 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4076 priv->ephy_16nm = pdata->ephy_16nm; 4077 } else { 4078 priv->version = pd->genet_version; 4079 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 4080 } 4081 4082 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4083 if (IS_ERR(priv->clk)) { 4084 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4085 err = PTR_ERR(priv->clk); 4086 goto err; 4087 } 4088 4089 err = clk_prepare_enable(priv->clk); 4090 if (err) 4091 goto err; 4092 4093 bcmgenet_set_hw_params(priv); 4094 4095 err = -EIO; 4096 if (priv->hw_params->flags & GENET_HAS_40BITS) 4097 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4098 if (err) 4099 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4100 if (err) 4101 goto err_clk_disable; 4102 4103 /* Mii wait queue */ 4104 init_waitqueue_head(&priv->wq); 4105 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4106 priv->rx_buf_len = RX_BUF_LENGTH; 4107 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4108 4109 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4110 if (IS_ERR(priv->clk_wol)) { 4111 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4112 err = PTR_ERR(priv->clk_wol); 4113 goto err_clk_disable; 4114 } 4115 4116 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4117 if (IS_ERR(priv->clk_eee)) { 4118 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4119 err = PTR_ERR(priv->clk_eee); 4120 goto err_clk_disable; 4121 } 4122 4123 /* If this is an internal GPHY, power it on now, before UniMAC is 4124 * brought out of reset as absolutely no UniMAC activity is allowed 4125 */ 4126 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4127 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4128 4129 if (pd && !IS_ERR_OR_NULL(pd->mac_address)) 4130 eth_hw_addr_set(dev, pd->mac_address); 4131 else 4132 if (device_get_ethdev_address(&pdev->dev, dev)) 4133 if (has_acpi_companion(&pdev->dev)) { 4134 u8 addr[ETH_ALEN]; 4135 4136 bcmgenet_get_hw_addr(priv, addr); 4137 eth_hw_addr_set(dev, addr); 4138 } 4139 4140 if (!is_valid_ether_addr(dev->dev_addr)) { 4141 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4142 eth_hw_addr_random(dev); 4143 } 4144 4145 reset_umac(priv); 4146 4147 err = bcmgenet_mii_init(dev); 4148 if (err) 4149 goto err_clk_disable; 4150 4151 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 4152 * just the ring 16 descriptor based TX 4153 */ 4154 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4155 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4156 4157 /* Set default coalescing parameters */ 4158 for (i = 0; i < priv->hw_params->rx_queues; i++) 4159 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4160 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 4161 4162 /* libphy will determine the link state */ 4163 netif_carrier_off(dev); 4164 4165 /* Turn off the main clock, WOL clock is handled separately */ 4166 clk_disable_unprepare(priv->clk); 4167 4168 err = register_netdev(dev); 4169 if (err) { 4170 bcmgenet_mii_exit(dev); 4171 goto err; 4172 } 4173 4174 return err; 4175 4176 err_clk_disable: 4177 clk_disable_unprepare(priv->clk); 4178 err: 4179 free_netdev(dev); 4180 return err; 4181 } 4182 4183 static int bcmgenet_remove(struct platform_device *pdev) 4184 { 4185 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4186 4187 dev_set_drvdata(&pdev->dev, NULL); 4188 unregister_netdev(priv->dev); 4189 bcmgenet_mii_exit(priv->dev); 4190 free_netdev(priv->dev); 4191 4192 return 0; 4193 } 4194 4195 static void bcmgenet_shutdown(struct platform_device *pdev) 4196 { 4197 bcmgenet_remove(pdev); 4198 } 4199 4200 #ifdef CONFIG_PM_SLEEP 4201 static int bcmgenet_resume_noirq(struct device *d) 4202 { 4203 struct net_device *dev = dev_get_drvdata(d); 4204 struct bcmgenet_priv *priv = netdev_priv(dev); 4205 int ret; 4206 u32 reg; 4207 4208 if (!netif_running(dev)) 4209 return 0; 4210 4211 /* Turn on the clock */ 4212 ret = clk_prepare_enable(priv->clk); 4213 if (ret) 4214 return ret; 4215 4216 if (device_may_wakeup(d) && priv->wolopts) { 4217 /* Account for Wake-on-LAN events and clear those events 4218 * (Some devices need more time between enabling the clocks 4219 * and the interrupt register reflecting the wake event so 4220 * read the register twice) 4221 */ 4222 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4223 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4224 if (reg & UMAC_IRQ_WAKE_EVENT) 4225 pm_wakeup_event(&priv->pdev->dev, 0); 4226 } 4227 4228 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); 4229 4230 return 0; 4231 } 4232 4233 static int bcmgenet_resume(struct device *d) 4234 { 4235 struct net_device *dev = dev_get_drvdata(d); 4236 struct bcmgenet_priv *priv = netdev_priv(dev); 4237 struct bcmgenet_rxnfc_rule *rule; 4238 unsigned long dma_ctrl; 4239 int ret; 4240 4241 if (!netif_running(dev)) 4242 return 0; 4243 4244 /* From WOL-enabled suspend, switch to regular clock */ 4245 if (device_may_wakeup(d) && priv->wolopts) 4246 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 4247 4248 /* If this is an internal GPHY, power it back on now, before UniMAC is 4249 * brought out of reset as absolutely no UniMAC activity is allowed 4250 */ 4251 if (priv->internal_phy) 4252 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4253 4254 bcmgenet_umac_reset(priv); 4255 4256 init_umac(priv); 4257 4258 phy_init_hw(dev->phydev); 4259 4260 /* Speed settings must be restored */ 4261 genphy_config_aneg(dev->phydev); 4262 bcmgenet_mii_config(priv->dev, false); 4263 4264 /* Restore enabled features */ 4265 bcmgenet_set_features(dev, dev->features); 4266 4267 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4268 4269 /* Restore hardware filters */ 4270 bcmgenet_hfb_clear(priv); 4271 list_for_each_entry(rule, &priv->rxnfc_list, list) 4272 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4273 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4274 4275 /* Disable RX/TX DMA and flush TX queues */ 4276 dma_ctrl = bcmgenet_dma_disable(priv); 4277 4278 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4279 ret = bcmgenet_init_dma(priv); 4280 if (ret) { 4281 netdev_err(dev, "failed to initialize DMA\n"); 4282 goto out_clk_disable; 4283 } 4284 4285 /* Always enable ring 16 - descriptor ring */ 4286 bcmgenet_enable_dma(priv, dma_ctrl); 4287 4288 if (!device_may_wakeup(d)) 4289 phy_resume(dev->phydev); 4290 4291 if (priv->eee.eee_enabled) 4292 bcmgenet_eee_enable_set(dev, true); 4293 4294 bcmgenet_netif_start(dev); 4295 4296 netif_device_attach(dev); 4297 4298 return 0; 4299 4300 out_clk_disable: 4301 if (priv->internal_phy) 4302 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4303 clk_disable_unprepare(priv->clk); 4304 return ret; 4305 } 4306 4307 static int bcmgenet_suspend(struct device *d) 4308 { 4309 struct net_device *dev = dev_get_drvdata(d); 4310 struct bcmgenet_priv *priv = netdev_priv(dev); 4311 4312 if (!netif_running(dev)) 4313 return 0; 4314 4315 netif_device_detach(dev); 4316 4317 bcmgenet_netif_stop(dev); 4318 4319 if (!device_may_wakeup(d)) 4320 phy_suspend(dev->phydev); 4321 4322 /* Disable filtering */ 4323 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 4324 4325 return 0; 4326 } 4327 4328 static int bcmgenet_suspend_noirq(struct device *d) 4329 { 4330 struct net_device *dev = dev_get_drvdata(d); 4331 struct bcmgenet_priv *priv = netdev_priv(dev); 4332 int ret = 0; 4333 4334 if (!netif_running(dev)) 4335 return 0; 4336 4337 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4338 if (device_may_wakeup(d) && priv->wolopts) 4339 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4340 else if (priv->internal_phy) 4341 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4342 4343 /* Let the framework handle resumption and leave the clocks on */ 4344 if (ret) 4345 return ret; 4346 4347 /* Turn off the clocks */ 4348 clk_disable_unprepare(priv->clk); 4349 4350 return 0; 4351 } 4352 #else 4353 #define bcmgenet_suspend NULL 4354 #define bcmgenet_suspend_noirq NULL 4355 #define bcmgenet_resume NULL 4356 #define bcmgenet_resume_noirq NULL 4357 #endif /* CONFIG_PM_SLEEP */ 4358 4359 static const struct dev_pm_ops bcmgenet_pm_ops = { 4360 .suspend = bcmgenet_suspend, 4361 .suspend_noirq = bcmgenet_suspend_noirq, 4362 .resume = bcmgenet_resume, 4363 .resume_noirq = bcmgenet_resume_noirq, 4364 }; 4365 4366 static const struct acpi_device_id genet_acpi_match[] = { 4367 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4368 { }, 4369 }; 4370 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4371 4372 static struct platform_driver bcmgenet_driver = { 4373 .probe = bcmgenet_probe, 4374 .remove = bcmgenet_remove, 4375 .shutdown = bcmgenet_shutdown, 4376 .driver = { 4377 .name = "bcmgenet", 4378 .of_match_table = bcmgenet_match, 4379 .pm = &bcmgenet_pm_ops, 4380 .acpi_match_table = genet_acpi_match, 4381 }, 4382 }; 4383 module_platform_driver(bcmgenet_driver); 4384 4385 MODULE_AUTHOR("Broadcom Corporation"); 4386 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4387 MODULE_ALIAS("platform:bcmgenet"); 4388 MODULE_LICENSE("GPL"); 4389 MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4390