1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 17 #include <linux/pci.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/types.h> 21 #include <linux/pci_regs.h> 22 23 /* compilation time flags */ 24 25 /* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27 /* #define BNX2X_STOP_ON_ERROR */ 28 29 #define DRV_MODULE_VERSION "1.78.02-0" 30 #define DRV_MODULE_RELDATE "2013/01/14" 31 #define BNX2X_BC_VER 0x040200 32 33 #if defined(CONFIG_DCB) 34 #define BCM_DCBNL 35 #endif 36 37 38 #include "bnx2x_hsi.h" 39 40 #include "../cnic_if.h" 41 42 43 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 44 45 #include <linux/mdio.h> 46 47 #include "bnx2x_reg.h" 48 #include "bnx2x_fw_defs.h" 49 #include "bnx2x_mfw_req.h" 50 #include "bnx2x_link.h" 51 #include "bnx2x_sp.h" 52 #include "bnx2x_dcb.h" 53 #include "bnx2x_stats.h" 54 #include "bnx2x_vfpf.h" 55 56 enum bnx2x_int_mode { 57 BNX2X_INT_MODE_MSIX, 58 BNX2X_INT_MODE_INTX, 59 BNX2X_INT_MODE_MSI 60 }; 61 62 /* error/debug prints */ 63 64 #define DRV_MODULE_NAME "bnx2x" 65 66 /* for messages that are currently off */ 67 #define BNX2X_MSG_OFF 0x0 68 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 69 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 70 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 71 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 72 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 73 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 74 #define BNX2X_MSG_IOV 0x0800000 75 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 76 #define BNX2X_MSG_ETHTOOL 0x4000000 77 #define BNX2X_MSG_DCB 0x8000000 78 79 /* regular debug print */ 80 #define DP(__mask, fmt, ...) \ 81 do { \ 82 if (unlikely(bp->msg_enable & (__mask))) \ 83 pr_notice("[%s:%d(%s)]" fmt, \ 84 __func__, __LINE__, \ 85 bp->dev ? (bp->dev->name) : "?", \ 86 ##__VA_ARGS__); \ 87 } while (0) 88 89 #define DP_CONT(__mask, fmt, ...) \ 90 do { \ 91 if (unlikely(bp->msg_enable & (__mask))) \ 92 pr_cont(fmt, ##__VA_ARGS__); \ 93 } while (0) 94 95 /* errors debug print */ 96 #define BNX2X_DBG_ERR(fmt, ...) \ 97 do { \ 98 if (unlikely(netif_msg_probe(bp))) \ 99 pr_err("[%s:%d(%s)]" fmt, \ 100 __func__, __LINE__, \ 101 bp->dev ? (bp->dev->name) : "?", \ 102 ##__VA_ARGS__); \ 103 } while (0) 104 105 /* for errors (never masked) */ 106 #define BNX2X_ERR(fmt, ...) \ 107 do { \ 108 pr_err("[%s:%d(%s)]" fmt, \ 109 __func__, __LINE__, \ 110 bp->dev ? (bp->dev->name) : "?", \ 111 ##__VA_ARGS__); \ 112 } while (0) 113 114 #define BNX2X_ERROR(fmt, ...) \ 115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 116 117 118 /* before we have a dev->name use dev_info() */ 119 #define BNX2X_DEV_INFO(fmt, ...) \ 120 do { \ 121 if (unlikely(netif_msg_probe(bp))) \ 122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 123 } while (0) 124 125 /* Error handling */ 126 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 127 #ifdef BNX2X_STOP_ON_ERROR 128 #define bnx2x_panic() \ 129 do { \ 130 bp->panic = 1; \ 131 BNX2X_ERR("driver assert\n"); \ 132 bnx2x_panic_dump(bp, true); \ 133 } while (0) 134 #else 135 #define bnx2x_panic() \ 136 do { \ 137 bp->panic = 1; \ 138 BNX2X_ERR("driver assert\n"); \ 139 bnx2x_panic_dump(bp, false); \ 140 } while (0) 141 #endif 142 143 #define bnx2x_mc_addr(ha) ((ha)->addr) 144 #define bnx2x_uc_addr(ha) ((ha)->addr) 145 146 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 147 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 148 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 149 150 151 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 152 153 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 154 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 155 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 156 157 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 158 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 159 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 160 161 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 162 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 163 164 #define REG_RD_DMAE(bp, offset, valp, len32) \ 165 do { \ 166 bnx2x_read_dmae(bp, offset, len32);\ 167 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 168 } while (0) 169 170 #define REG_WR_DMAE(bp, offset, valp, len32) \ 171 do { \ 172 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 173 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 174 offset, len32); \ 175 } while (0) 176 177 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 178 REG_WR_DMAE(bp, offset, valp, len32) 179 180 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 181 do { \ 182 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 183 bnx2x_write_big_buf_wb(bp, addr, len32); \ 184 } while (0) 185 186 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 187 offsetof(struct shmem_region, field)) 188 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 189 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 190 191 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 192 offsetof(struct shmem2_region, field)) 193 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 194 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 195 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 196 offsetof(struct mf_cfg, field)) 197 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 198 offsetof(struct mf2_cfg, field)) 199 200 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 201 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 202 MF_CFG_ADDR(bp, field), (val)) 203 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 204 205 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 206 (SHMEM2_RD((bp), size) > \ 207 offsetof(struct shmem2_region, field))) 208 209 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 210 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 211 212 /* SP SB indices */ 213 214 /* General SP events - stats query, cfc delete, etc */ 215 #define HC_SP_INDEX_ETH_DEF_CONS 3 216 217 /* EQ completions */ 218 #define HC_SP_INDEX_EQ_CONS 7 219 220 /* FCoE L2 connection completions */ 221 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 222 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 223 /* iSCSI L2 */ 224 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 225 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 226 227 /* Special clients parameters */ 228 229 /* SB indices */ 230 /* FCoE L2 */ 231 #define BNX2X_FCOE_L2_RX_INDEX \ 232 (&bp->def_status_blk->sp_sb.\ 233 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 234 235 #define BNX2X_FCOE_L2_TX_INDEX \ 236 (&bp->def_status_blk->sp_sb.\ 237 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 238 239 /** 240 * CIDs and CLIDs: 241 * CLIDs below is a CLID for func 0, then the CLID for other 242 * functions will be calculated by the formula: 243 * 244 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 245 * 246 */ 247 enum { 248 BNX2X_ISCSI_ETH_CL_ID_IDX, 249 BNX2X_FCOE_ETH_CL_ID_IDX, 250 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 251 }; 252 253 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 254 (bp)->max_cos) 255 /* iSCSI L2 */ 256 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 257 /* FCoE L2 */ 258 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 259 260 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 261 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 262 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 263 #define FCOE_INIT(bp) ((bp)->fcoe_init) 264 265 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 266 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 267 268 #define SM_RX_ID 0 269 #define SM_TX_ID 1 270 271 /* defines for multiple tx priority indices */ 272 #define FIRST_TX_ONLY_COS_INDEX 1 273 #define FIRST_TX_COS_INDEX 0 274 275 /* rules for calculating the cids of tx-only connections */ 276 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 277 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 278 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 279 280 /* fp index inside class of service range */ 281 #define FP_COS_TO_TXQ(fp, cos, bp) \ 282 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 283 284 /* Indexes for transmission queues array: 285 * txdata for RSS i CoS j is at location i + (j * num of RSS) 286 * txdata for FCoE (if exist) is at location max cos * num of RSS 287 * txdata for FWD (if exist) is one location after FCoE 288 * txdata for OOO (if exist) is one location after FWD 289 */ 290 enum { 291 FCOE_TXQ_IDX_OFFSET, 292 FWD_TXQ_IDX_OFFSET, 293 OOO_TXQ_IDX_OFFSET, 294 }; 295 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 296 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 297 298 /* fast path */ 299 /* 300 * This driver uses new build_skb() API : 301 * RX ring buffer contains pointer to kmalloc() data only, 302 * skb are built only after Hardware filled the frame. 303 */ 304 struct sw_rx_bd { 305 u8 *data; 306 DEFINE_DMA_UNMAP_ADDR(mapping); 307 }; 308 309 struct sw_tx_bd { 310 struct sk_buff *skb; 311 u16 first_bd; 312 u8 flags; 313 /* Set on the first BD descriptor when there is a split BD */ 314 #define BNX2X_TSO_SPLIT_BD (1<<0) 315 }; 316 317 struct sw_rx_page { 318 struct page *page; 319 DEFINE_DMA_UNMAP_ADDR(mapping); 320 }; 321 322 union db_prod { 323 struct doorbell_set_prod data; 324 u32 raw; 325 }; 326 327 /* dropless fc FW/HW related params */ 328 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 329 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 330 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 331 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 332 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 333 #define FW_PREFETCH_CNT 16 334 #define DROPLESS_FC_HEADROOM 100 335 336 /* MC hsi */ 337 #define BCM_PAGE_SHIFT 12 338 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 339 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 340 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 341 342 #define PAGES_PER_SGE_SHIFT 0 343 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 344 #define SGE_PAGE_SIZE PAGE_SIZE 345 #define SGE_PAGE_SHIFT PAGE_SHIFT 346 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 347 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 348 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 349 SGE_PAGES), 0xffff) 350 351 /* SGE ring related macros */ 352 #define NUM_RX_SGE_PAGES 2 353 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 354 #define NEXT_PAGE_SGE_DESC_CNT 2 355 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 356 /* RX_SGE_CNT is promised to be a power of 2 */ 357 #define RX_SGE_MASK (RX_SGE_CNT - 1) 358 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 359 #define MAX_RX_SGE (NUM_RX_SGE - 1) 360 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 361 (MAX_RX_SGE_CNT - 1)) ? \ 362 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 363 (x) + 1) 364 #define RX_SGE(x) ((x) & MAX_RX_SGE) 365 366 /* 367 * Number of required SGEs is the sum of two: 368 * 1. Number of possible opened aggregations (next packet for 369 * these aggregations will probably consume SGE immidiatelly) 370 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 371 * after placement on BD for new TPA aggregation) 372 * 373 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 374 */ 375 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 376 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 377 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 378 MAX_RX_SGE_CNT) 379 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 380 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 381 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 382 383 /* Manipulate a bit vector defined as an array of u64 */ 384 385 /* Number of bits in one sge_mask array element */ 386 #define BIT_VEC64_ELEM_SZ 64 387 #define BIT_VEC64_ELEM_SHIFT 6 388 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 389 390 391 #define __BIT_VEC64_SET_BIT(el, bit) \ 392 do { \ 393 el = ((el) | ((u64)0x1 << (bit))); \ 394 } while (0) 395 396 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 397 do { \ 398 el = ((el) & (~((u64)0x1 << (bit)))); \ 399 } while (0) 400 401 402 #define BIT_VEC64_SET_BIT(vec64, idx) \ 403 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 404 (idx) & BIT_VEC64_ELEM_MASK) 405 406 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 407 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 408 (idx) & BIT_VEC64_ELEM_MASK) 409 410 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 411 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 412 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 413 414 /* Creates a bitmask of all ones in less significant bits. 415 idx - index of the most significant bit in the created mask */ 416 #define BIT_VEC64_ONES_MASK(idx) \ 417 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 418 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 419 420 /*******************************************************/ 421 422 423 424 /* Number of u64 elements in SGE mask array */ 425 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 426 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 427 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 428 429 union host_hc_status_block { 430 /* pointer to fp status block e1x */ 431 struct host_hc_status_block_e1x *e1x_sb; 432 /* pointer to fp status block e2 */ 433 struct host_hc_status_block_e2 *e2_sb; 434 }; 435 436 struct bnx2x_agg_info { 437 /* 438 * First aggregation buffer is a data buffer, the following - are pages. 439 * We will preallocate the data buffer for each aggregation when 440 * we open the interface and will replace the BD at the consumer 441 * with this one when we receive the TPA_START CQE in order to 442 * keep the Rx BD ring consistent. 443 */ 444 struct sw_rx_bd first_buf; 445 u8 tpa_state; 446 #define BNX2X_TPA_START 1 447 #define BNX2X_TPA_STOP 2 448 #define BNX2X_TPA_ERROR 3 449 u8 placement_offset; 450 u16 parsing_flags; 451 u16 vlan_tag; 452 u16 len_on_bd; 453 u32 rxhash; 454 bool l4_rxhash; 455 u16 gro_size; 456 u16 full_page; 457 }; 458 459 #define Q_STATS_OFFSET32(stat_name) \ 460 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 461 462 struct bnx2x_fp_txdata { 463 464 struct sw_tx_bd *tx_buf_ring; 465 466 union eth_tx_bd_types *tx_desc_ring; 467 dma_addr_t tx_desc_mapping; 468 469 u32 cid; 470 471 union db_prod tx_db; 472 473 u16 tx_pkt_prod; 474 u16 tx_pkt_cons; 475 u16 tx_bd_prod; 476 u16 tx_bd_cons; 477 478 unsigned long tx_pkt; 479 480 __le16 *tx_cons_sb; 481 482 int txq_index; 483 struct bnx2x_fastpath *parent_fp; 484 int tx_ring_size; 485 }; 486 487 enum bnx2x_tpa_mode_t { 488 TPA_MODE_LRO, 489 TPA_MODE_GRO 490 }; 491 492 struct bnx2x_fastpath { 493 struct bnx2x *bp; /* parent */ 494 495 struct napi_struct napi; 496 union host_hc_status_block status_blk; 497 /* chip independed shortcuts into sb structure */ 498 __le16 *sb_index_values; 499 __le16 *sb_running_index; 500 /* chip independed shortcut into rx_prods_offset memory */ 501 u32 ustorm_rx_prods_offset; 502 503 u32 rx_buf_size; 504 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 505 dma_addr_t status_blk_mapping; 506 507 enum bnx2x_tpa_mode_t mode; 508 509 u8 max_cos; /* actual number of active tx coses */ 510 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 511 512 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 513 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 514 515 struct eth_rx_bd *rx_desc_ring; 516 dma_addr_t rx_desc_mapping; 517 518 union eth_rx_cqe *rx_comp_ring; 519 dma_addr_t rx_comp_mapping; 520 521 /* SGE ring */ 522 struct eth_rx_sge *rx_sge_ring; 523 dma_addr_t rx_sge_mapping; 524 525 u64 sge_mask[RX_SGE_MASK_LEN]; 526 527 u32 cid; 528 529 __le16 fp_hc_idx; 530 531 u8 index; /* number in fp array */ 532 u8 rx_queue; /* index for skb_record */ 533 u8 cl_id; /* eth client id */ 534 u8 cl_qzone_id; 535 u8 fw_sb_id; /* status block number in FW */ 536 u8 igu_sb_id; /* status block number in HW */ 537 538 u16 rx_bd_prod; 539 u16 rx_bd_cons; 540 u16 rx_comp_prod; 541 u16 rx_comp_cons; 542 u16 rx_sge_prod; 543 /* The last maximal completed SGE */ 544 u16 last_max_sge; 545 __le16 *rx_cons_sb; 546 unsigned long rx_pkt, 547 rx_calls; 548 549 /* TPA related */ 550 struct bnx2x_agg_info *tpa_info; 551 u8 disable_tpa; 552 #ifdef BNX2X_STOP_ON_ERROR 553 u64 tpa_queue_used; 554 #endif 555 /* The size is calculated using the following: 556 sizeof name field from netdev structure + 557 4 ('-Xx-' string) + 558 4 (for the digits and to make it DWORD aligned) */ 559 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 560 char name[FP_NAME_SIZE]; 561 }; 562 563 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 564 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 565 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 566 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 567 568 /* Use 2500 as a mini-jumbo MTU for FCoE */ 569 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 570 571 #define FCOE_IDX_OFFSET 0 572 573 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 574 FCOE_IDX_OFFSET) 575 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 576 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 577 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 578 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 579 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 580 txdata_ptr[FIRST_TX_COS_INDEX] \ 581 ->var) 582 583 584 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 585 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 586 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 587 588 589 /* MC hsi */ 590 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 591 #define RX_COPY_THRESH 92 592 593 #define NUM_TX_RINGS 16 594 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 595 #define NEXT_PAGE_TX_DESC_CNT 1 596 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 597 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 598 #define MAX_TX_BD (NUM_TX_BD - 1) 599 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 600 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 601 (MAX_TX_DESC_CNT - 1)) ? \ 602 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 603 (x) + 1) 604 #define TX_BD(x) ((x) & MAX_TX_BD) 605 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 606 607 /* number of NEXT_PAGE descriptors may be required during placement */ 608 #define NEXT_CNT_PER_TX_PKT(bds) \ 609 (((bds) + MAX_TX_DESC_CNT - 1) / \ 610 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 611 /* max BDs per tx packet w/o next_pages: 612 * START_BD - describes packed 613 * START_BD(splitted) - includes unpaged data segment for GSO 614 * PARSING_BD - for TSO and CSUM data 615 * PARSING_BD2 - for encapsulation data 616 * Frag BDs - decribes pages for frags 617 */ 618 #define BDS_PER_TX_PKT 4 619 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 620 /* max BDs per tx packet including next pages */ 621 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 622 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 623 624 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 625 #define NUM_RX_RINGS 8 626 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 627 #define NEXT_PAGE_RX_DESC_CNT 2 628 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 629 #define RX_DESC_MASK (RX_DESC_CNT - 1) 630 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 631 #define MAX_RX_BD (NUM_RX_BD - 1) 632 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 633 634 /* dropless fc calculations for BDs 635 * 636 * Number of BDs should as number of buffers in BRB: 637 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 638 * "next" elements on each page 639 */ 640 #define NUM_BD_REQ BRB_SIZE(bp) 641 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 642 MAX_RX_DESC_CNT) 643 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 644 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 645 FW_DROP_LEVEL(bp)) 646 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 647 648 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 649 650 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 651 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 652 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 653 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 654 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 655 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 656 MIN_RX_AVAIL)) 657 658 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 659 (MAX_RX_DESC_CNT - 1)) ? \ 660 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 661 (x) + 1) 662 #define RX_BD(x) ((x) & MAX_RX_BD) 663 664 /* 665 * As long as CQE is X times bigger than BD entry we have to allocate X times 666 * more pages for CQ ring in order to keep it balanced with BD ring 667 */ 668 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 669 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 670 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 671 #define NEXT_PAGE_RCQ_DESC_CNT 1 672 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 673 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 674 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 675 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 676 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 677 (MAX_RCQ_DESC_CNT - 1)) ? \ 678 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 679 (x) + 1) 680 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 681 682 /* dropless fc calculations for RCQs 683 * 684 * Number of RCQs should be as number of buffers in BRB: 685 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 686 * "next" elements on each page 687 */ 688 #define NUM_RCQ_REQ BRB_SIZE(bp) 689 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 690 MAX_RCQ_DESC_CNT) 691 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 692 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 693 FW_DROP_LEVEL(bp)) 694 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 695 696 697 /* This is needed for determining of last_max */ 698 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 699 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 700 701 702 #define BNX2X_SWCID_SHIFT 17 703 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 704 705 /* used on a CID received from the HW */ 706 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 707 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 708 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 709 710 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 711 le32_to_cpu((bd)->addr_lo)) 712 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 713 714 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 715 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 716 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 717 #error "Min DB doorbell stride is 8" 718 #endif 719 #define DPM_TRIGER_TYPE 0x40 720 #define DOORBELL(bp, cid, val) \ 721 do { \ 722 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 723 DPM_TRIGER_TYPE); \ 724 } while (0) 725 726 727 /* TX CSUM helpers */ 728 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 729 skb->csum_offset) 730 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 731 skb->csum_offset)) 732 733 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 734 735 #define XMIT_PLAIN 0 736 #define XMIT_CSUM_V4 (1 << 0) 737 #define XMIT_CSUM_V6 (1 << 1) 738 #define XMIT_CSUM_TCP (1 << 2) 739 #define XMIT_GSO_V4 (1 << 3) 740 #define XMIT_GSO_V6 (1 << 4) 741 #define XMIT_CSUM_ENC_V4 (1 << 5) 742 #define XMIT_CSUM_ENC_V6 (1 << 6) 743 #define XMIT_GSO_ENC_V4 (1 << 7) 744 #define XMIT_GSO_ENC_V6 (1 << 8) 745 746 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 747 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 748 749 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 750 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 751 752 /* stuff added to make the code fit 80Col */ 753 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 754 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 755 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 756 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 757 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 758 759 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 760 761 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 762 (((le16_to_cpu(flags) & \ 763 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 764 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 765 == PRS_FLAG_OVERETH_IPV4) 766 #define BNX2X_RX_SUM_FIX(cqe) \ 767 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 768 769 770 #define FP_USB_FUNC_OFF \ 771 offsetof(struct cstorm_status_block_u, func) 772 #define FP_CSB_FUNC_OFF \ 773 offsetof(struct cstorm_status_block_c, func) 774 775 #define HC_INDEX_ETH_RX_CQ_CONS 1 776 777 #define HC_INDEX_OOO_TX_CQ_CONS 4 778 779 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 780 781 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 782 783 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 784 785 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 786 787 #define BNX2X_RX_SB_INDEX \ 788 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 789 790 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 791 792 #define BNX2X_TX_SB_INDEX_COS0 \ 793 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 794 795 /* end of fast path */ 796 797 /* common */ 798 799 struct bnx2x_common { 800 801 u32 chip_id; 802 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 803 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 804 805 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 806 #define CHIP_NUM_57710 0x164e 807 #define CHIP_NUM_57711 0x164f 808 #define CHIP_NUM_57711E 0x1650 809 #define CHIP_NUM_57712 0x1662 810 #define CHIP_NUM_57712_MF 0x1663 811 #define CHIP_NUM_57712_VF 0x166f 812 #define CHIP_NUM_57713 0x1651 813 #define CHIP_NUM_57713E 0x1652 814 #define CHIP_NUM_57800 0x168a 815 #define CHIP_NUM_57800_MF 0x16a5 816 #define CHIP_NUM_57800_VF 0x16a9 817 #define CHIP_NUM_57810 0x168e 818 #define CHIP_NUM_57810_MF 0x16ae 819 #define CHIP_NUM_57810_VF 0x16af 820 #define CHIP_NUM_57811 0x163d 821 #define CHIP_NUM_57811_MF 0x163e 822 #define CHIP_NUM_57811_VF 0x163f 823 #define CHIP_NUM_57840_OBSOLETE 0x168d 824 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 825 #define CHIP_NUM_57840_4_10 0x16a1 826 #define CHIP_NUM_57840_2_20 0x16a2 827 #define CHIP_NUM_57840_MF 0x16a4 828 #define CHIP_NUM_57840_VF 0x16ad 829 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 830 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 831 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 832 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 833 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 834 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 835 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 836 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 837 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 838 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 839 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 840 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 841 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 842 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 843 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 844 #define CHIP_IS_57840(bp) \ 845 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 846 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 847 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 848 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 849 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 850 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 851 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 852 CHIP_IS_57711E(bp)) 853 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 854 CHIP_IS_57712_MF(bp) || \ 855 CHIP_IS_57712_VF(bp)) 856 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 857 CHIP_IS_57800_MF(bp) || \ 858 CHIP_IS_57800_VF(bp) || \ 859 CHIP_IS_57810(bp) || \ 860 CHIP_IS_57810_MF(bp) || \ 861 CHIP_IS_57810_VF(bp) || \ 862 CHIP_IS_57811(bp) || \ 863 CHIP_IS_57811_MF(bp) || \ 864 CHIP_IS_57811_VF(bp) || \ 865 CHIP_IS_57840(bp) || \ 866 CHIP_IS_57840_MF(bp) || \ 867 CHIP_IS_57840_VF(bp)) 868 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 869 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 870 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 871 872 #define CHIP_REV_SHIFT 12 873 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 874 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 875 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 876 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 877 /* assume maximum 5 revisions */ 878 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 879 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 880 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 881 !(CHIP_REV_VAL(bp) & 0x00001000)) 882 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 883 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 884 (CHIP_REV_VAL(bp) & 0x00001000)) 885 886 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 887 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 888 889 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 890 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 891 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 892 (CHIP_REV_SHIFT + 1)) \ 893 << CHIP_REV_SHIFT) 894 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 895 CHIP_REV_SIM(bp) :\ 896 CHIP_REV_VAL(bp)) 897 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 898 (CHIP_REV(bp) == CHIP_REV_Bx)) 899 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 900 (CHIP_REV(bp) == CHIP_REV_Ax)) 901 /* This define is used in two main places: 902 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher 903 * to nic-only mode or to offload mode. Offload mode is configured if either the 904 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 905 * registered for this port (which means that the user wants storage services). 906 * 2. During cnic-related load, to know if offload mode is already configured in 907 * the HW or needs to be configrued. 908 * Since the transition from nic-mode to offload-mode in HW causes traffic 909 * coruption, nic-mode is configured only in ports on which storage services 910 * where never requested. 911 */ 912 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 913 914 int flash_size; 915 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 916 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 917 #define BNX2X_NVRAM_PAGE_SIZE 256 918 919 u32 shmem_base; 920 u32 shmem2_base; 921 u32 mf_cfg_base; 922 u32 mf2_cfg_base; 923 924 u32 hw_config; 925 926 u32 bc_ver; 927 928 u8 int_block; 929 #define INT_BLOCK_HC 0 930 #define INT_BLOCK_IGU 1 931 #define INT_BLOCK_MODE_NORMAL 0 932 #define INT_BLOCK_MODE_BW_COMP 2 933 #define CHIP_INT_MODE_IS_NBC(bp) \ 934 (!CHIP_IS_E1x(bp) && \ 935 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 936 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 937 938 u8 chip_port_mode; 939 #define CHIP_4_PORT_MODE 0x0 940 #define CHIP_2_PORT_MODE 0x1 941 #define CHIP_PORT_MODE_NONE 0x2 942 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 943 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 944 945 u32 boot_mode; 946 }; 947 948 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 949 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 950 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 951 952 #define MAX_IGU_ATTN_ACK_TO 100 953 /* end of common */ 954 955 /* port */ 956 957 struct bnx2x_port { 958 u32 pmf; 959 960 u32 link_config[LINK_CONFIG_SIZE]; 961 962 u32 supported[LINK_CONFIG_SIZE]; 963 /* link settings - missing defines */ 964 #define SUPPORTED_2500baseX_Full (1 << 15) 965 966 u32 advertising[LINK_CONFIG_SIZE]; 967 /* link settings - missing defines */ 968 #define ADVERTISED_2500baseX_Full (1 << 15) 969 970 u32 phy_addr; 971 972 /* used to synchronize phy accesses */ 973 struct mutex phy_mutex; 974 975 u32 port_stx; 976 977 struct nig_stats old_nig_stats; 978 }; 979 980 /* end of port */ 981 982 #define STATS_OFFSET32(stat_name) \ 983 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 984 985 /* slow path */ 986 987 /* slow path work-queue */ 988 extern struct workqueue_struct *bnx2x_wq; 989 990 #define BNX2X_MAX_NUM_OF_VFS 64 991 #define BNX2X_VF_CID_WND 0 992 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 993 #define BNX2X_CLIENTS_PER_VF 1 994 #define BNX2X_FIRST_VF_CID 256 995 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 996 #define BNX2X_VF_ID_INVALID 0xFF 997 998 /* 999 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1000 * control by the number of fast-path status blocks supported by the 1001 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1002 * status block represents an independent interrupts context that can 1003 * serve a regular L2 networking queue. However special L2 queues such 1004 * as the FCoE queue do not require a FP-SB and other components like 1005 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1006 * 1007 * If the maximum number of FP-SB available is X then: 1008 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1009 * regular L2 queues is Y=X-1 1010 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1011 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1012 * is Y+1 1013 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1014 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1015 * FP interrupt context for the CNIC). 1016 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1017 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 1018 */ 1019 1020 /* fast-path interrupt contexts E1x */ 1021 #define FP_SB_MAX_E1x 16 1022 /* fast-path interrupt contexts E2 */ 1023 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1024 1025 union cdu_context { 1026 struct eth_context eth; 1027 char pad[1024]; 1028 }; 1029 1030 /* CDU host DB constants */ 1031 #define CDU_ILT_PAGE_SZ_HW 2 1032 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1033 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1034 1035 #define CNIC_ISCSI_CID_MAX 256 1036 #define CNIC_FCOE_CID_MAX 2048 1037 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1038 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1039 1040 #define QM_ILT_PAGE_SZ_HW 0 1041 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1042 #define QM_CID_ROUND 1024 1043 1044 /* TM (timers) host DB constants */ 1045 #define TM_ILT_PAGE_SZ_HW 0 1046 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1047 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1048 #define TM_CONN_NUM 1024 1049 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1050 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1051 1052 /* SRC (Searcher) host DB constants */ 1053 #define SRC_ILT_PAGE_SZ_HW 0 1054 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1055 #define SRC_HASH_BITS 10 1056 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1057 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1058 #define SRC_T2_SZ SRC_ILT_SZ 1059 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1060 1061 #define MAX_DMAE_C 8 1062 1063 /* DMA memory not used in fastpath */ 1064 struct bnx2x_slowpath { 1065 union { 1066 struct mac_configuration_cmd e1x; 1067 struct eth_classify_rules_ramrod_data e2; 1068 } mac_rdata; 1069 1070 1071 union { 1072 struct tstorm_eth_mac_filter_config e1x; 1073 struct eth_filter_rules_ramrod_data e2; 1074 } rx_mode_rdata; 1075 1076 union { 1077 struct mac_configuration_cmd e1; 1078 struct eth_multicast_rules_ramrod_data e2; 1079 } mcast_rdata; 1080 1081 struct eth_rss_update_ramrod_data rss_rdata; 1082 1083 /* Queue State related ramrods are always sent under rtnl_lock */ 1084 union { 1085 struct client_init_ramrod_data init_data; 1086 struct client_update_ramrod_data update_data; 1087 } q_rdata; 1088 1089 union { 1090 struct function_start_data func_start; 1091 /* pfc configuration for DCBX ramrod */ 1092 struct flow_control_configuration pfc_config; 1093 } func_rdata; 1094 1095 /* afex ramrod can not be a part of func_rdata union because these 1096 * events might arrive in parallel to other events from func_rdata. 1097 * Therefore, if they would have been defined in the same union, 1098 * data can get corrupted. 1099 */ 1100 struct afex_vif_list_ramrod_data func_afex_rdata; 1101 1102 /* used by dmae command executer */ 1103 struct dmae_command dmae[MAX_DMAE_C]; 1104 1105 u32 stats_comp; 1106 union mac_stats mac_stats; 1107 struct nig_stats nig_stats; 1108 struct host_port_stats port_stats; 1109 struct host_func_stats func_stats; 1110 1111 u32 wb_comp; 1112 u32 wb_data[4]; 1113 1114 union drv_info_to_mcp drv_info_to_mcp; 1115 }; 1116 1117 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1118 #define bnx2x_sp_mapping(bp, var) \ 1119 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1120 1121 1122 /* attn group wiring */ 1123 #define MAX_DYNAMIC_ATTN_GRPS 8 1124 1125 struct attn_route { 1126 u32 sig[5]; 1127 }; 1128 1129 struct iro { 1130 u32 base; 1131 u16 m1; 1132 u16 m2; 1133 u16 m3; 1134 u16 size; 1135 }; 1136 1137 struct hw_context { 1138 union cdu_context *vcxt; 1139 dma_addr_t cxt_mapping; 1140 size_t size; 1141 }; 1142 1143 /* forward */ 1144 struct bnx2x_ilt; 1145 1146 struct bnx2x_vfdb; 1147 1148 enum bnx2x_recovery_state { 1149 BNX2X_RECOVERY_DONE, 1150 BNX2X_RECOVERY_INIT, 1151 BNX2X_RECOVERY_WAIT, 1152 BNX2X_RECOVERY_FAILED, 1153 BNX2X_RECOVERY_NIC_LOADING 1154 }; 1155 1156 /* 1157 * Event queue (EQ or event ring) MC hsi 1158 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1159 */ 1160 #define NUM_EQ_PAGES 1 1161 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1162 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1163 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1164 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1165 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1166 1167 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1168 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1169 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1170 1171 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1172 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1173 1174 #define BNX2X_EQ_INDEX \ 1175 (&bp->def_status_blk->sp_sb.\ 1176 index_values[HC_SP_INDEX_EQ_CONS]) 1177 1178 /* This is a data that will be used to create a link report message. 1179 * We will keep the data used for the last link report in order 1180 * to prevent reporting the same link parameters twice. 1181 */ 1182 struct bnx2x_link_report_data { 1183 u16 line_speed; /* Effective line speed */ 1184 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1185 }; 1186 1187 enum { 1188 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1189 BNX2X_LINK_REPORT_LINK_DOWN, 1190 BNX2X_LINK_REPORT_RX_FC_ON, 1191 BNX2X_LINK_REPORT_TX_FC_ON, 1192 }; 1193 1194 enum { 1195 BNX2X_PORT_QUERY_IDX, 1196 BNX2X_PF_QUERY_IDX, 1197 BNX2X_FCOE_QUERY_IDX, 1198 BNX2X_FIRST_QUEUE_QUERY_IDX, 1199 }; 1200 1201 struct bnx2x_fw_stats_req { 1202 struct stats_query_header hdr; 1203 struct stats_query_entry query[FP_SB_MAX_E1x+ 1204 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1205 }; 1206 1207 struct bnx2x_fw_stats_data { 1208 struct stats_counter storm_counters; 1209 struct per_port_stats port; 1210 struct per_pf_stats pf; 1211 struct fcoe_statistics_params fcoe; 1212 struct per_queue_stats queue_stats[1]; 1213 }; 1214 1215 /* Public slow path states */ 1216 enum { 1217 BNX2X_SP_RTNL_SETUP_TC, 1218 BNX2X_SP_RTNL_TX_TIMEOUT, 1219 BNX2X_SP_RTNL_FAN_FAILURE, 1220 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1221 BNX2X_SP_RTNL_ENABLE_SRIOV, 1222 BNX2X_SP_RTNL_VFPF_MCAST, 1223 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 1224 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1225 }; 1226 1227 1228 struct bnx2x_prev_path_list { 1229 u8 bus; 1230 u8 slot; 1231 u8 path; 1232 struct list_head list; 1233 u8 undi; 1234 }; 1235 1236 struct bnx2x_sp_objs { 1237 /* MACs object */ 1238 struct bnx2x_vlan_mac_obj mac_obj; 1239 1240 /* Queue State object */ 1241 struct bnx2x_queue_sp_obj q_obj; 1242 }; 1243 1244 struct bnx2x_fp_stats { 1245 struct tstorm_per_queue_stats old_tclient; 1246 struct ustorm_per_queue_stats old_uclient; 1247 struct xstorm_per_queue_stats old_xclient; 1248 struct bnx2x_eth_q_stats eth_q_stats; 1249 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1250 }; 1251 1252 struct bnx2x { 1253 /* Fields used in the tx and intr/napi performance paths 1254 * are grouped together in the beginning of the structure 1255 */ 1256 struct bnx2x_fastpath *fp; 1257 struct bnx2x_sp_objs *sp_objs; 1258 struct bnx2x_fp_stats *fp_stats; 1259 struct bnx2x_fp_txdata *bnx2x_txq; 1260 void __iomem *regview; 1261 void __iomem *doorbells; 1262 u16 db_size; 1263 1264 u8 pf_num; /* absolute PF number */ 1265 u8 pfid; /* per-path PF number */ 1266 int base_fw_ndsb; /**/ 1267 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1268 #define BP_PORT(bp) (bp->pfid & 1) 1269 #define BP_FUNC(bp) (bp->pfid) 1270 #define BP_ABS_FUNC(bp) (bp->pf_num) 1271 #define BP_VN(bp) ((bp)->pfid >> 1) 1272 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1273 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1274 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1275 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1276 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1277 1278 #ifdef CONFIG_BNX2X_SRIOV 1279 /* vf pf channel mailbox contains request and response buffers */ 1280 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1281 dma_addr_t vf2pf_mbox_mapping; 1282 1283 /* we set aside a copy of the acquire response */ 1284 struct pfvf_acquire_resp_tlv acquire_resp; 1285 1286 /* bulletin board for messages from pf to vf */ 1287 union pf_vf_bulletin *pf2vf_bulletin; 1288 dma_addr_t pf2vf_bulletin_mapping; 1289 1290 struct pf_vf_bulletin_content old_bulletin; 1291 1292 u16 requested_nr_virtfn; 1293 #endif /* CONFIG_BNX2X_SRIOV */ 1294 1295 struct net_device *dev; 1296 struct pci_dev *pdev; 1297 1298 const struct iro *iro_arr; 1299 #define IRO (bp->iro_arr) 1300 1301 enum bnx2x_recovery_state recovery_state; 1302 int is_leader; 1303 struct msix_entry *msix_table; 1304 1305 int tx_ring_size; 1306 1307 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1308 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1309 #define ETH_MIN_PACKET_SIZE 60 1310 #define ETH_MAX_PACKET_SIZE 1500 1311 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1312 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1313 #define ETH_MAX_TPA_HEADER_SIZE 72 1314 1315 /* Max supported alignment is 256 (8 shift) */ 1316 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1317 1318 /* FW uses 2 Cache lines Alignment for start packet and size 1319 * 1320 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1321 * at the end of skb->data, to avoid wasting a full cache line. 1322 * This reduces memory use (skb->truesize). 1323 */ 1324 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1325 1326 #define BNX2X_FW_RX_ALIGN_END \ 1327 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1328 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1329 1330 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1331 1332 struct host_sp_status_block *def_status_blk; 1333 #define DEF_SB_IGU_ID 16 1334 #define DEF_SB_ID HC_SP_SB_ID 1335 __le16 def_idx; 1336 __le16 def_att_idx; 1337 u32 attn_state; 1338 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1339 1340 /* slow path ring */ 1341 struct eth_spe *spq; 1342 dma_addr_t spq_mapping; 1343 u16 spq_prod_idx; 1344 struct eth_spe *spq_prod_bd; 1345 struct eth_spe *spq_last_bd; 1346 __le16 *dsb_sp_prod; 1347 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1348 /* used to synchronize spq accesses */ 1349 spinlock_t spq_lock; 1350 1351 /* event queue */ 1352 union event_ring_elem *eq_ring; 1353 dma_addr_t eq_mapping; 1354 u16 eq_prod; 1355 u16 eq_cons; 1356 __le16 *eq_cons_sb; 1357 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1358 1359 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1360 u16 stats_pending; 1361 /* Counter for completed statistics ramrods */ 1362 u16 stats_comp; 1363 1364 /* End of fields used in the performance code paths */ 1365 1366 int panic; 1367 int msg_enable; 1368 1369 u32 flags; 1370 #define PCIX_FLAG (1 << 0) 1371 #define PCI_32BIT_FLAG (1 << 1) 1372 #define ONE_PORT_FLAG (1 << 2) 1373 #define NO_WOL_FLAG (1 << 3) 1374 #define USING_DAC_FLAG (1 << 4) 1375 #define USING_MSIX_FLAG (1 << 5) 1376 #define USING_MSI_FLAG (1 << 6) 1377 #define DISABLE_MSI_FLAG (1 << 7) 1378 #define TPA_ENABLE_FLAG (1 << 8) 1379 #define NO_MCP_FLAG (1 << 9) 1380 #define GRO_ENABLE_FLAG (1 << 10) 1381 #define MF_FUNC_DIS (1 << 11) 1382 #define OWN_CNIC_IRQ (1 << 12) 1383 #define NO_ISCSI_OOO_FLAG (1 << 13) 1384 #define NO_ISCSI_FLAG (1 << 14) 1385 #define NO_FCOE_FLAG (1 << 15) 1386 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1387 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1388 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1389 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1390 #define IS_VF_FLAG (1 << 22) 1391 1392 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1393 1394 #ifdef CONFIG_BNX2X_SRIOV 1395 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1396 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1397 #else 1398 #define IS_VF(bp) false 1399 #define IS_PF(bp) true 1400 #endif 1401 1402 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1403 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1404 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1405 1406 u8 cnic_support; 1407 bool cnic_enabled; 1408 bool cnic_loaded; 1409 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1410 1411 /* Flag that indicates that we can start looking for FCoE L2 queue 1412 * completions in the default status block. 1413 */ 1414 bool fcoe_init; 1415 1416 int pm_cap; 1417 int mrrs; 1418 1419 struct delayed_work sp_task; 1420 atomic_t interrupt_occurred; 1421 struct delayed_work sp_rtnl_task; 1422 1423 struct delayed_work period_task; 1424 struct timer_list timer; 1425 int current_interval; 1426 1427 u16 fw_seq; 1428 u16 fw_drv_pulse_wr_seq; 1429 u32 func_stx; 1430 1431 struct link_params link_params; 1432 struct link_vars link_vars; 1433 u32 link_cnt; 1434 struct bnx2x_link_report_data last_reported_link; 1435 1436 struct mdio_if_info mdio; 1437 1438 struct bnx2x_common common; 1439 struct bnx2x_port port; 1440 1441 struct cmng_init cmng; 1442 1443 u32 mf_config[E1HVN_MAX]; 1444 u32 mf_ext_config; 1445 u32 path_has_ovlan; /* E3 */ 1446 u16 mf_ov; 1447 u8 mf_mode; 1448 #define IS_MF(bp) (bp->mf_mode != 0) 1449 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1450 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1451 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1452 1453 u8 wol; 1454 1455 int rx_ring_size; 1456 1457 u16 tx_quick_cons_trip_int; 1458 u16 tx_quick_cons_trip; 1459 u16 tx_ticks_int; 1460 u16 tx_ticks; 1461 1462 u16 rx_quick_cons_trip_int; 1463 u16 rx_quick_cons_trip; 1464 u16 rx_ticks_int; 1465 u16 rx_ticks; 1466 /* Maximal coalescing timeout in us */ 1467 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1468 1469 u32 lin_cnt; 1470 1471 u16 state; 1472 #define BNX2X_STATE_CLOSED 0 1473 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1474 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1475 #define BNX2X_STATE_OPEN 0x3000 1476 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1477 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1478 1479 #define BNX2X_STATE_DIAG 0xe000 1480 #define BNX2X_STATE_ERROR 0xf000 1481 1482 #define BNX2X_MAX_PRIORITY 8 1483 #define BNX2X_MAX_ENTRIES_PER_PRI 16 1484 #define BNX2X_MAX_COS 3 1485 #define BNX2X_MAX_TX_COS 2 1486 int num_queues; 1487 uint num_ethernet_queues; 1488 uint num_cnic_queues; 1489 int num_napi_queues; 1490 int disable_tpa; 1491 1492 u32 rx_mode; 1493 #define BNX2X_RX_MODE_NONE 0 1494 #define BNX2X_RX_MODE_NORMAL 1 1495 #define BNX2X_RX_MODE_ALLMULTI 2 1496 #define BNX2X_RX_MODE_PROMISC 3 1497 #define BNX2X_MAX_MULTICAST 64 1498 1499 u8 igu_dsb_id; 1500 u8 igu_base_sb; 1501 u8 igu_sb_cnt; 1502 u8 min_msix_vec_cnt; 1503 1504 u32 igu_base_addr; 1505 dma_addr_t def_status_blk_mapping; 1506 1507 struct bnx2x_slowpath *slowpath; 1508 dma_addr_t slowpath_mapping; 1509 1510 /* Total number of FW statistics requests */ 1511 u8 fw_stats_num; 1512 1513 /* 1514 * This is a memory buffer that will contain both statistics 1515 * ramrod request and data. 1516 */ 1517 void *fw_stats; 1518 dma_addr_t fw_stats_mapping; 1519 1520 /* 1521 * FW statistics request shortcut (points at the 1522 * beginning of fw_stats buffer). 1523 */ 1524 struct bnx2x_fw_stats_req *fw_stats_req; 1525 dma_addr_t fw_stats_req_mapping; 1526 int fw_stats_req_sz; 1527 1528 /* 1529 * FW statistics data shortcut (points at the beginning of 1530 * fw_stats buffer + fw_stats_req_sz). 1531 */ 1532 struct bnx2x_fw_stats_data *fw_stats_data; 1533 dma_addr_t fw_stats_data_mapping; 1534 int fw_stats_data_sz; 1535 1536 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1537 * context size we need 8 ILT entries. 1538 */ 1539 #define ILT_MAX_L2_LINES 8 1540 struct hw_context context[ILT_MAX_L2_LINES]; 1541 1542 struct bnx2x_ilt *ilt; 1543 #define BP_ILT(bp) ((bp)->ilt) 1544 #define ILT_MAX_LINES 256 1545 /* 1546 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1547 * to CNIC. 1548 */ 1549 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1550 1551 /* 1552 * Maximum CID count that might be required by the bnx2x: 1553 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1554 */ 1555 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1556 + 2 * CNIC_SUPPORT(bp)) 1557 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1558 + 2 * CNIC_SUPPORT(bp)) 1559 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1560 ILT_PAGE_CIDS)) 1561 1562 int qm_cid_count; 1563 1564 bool dropless_fc; 1565 1566 void *t2; 1567 dma_addr_t t2_mapping; 1568 struct cnic_ops __rcu *cnic_ops; 1569 void *cnic_data; 1570 u32 cnic_tag; 1571 struct cnic_eth_dev cnic_eth_dev; 1572 union host_hc_status_block cnic_sb; 1573 dma_addr_t cnic_sb_mapping; 1574 struct eth_spe *cnic_kwq; 1575 struct eth_spe *cnic_kwq_prod; 1576 struct eth_spe *cnic_kwq_cons; 1577 struct eth_spe *cnic_kwq_last; 1578 u16 cnic_kwq_pending; 1579 u16 cnic_spq_pending; 1580 u8 fip_mac[ETH_ALEN]; 1581 struct mutex cnic_mutex; 1582 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1583 1584 /* Start index of the "special" (CNIC related) L2 cleints */ 1585 u8 cnic_base_cl_id; 1586 1587 int dmae_ready; 1588 /* used to synchronize dmae accesses */ 1589 spinlock_t dmae_lock; 1590 1591 /* used to protect the FW mail box */ 1592 struct mutex fw_mb_mutex; 1593 1594 /* used to synchronize stats collecting */ 1595 int stats_state; 1596 1597 /* used for synchronization of concurrent threads statistics handling */ 1598 spinlock_t stats_lock; 1599 1600 /* used by dmae command loader */ 1601 struct dmae_command stats_dmae; 1602 int executer_idx; 1603 1604 u16 stats_counter; 1605 struct bnx2x_eth_stats eth_stats; 1606 struct host_func_stats func_stats; 1607 struct bnx2x_eth_stats_old eth_stats_old; 1608 struct bnx2x_net_stats_old net_stats_old; 1609 struct bnx2x_fw_port_stats_old fw_stats_old; 1610 bool stats_init; 1611 1612 struct z_stream_s *strm; 1613 void *gunzip_buf; 1614 dma_addr_t gunzip_mapping; 1615 int gunzip_outlen; 1616 #define FW_BUF_SIZE 0x8000 1617 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1618 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1619 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1620 1621 struct raw_op *init_ops; 1622 /* Init blocks offsets inside init_ops */ 1623 u16 *init_ops_offsets; 1624 /* Data blob - has 32 bit granularity */ 1625 u32 *init_data; 1626 u32 init_mode_flags; 1627 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1628 /* Zipped PRAM blobs - raw data */ 1629 const u8 *tsem_int_table_data; 1630 const u8 *tsem_pram_data; 1631 const u8 *usem_int_table_data; 1632 const u8 *usem_pram_data; 1633 const u8 *xsem_int_table_data; 1634 const u8 *xsem_pram_data; 1635 const u8 *csem_int_table_data; 1636 const u8 *csem_pram_data; 1637 #define INIT_OPS(bp) (bp->init_ops) 1638 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1639 #define INIT_DATA(bp) (bp->init_data) 1640 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1641 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1642 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1643 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1644 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1645 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1646 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1647 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1648 1649 #define PHY_FW_VER_LEN 20 1650 char fw_ver[32]; 1651 const struct firmware *firmware; 1652 1653 struct bnx2x_vfdb *vfdb; 1654 #define IS_SRIOV(bp) ((bp)->vfdb) 1655 1656 /* DCB support on/off */ 1657 u16 dcb_state; 1658 #define BNX2X_DCB_STATE_OFF 0 1659 #define BNX2X_DCB_STATE_ON 1 1660 1661 /* DCBX engine mode */ 1662 int dcbx_enabled; 1663 #define BNX2X_DCBX_ENABLED_OFF 0 1664 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1665 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1666 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1667 1668 bool dcbx_mode_uset; 1669 1670 struct bnx2x_config_dcbx_params dcbx_config_params; 1671 struct bnx2x_dcbx_port_params dcbx_port_params; 1672 int dcb_version; 1673 1674 /* CAM credit pools */ 1675 1676 /* used only in sriov */ 1677 struct bnx2x_credit_pool_obj vlans_pool; 1678 1679 struct bnx2x_credit_pool_obj macs_pool; 1680 1681 /* RX_MODE object */ 1682 struct bnx2x_rx_mode_obj rx_mode_obj; 1683 1684 /* MCAST object */ 1685 struct bnx2x_mcast_obj mcast_obj; 1686 1687 /* RSS configuration object */ 1688 struct bnx2x_rss_config_obj rss_conf_obj; 1689 1690 /* Function State controlling object */ 1691 struct bnx2x_func_sp_obj func_obj; 1692 1693 unsigned long sp_state; 1694 1695 /* operation indication for the sp_rtnl task */ 1696 unsigned long sp_rtnl_state; 1697 1698 /* DCBX Negotation results */ 1699 struct dcbx_features dcbx_local_feat; 1700 u32 dcbx_error; 1701 1702 #ifdef BCM_DCBNL 1703 struct dcbx_features dcbx_remote_feat; 1704 u32 dcbx_remote_flags; 1705 #endif 1706 /* AFEX: store default vlan used */ 1707 int afex_def_vlan_tag; 1708 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1709 u32 pending_max; 1710 1711 /* multiple tx classes of service */ 1712 u8 max_cos; 1713 1714 /* priority to cos mapping */ 1715 u8 prio_to_cos[8]; 1716 1717 int fp_array_size; 1718 u32 dump_preset_idx; 1719 }; 1720 1721 /* Tx queues may be less or equal to Rx queues */ 1722 extern int num_queues; 1723 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1724 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1725 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1726 (bp)->num_cnic_queues) 1727 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1728 1729 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1730 1731 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1732 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1733 1734 #define RSS_IPV4_CAP_MASK \ 1735 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1736 1737 #define RSS_IPV4_TCP_CAP_MASK \ 1738 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1739 1740 #define RSS_IPV6_CAP_MASK \ 1741 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1742 1743 #define RSS_IPV6_TCP_CAP_MASK \ 1744 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1745 1746 /* func init flags */ 1747 #define FUNC_FLG_RSS 0x0001 1748 #define FUNC_FLG_STATS 0x0002 1749 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1750 #define FUNC_FLG_TPA 0x0008 1751 #define FUNC_FLG_SPQ 0x0010 1752 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1753 1754 1755 struct bnx2x_func_init_params { 1756 /* dma */ 1757 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1758 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1759 1760 u16 func_flgs; 1761 u16 func_id; /* abs fid */ 1762 u16 pf_id; 1763 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1764 }; 1765 1766 #define for_each_cnic_queue(bp, var) \ 1767 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1768 (var)++) \ 1769 if (skip_queue(bp, var)) \ 1770 continue; \ 1771 else 1772 1773 #define for_each_eth_queue(bp, var) \ 1774 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1775 1776 #define for_each_nondefault_eth_queue(bp, var) \ 1777 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1778 1779 #define for_each_queue(bp, var) \ 1780 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1781 if (skip_queue(bp, var)) \ 1782 continue; \ 1783 else 1784 1785 /* Skip forwarding FP */ 1786 #define for_each_valid_rx_queue(bp, var) \ 1787 for ((var) = 0; \ 1788 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1789 BNX2X_NUM_ETH_QUEUES(bp)); \ 1790 (var)++) \ 1791 if (skip_rx_queue(bp, var)) \ 1792 continue; \ 1793 else 1794 1795 #define for_each_rx_queue_cnic(bp, var) \ 1796 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1797 (var)++) \ 1798 if (skip_rx_queue(bp, var)) \ 1799 continue; \ 1800 else 1801 1802 #define for_each_rx_queue(bp, var) \ 1803 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1804 if (skip_rx_queue(bp, var)) \ 1805 continue; \ 1806 else 1807 1808 /* Skip OOO FP */ 1809 #define for_each_valid_tx_queue(bp, var) \ 1810 for ((var) = 0; \ 1811 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1812 BNX2X_NUM_ETH_QUEUES(bp)); \ 1813 (var)++) \ 1814 if (skip_tx_queue(bp, var)) \ 1815 continue; \ 1816 else 1817 1818 #define for_each_tx_queue_cnic(bp, var) \ 1819 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1820 (var)++) \ 1821 if (skip_tx_queue(bp, var)) \ 1822 continue; \ 1823 else 1824 1825 #define for_each_tx_queue(bp, var) \ 1826 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1827 if (skip_tx_queue(bp, var)) \ 1828 continue; \ 1829 else 1830 1831 #define for_each_nondefault_queue(bp, var) \ 1832 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1833 if (skip_queue(bp, var)) \ 1834 continue; \ 1835 else 1836 1837 #define for_each_cos_in_tx_queue(fp, var) \ 1838 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1839 1840 /* skip rx queue 1841 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1842 */ 1843 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1844 1845 /* skip tx queue 1846 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1847 */ 1848 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1849 1850 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1851 1852 1853 1854 1855 /** 1856 * bnx2x_set_mac_one - configure a single MAC address 1857 * 1858 * @bp: driver handle 1859 * @mac: MAC to configure 1860 * @obj: MAC object handle 1861 * @set: if 'true' add a new MAC, otherwise - delete 1862 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1863 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1864 * 1865 * Configures one MAC according to provided parameters or continues the 1866 * execution of previously scheduled commands if RAMROD_CONT is set in 1867 * ramrod_flags. 1868 * 1869 * Returns zero if operation has successfully completed, a positive value if the 1870 * operation has been successfully scheduled and a negative - if a requested 1871 * operations has failed. 1872 */ 1873 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1874 struct bnx2x_vlan_mac_obj *obj, bool set, 1875 int mac_type, unsigned long *ramrod_flags); 1876 /** 1877 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1878 * 1879 * @bp: driver handle 1880 * @mac_obj: MAC object handle 1881 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1882 * @wait_for_comp: if 'true' block until completion 1883 * 1884 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1885 * 1886 * Returns zero if operation has successfully completed, a positive value if the 1887 * operation has been successfully scheduled and a negative - if a requested 1888 * operations has failed. 1889 */ 1890 int bnx2x_del_all_macs(struct bnx2x *bp, 1891 struct bnx2x_vlan_mac_obj *mac_obj, 1892 int mac_type, bool wait_for_comp); 1893 1894 /* Init Function API */ 1895 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1896 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 1897 u8 vf_valid, int fw_sb_id, int igu_sb_id); 1898 u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 1899 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1900 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1901 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1902 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1903 void bnx2x_read_mf_cfg(struct bnx2x *bp); 1904 1905 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 1906 1907 /* dmae */ 1908 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1909 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1910 u32 len32); 1911 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1912 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1913 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1914 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1915 bool with_comp, u8 comp_type); 1916 1917 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 1918 u8 src_type, u8 dst_type); 1919 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); 1920 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl); 1921 1922 /* FLR related routines */ 1923 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 1924 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 1925 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 1926 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 1927 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1928 char *msg, u32 poll_cnt); 1929 1930 void bnx2x_calc_fc_adv(struct bnx2x *bp); 1931 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1932 u32 data_hi, u32 data_lo, int cmd_type); 1933 void bnx2x_update_coalesce(struct bnx2x *bp); 1934 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1935 1936 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1937 int wait) 1938 { 1939 u32 val; 1940 1941 do { 1942 val = REG_RD(bp, reg); 1943 if (val == expected) 1944 break; 1945 ms -= wait; 1946 msleep(wait); 1947 1948 } while (ms > 0); 1949 1950 return val; 1951 } 1952 1953 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 1954 bool is_pf); 1955 1956 #define BNX2X_ILT_ZALLOC(x, y, size) \ 1957 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ 1958 GFP_KERNEL | __GFP_ZERO) 1959 1960 #define BNX2X_ILT_FREE(x, y, size) \ 1961 do { \ 1962 if (x) { \ 1963 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1964 x = NULL; \ 1965 y = 0; \ 1966 } \ 1967 } while (0) 1968 1969 #define ILOG2(x) (ilog2((x))) 1970 1971 #define ILT_NUM_PAGE_ENTRIES (3072) 1972 /* In 57710/11 we use whole table since we have 8 func 1973 * In 57712 we have only 4 func, but use same size per func, then only half of 1974 * the table in use 1975 */ 1976 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1977 1978 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1979 /* 1980 * the phys address is shifted right 12 bits and has an added 1981 * 1=valid bit added to the 53rd bit 1982 * then since this is a wide register(TM) 1983 * we split it into two 32 bit writes 1984 */ 1985 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1986 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1987 1988 /* load/unload mode */ 1989 #define LOAD_NORMAL 0 1990 #define LOAD_OPEN 1 1991 #define LOAD_DIAG 2 1992 #define LOAD_LOOPBACK_EXT 3 1993 #define UNLOAD_NORMAL 0 1994 #define UNLOAD_CLOSE 1 1995 #define UNLOAD_RECOVERY 2 1996 1997 1998 /* DMAE command defines */ 1999 #define DMAE_TIMEOUT -1 2000 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2001 #define DMAE_NOT_RDY -3 2002 #define DMAE_PCI_ERR_FLAG 0x80000000 2003 2004 #define DMAE_SRC_PCI 0 2005 #define DMAE_SRC_GRC 1 2006 2007 #define DMAE_DST_NONE 0 2008 #define DMAE_DST_PCI 1 2009 #define DMAE_DST_GRC 2 2010 2011 #define DMAE_COMP_PCI 0 2012 #define DMAE_COMP_GRC 1 2013 2014 /* E2 and onward - PCI error handling in the completion */ 2015 2016 #define DMAE_COMP_REGULAR 0 2017 #define DMAE_COM_SET_ERR 1 2018 2019 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2020 DMAE_COMMAND_SRC_SHIFT) 2021 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2022 DMAE_COMMAND_SRC_SHIFT) 2023 2024 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2025 DMAE_COMMAND_DST_SHIFT) 2026 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2027 DMAE_COMMAND_DST_SHIFT) 2028 2029 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2030 DMAE_COMMAND_C_DST_SHIFT) 2031 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2032 DMAE_COMMAND_C_DST_SHIFT) 2033 2034 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2035 2036 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2037 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2038 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2039 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2040 2041 #define DMAE_CMD_PORT_0 0 2042 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2043 2044 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2045 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2046 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2047 2048 #define DMAE_SRC_PF 0 2049 #define DMAE_SRC_VF 1 2050 2051 #define DMAE_DST_PF 0 2052 #define DMAE_DST_VF 1 2053 2054 #define DMAE_C_SRC 0 2055 #define DMAE_C_DST 1 2056 2057 #define DMAE_LEN32_RD_MAX 0x80 2058 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2059 2060 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2061 indicates eror */ 2062 2063 #define MAX_DMAE_C_PER_PORT 8 2064 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2065 BP_VN(bp)) 2066 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2067 E1HVN_MAX) 2068 2069 /* PCIE link and speed */ 2070 #define PCICFG_LINK_WIDTH 0x1f00000 2071 #define PCICFG_LINK_WIDTH_SHIFT 20 2072 #define PCICFG_LINK_SPEED 0xf0000 2073 #define PCICFG_LINK_SPEED_SHIFT 16 2074 2075 #define BNX2X_NUM_TESTS_SF 7 2076 #define BNX2X_NUM_TESTS_MF 3 2077 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2078 BNX2X_NUM_TESTS_SF) 2079 2080 #define BNX2X_PHY_LOOPBACK 0 2081 #define BNX2X_MAC_LOOPBACK 1 2082 #define BNX2X_EXT_LOOPBACK 2 2083 #define BNX2X_PHY_LOOPBACK_FAILED 1 2084 #define BNX2X_MAC_LOOPBACK_FAILED 2 2085 #define BNX2X_EXT_LOOPBACK_FAILED 3 2086 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2087 BNX2X_PHY_LOOPBACK_FAILED) 2088 2089 #define STROM_ASSERT_ARRAY_SIZE 50 2090 2091 /* must be used on a CID before placing it on a HW ring */ 2092 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2093 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2094 (x)) 2095 2096 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2097 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2098 2099 2100 #define BNX2X_BTR 4 2101 #define MAX_SPQ_PENDING 8 2102 2103 /* CMNG constants, as derived from system spec calculations */ 2104 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2105 #define DEF_MIN_RATE 100 2106 /* resolution of the rate shaping timer - 400 usec */ 2107 #define RS_PERIODIC_TIMEOUT_USEC 400 2108 /* number of bytes in single QM arbitration cycle - 2109 * coefficient for calculating the fairness timer */ 2110 #define QM_ARB_BYTES 160000 2111 /* resolution of Min algorithm 1:100 */ 2112 #define MIN_RES 100 2113 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2114 #define MIN_ABOVE_THRESH 32768 2115 /* Fairness algorithm integration time coefficient - 2116 * for calculating the actual Tfair */ 2117 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2118 /* Memory of fairness algorithm . 2 cycles */ 2119 #define FAIR_MEM 2 2120 2121 #define ATTN_NIG_FOR_FUNC (1L << 8) 2122 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2123 #define GPIO_2_FUNC (1L << 10) 2124 #define GPIO_3_FUNC (1L << 11) 2125 #define GPIO_4_FUNC (1L << 12) 2126 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2127 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2128 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2129 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2130 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2131 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2132 2133 #define ATTN_HARD_WIRED_MASK 0xff00 2134 #define ATTENTION_ID 4 2135 2136 2137 /* stuff added to make the code fit 80Col */ 2138 2139 #define BNX2X_PMF_LINK_ASSERT \ 2140 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2141 2142 #define BNX2X_MC_ASSERT_BITS \ 2143 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2144 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2145 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2146 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2147 2148 #define BNX2X_MCP_ASSERT \ 2149 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2150 2151 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2152 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2153 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2154 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2155 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2156 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2157 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2158 2159 #define HW_INTERRUT_ASSERT_SET_0 \ 2160 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2161 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2162 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2163 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2164 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2165 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2166 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2167 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2168 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2169 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2170 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2171 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2172 #define HW_INTERRUT_ASSERT_SET_1 \ 2173 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2174 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2175 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2176 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2177 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2178 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2179 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2180 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2181 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2182 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2183 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2184 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2185 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2186 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2187 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2188 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2189 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2190 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2191 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2192 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2193 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2194 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2195 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2196 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2197 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2198 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2199 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2200 #define HW_INTERRUT_ASSERT_SET_2 \ 2201 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2202 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2203 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2204 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2205 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2206 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2207 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2208 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2209 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2210 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2211 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2212 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2213 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2214 2215 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2216 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2217 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2218 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2219 2220 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2221 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2222 2223 #define MULTI_MASK 0x7f 2224 2225 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2226 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2227 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2228 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2229 2230 #define DEF_USB_IGU_INDEX_OFF \ 2231 offsetof(struct cstorm_def_status_block_u, igu_index) 2232 #define DEF_CSB_IGU_INDEX_OFF \ 2233 offsetof(struct cstorm_def_status_block_c, igu_index) 2234 #define DEF_XSB_IGU_INDEX_OFF \ 2235 offsetof(struct xstorm_def_status_block, igu_index) 2236 #define DEF_TSB_IGU_INDEX_OFF \ 2237 offsetof(struct tstorm_def_status_block, igu_index) 2238 2239 #define DEF_USB_SEGMENT_OFF \ 2240 offsetof(struct cstorm_def_status_block_u, segment) 2241 #define DEF_CSB_SEGMENT_OFF \ 2242 offsetof(struct cstorm_def_status_block_c, segment) 2243 #define DEF_XSB_SEGMENT_OFF \ 2244 offsetof(struct xstorm_def_status_block, segment) 2245 #define DEF_TSB_SEGMENT_OFF \ 2246 offsetof(struct tstorm_def_status_block, segment) 2247 2248 #define BNX2X_SP_DSB_INDEX \ 2249 (&bp->def_status_blk->sp_sb.\ 2250 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2251 2252 #define CAM_IS_INVALID(x) \ 2253 (GET_FLAG(x.flags, \ 2254 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2255 (T_ETH_MAC_COMMAND_INVALIDATE)) 2256 2257 /* Number of u32 elements in MC hash array */ 2258 #define MC_HASH_SIZE 8 2259 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2260 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2261 2262 #ifndef PXP2_REG_PXP2_INT_STS 2263 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2264 #endif 2265 2266 #ifndef ETH_MAX_RX_CLIENTS_E2 2267 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2268 #endif 2269 2270 #define BNX2X_VPD_LEN 128 2271 #define VENDOR_ID_LEN 4 2272 2273 #define VF_ACQUIRE_THRESH 3 2274 #define VF_ACQUIRE_MAC_FILTERS 1 2275 #define VF_ACQUIRE_MC_FILTERS 10 2276 2277 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2278 (!((me_reg) & ME_REG_VF_ERR))) 2279 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2280 /* Congestion management fairness mode */ 2281 #define CMNG_FNS_NONE 0 2282 #define CMNG_FNS_MINMAX 1 2283 2284 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2285 #define HC_SEG_ACCESS_ATTN 4 2286 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2287 2288 static const u32 dmae_reg_go_c[] = { 2289 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2290 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2291 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2292 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2293 }; 2294 2295 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2296 void bnx2x_notify_link_changed(struct bnx2x *bp); 2297 2298 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2299 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2300 2301 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2302 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2303 2304 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2305 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2306 2307 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2308 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2309 2310 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2311 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2312 2313 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2314 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2315 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2316 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2317 2318 #define SET_FLAG(value, mask, flag) \ 2319 do {\ 2320 (value) &= ~(mask);\ 2321 (value) |= ((flag) << (mask##_SHIFT));\ 2322 } while (0) 2323 2324 #define GET_FLAG(value, mask) \ 2325 (((value) & (mask)) >> (mask##_SHIFT)) 2326 2327 #define GET_FIELD(value, fname) \ 2328 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2329 2330 enum { 2331 SWITCH_UPDATE, 2332 AFEX_UPDATE, 2333 }; 2334 2335 #define NUM_MACS 8 2336 2337 #endif /* bnx2x.h */ 2338