1*2e0bf125SRasesh Mody /* bnx2_fw.h: QLogic bnx2 network driver. 2adfc5217SJeff Kirsher * 3adfc5217SJeff Kirsher * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation 4*2e0bf125SRasesh Mody * Copyright (c) 2014-2015 QLogic Corporation 5adfc5217SJeff Kirsher * 6adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 7adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 8adfc5217SJeff Kirsher * the Free Software Foundation. 9adfc5217SJeff Kirsher */ 10adfc5217SJeff Kirsher 11adfc5217SJeff Kirsher /* Initialized Values for the Completion Processor. */ 12adfc5217SJeff Kirsher static const struct cpu_reg cpu_reg_com = { 13adfc5217SJeff Kirsher .mode = BNX2_COM_CPU_MODE, 14adfc5217SJeff Kirsher .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT, 15adfc5217SJeff Kirsher .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA, 16adfc5217SJeff Kirsher .state = BNX2_COM_CPU_STATE, 17adfc5217SJeff Kirsher .state_value_clear = 0xffffff, 18adfc5217SJeff Kirsher .gpr0 = BNX2_COM_CPU_REG_FILE, 19adfc5217SJeff Kirsher .evmask = BNX2_COM_CPU_EVENT_MASK, 20adfc5217SJeff Kirsher .pc = BNX2_COM_CPU_PROGRAM_COUNTER, 21adfc5217SJeff Kirsher .inst = BNX2_COM_CPU_INSTRUCTION, 22adfc5217SJeff Kirsher .bp = BNX2_COM_CPU_HW_BREAKPOINT, 23adfc5217SJeff Kirsher .spad_base = BNX2_COM_SCRATCH, 24adfc5217SJeff Kirsher .mips_view_base = 0x8000000, 25adfc5217SJeff Kirsher }; 26adfc5217SJeff Kirsher 27adfc5217SJeff Kirsher /* Initialized Values the Command Processor. */ 28adfc5217SJeff Kirsher static const struct cpu_reg cpu_reg_cp = { 29adfc5217SJeff Kirsher .mode = BNX2_CP_CPU_MODE, 30adfc5217SJeff Kirsher .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT, 31adfc5217SJeff Kirsher .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA, 32adfc5217SJeff Kirsher .state = BNX2_CP_CPU_STATE, 33adfc5217SJeff Kirsher .state_value_clear = 0xffffff, 34adfc5217SJeff Kirsher .gpr0 = BNX2_CP_CPU_REG_FILE, 35adfc5217SJeff Kirsher .evmask = BNX2_CP_CPU_EVENT_MASK, 36adfc5217SJeff Kirsher .pc = BNX2_CP_CPU_PROGRAM_COUNTER, 37adfc5217SJeff Kirsher .inst = BNX2_CP_CPU_INSTRUCTION, 38adfc5217SJeff Kirsher .bp = BNX2_CP_CPU_HW_BREAKPOINT, 39adfc5217SJeff Kirsher .spad_base = BNX2_CP_SCRATCH, 40adfc5217SJeff Kirsher .mips_view_base = 0x8000000, 41adfc5217SJeff Kirsher }; 42adfc5217SJeff Kirsher 43adfc5217SJeff Kirsher /* Initialized Values for the RX Processor. */ 44adfc5217SJeff Kirsher static const struct cpu_reg cpu_reg_rxp = { 45adfc5217SJeff Kirsher .mode = BNX2_RXP_CPU_MODE, 46adfc5217SJeff Kirsher .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT, 47adfc5217SJeff Kirsher .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA, 48adfc5217SJeff Kirsher .state = BNX2_RXP_CPU_STATE, 49adfc5217SJeff Kirsher .state_value_clear = 0xffffff, 50adfc5217SJeff Kirsher .gpr0 = BNX2_RXP_CPU_REG_FILE, 51adfc5217SJeff Kirsher .evmask = BNX2_RXP_CPU_EVENT_MASK, 52adfc5217SJeff Kirsher .pc = BNX2_RXP_CPU_PROGRAM_COUNTER, 53adfc5217SJeff Kirsher .inst = BNX2_RXP_CPU_INSTRUCTION, 54adfc5217SJeff Kirsher .bp = BNX2_RXP_CPU_HW_BREAKPOINT, 55adfc5217SJeff Kirsher .spad_base = BNX2_RXP_SCRATCH, 56adfc5217SJeff Kirsher .mips_view_base = 0x8000000, 57adfc5217SJeff Kirsher }; 58adfc5217SJeff Kirsher 59adfc5217SJeff Kirsher /* Initialized Values for the TX Patch-up Processor. */ 60adfc5217SJeff Kirsher static const struct cpu_reg cpu_reg_tpat = { 61adfc5217SJeff Kirsher .mode = BNX2_TPAT_CPU_MODE, 62adfc5217SJeff Kirsher .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT, 63adfc5217SJeff Kirsher .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA, 64adfc5217SJeff Kirsher .state = BNX2_TPAT_CPU_STATE, 65adfc5217SJeff Kirsher .state_value_clear = 0xffffff, 66adfc5217SJeff Kirsher .gpr0 = BNX2_TPAT_CPU_REG_FILE, 67adfc5217SJeff Kirsher .evmask = BNX2_TPAT_CPU_EVENT_MASK, 68adfc5217SJeff Kirsher .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER, 69adfc5217SJeff Kirsher .inst = BNX2_TPAT_CPU_INSTRUCTION, 70adfc5217SJeff Kirsher .bp = BNX2_TPAT_CPU_HW_BREAKPOINT, 71adfc5217SJeff Kirsher .spad_base = BNX2_TPAT_SCRATCH, 72adfc5217SJeff Kirsher .mips_view_base = 0x8000000, 73adfc5217SJeff Kirsher }; 74adfc5217SJeff Kirsher 75adfc5217SJeff Kirsher /* Initialized Values for the TX Processor. */ 76adfc5217SJeff Kirsher static const struct cpu_reg cpu_reg_txp = { 77adfc5217SJeff Kirsher .mode = BNX2_TXP_CPU_MODE, 78adfc5217SJeff Kirsher .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT, 79adfc5217SJeff Kirsher .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA, 80adfc5217SJeff Kirsher .state = BNX2_TXP_CPU_STATE, 81adfc5217SJeff Kirsher .state_value_clear = 0xffffff, 82adfc5217SJeff Kirsher .gpr0 = BNX2_TXP_CPU_REG_FILE, 83adfc5217SJeff Kirsher .evmask = BNX2_TXP_CPU_EVENT_MASK, 84adfc5217SJeff Kirsher .pc = BNX2_TXP_CPU_PROGRAM_COUNTER, 85adfc5217SJeff Kirsher .inst = BNX2_TXP_CPU_INSTRUCTION, 86adfc5217SJeff Kirsher .bp = BNX2_TXP_CPU_HW_BREAKPOINT, 87adfc5217SJeff Kirsher .spad_base = BNX2_TXP_SCRATCH, 88adfc5217SJeff Kirsher .mips_view_base = 0x8000000, 89adfc5217SJeff Kirsher }; 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