1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <bcm47xx_nvram.h> 21 22 static const struct bcma_device_id bgmac_bcma_tbl[] = { 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 28 29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 30 u32 value, int timeout) 31 { 32 u32 val; 33 int i; 34 35 for (i = 0; i < timeout / 10; i++) { 36 val = bcma_read32(core, reg); 37 if ((val & mask) == value) 38 return true; 39 udelay(10); 40 } 41 pr_err("Timeout waiting for reg 0x%X\n", reg); 42 return false; 43 } 44 45 /************************************************** 46 * DMA 47 **************************************************/ 48 49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 50 { 51 u32 val; 52 int i; 53 54 if (!ring->mmio_base) 55 return; 56 57 /* Suspend DMA TX ring first. 58 * bgmac_wait_value doesn't support waiting for any of few values, so 59 * implement whole loop here. 60 */ 61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 62 BGMAC_DMA_TX_SUSPEND); 63 for (i = 0; i < 10000 / 10; i++) { 64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 65 val &= BGMAC_DMA_TX_STAT; 66 if (val == BGMAC_DMA_TX_STAT_DISABLED || 67 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 68 val == BGMAC_DMA_TX_STAT_STOPPED) { 69 i = 0; 70 break; 71 } 72 udelay(10); 73 } 74 if (i) 75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 76 ring->mmio_base, val); 77 78 /* Remove SUSPEND bit */ 79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 80 if (!bgmac_wait_value(bgmac->core, 81 ring->mmio_base + BGMAC_DMA_TX_STATUS, 82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 83 10000)) { 84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 85 ring->mmio_base); 86 udelay(300); 87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 90 ring->mmio_base); 91 } 92 } 93 94 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 95 struct bgmac_dma_ring *ring) 96 { 97 u32 ctl; 98 99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 100 if (bgmac->core->id.rev >= 4) { 101 ctl &= ~BGMAC_DMA_TX_BL_MASK; 102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 103 104 ctl &= ~BGMAC_DMA_TX_MR_MASK; 105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 106 107 ctl &= ~BGMAC_DMA_TX_PC_MASK; 108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 109 110 ctl &= ~BGMAC_DMA_TX_PT_MASK; 111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 112 } 113 ctl |= BGMAC_DMA_TX_ENABLE; 114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 116 } 117 118 static void 119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 120 int i, int len, u32 ctl0) 121 { 122 struct bgmac_slot_info *slot; 123 struct bgmac_dma_desc *dma_desc; 124 u32 ctl1; 125 126 if (i == ring->num_slots - 1) 127 ctl0 |= BGMAC_DESC_CTL0_EOT; 128 129 ctl1 = len & BGMAC_DESC_CTL1_LEN; 130 131 slot = &ring->slots[i]; 132 dma_desc = &ring->cpu_base[i]; 133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 135 dma_desc->ctl0 = cpu_to_le32(ctl0); 136 dma_desc->ctl1 = cpu_to_le32(ctl1); 137 } 138 139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 140 struct bgmac_dma_ring *ring, 141 struct sk_buff *skb) 142 { 143 struct device *dma_dev = bgmac->core->dma_dev; 144 struct net_device *net_dev = bgmac->net_dev; 145 int index = ring->end % BGMAC_TX_RING_SLOTS; 146 struct bgmac_slot_info *slot = &ring->slots[index]; 147 int nr_frags; 148 u32 flags; 149 int i; 150 151 if (skb->len > BGMAC_DESC_CTL1_LEN) { 152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 153 goto err_drop; 154 } 155 156 if (skb->ip_summed == CHECKSUM_PARTIAL) 157 skb_checksum_help(skb); 158 159 nr_frags = skb_shinfo(skb)->nr_frags; 160 161 /* ring->end - ring->start will return the number of valid slots, 162 * even when ring->end overflows 163 */ 164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 166 netif_stop_queue(net_dev); 167 return NETDEV_TX_BUSY; 168 } 169 170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 171 DMA_TO_DEVICE); 172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 173 goto err_dma_head; 174 175 flags = BGMAC_DESC_CTL0_SOF; 176 if (!nr_frags) 177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 178 179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 180 flags = 0; 181 182 for (i = 0; i < nr_frags; i++) { 183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 184 int len = skb_frag_size(frag); 185 186 index = (index + 1) % BGMAC_TX_RING_SLOTS; 187 slot = &ring->slots[index]; 188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 189 len, DMA_TO_DEVICE); 190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 191 goto err_dma; 192 193 if (i == nr_frags - 1) 194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 195 196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 197 } 198 199 slot->skb = skb; 200 ring->end += nr_frags + 1; 201 netdev_sent_queue(net_dev, skb->len); 202 203 wmb(); 204 205 /* Increase ring->end to point empty slot. We tell hardware the first 206 * slot it should *not* read. 207 */ 208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 209 ring->index_base + 210 (ring->end % BGMAC_TX_RING_SLOTS) * 211 sizeof(struct bgmac_dma_desc)); 212 213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 214 netif_stop_queue(net_dev); 215 216 return NETDEV_TX_OK; 217 218 err_dma: 219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 220 DMA_TO_DEVICE); 221 222 while (i > 0) { 223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 224 struct bgmac_slot_info *slot = &ring->slots[index]; 225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 226 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 227 228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 229 } 230 231 err_dma_head: 232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 233 ring->mmio_base); 234 235 err_drop: 236 dev_kfree_skb(skb); 237 return NETDEV_TX_OK; 238 } 239 240 /* Free transmitted packets */ 241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 242 { 243 struct device *dma_dev = bgmac->core->dma_dev; 244 int empty_slot; 245 bool freed = false; 246 unsigned bytes_compl = 0, pkts_compl = 0; 247 248 /* The last slot that hardware didn't consume yet */ 249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 250 empty_slot &= BGMAC_DMA_TX_STATDPTR; 251 empty_slot -= ring->index_base; 252 empty_slot &= BGMAC_DMA_TX_STATDPTR; 253 empty_slot /= sizeof(struct bgmac_dma_desc); 254 255 while (ring->start != ring->end) { 256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 257 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 258 u32 ctl1; 259 int len; 260 261 if (slot_idx == empty_slot) 262 break; 263 264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 265 len = ctl1 & BGMAC_DESC_CTL1_LEN; 266 if (ctl1 & BGMAC_DESC_CTL0_SOF) 267 /* Unmap no longer used buffer */ 268 dma_unmap_single(dma_dev, slot->dma_addr, len, 269 DMA_TO_DEVICE); 270 else 271 dma_unmap_page(dma_dev, slot->dma_addr, len, 272 DMA_TO_DEVICE); 273 274 if (slot->skb) { 275 bytes_compl += slot->skb->len; 276 pkts_compl++; 277 278 /* Free memory! :) */ 279 dev_kfree_skb(slot->skb); 280 slot->skb = NULL; 281 } 282 283 slot->dma_addr = 0; 284 ring->start++; 285 freed = true; 286 } 287 288 if (!pkts_compl) 289 return; 290 291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 292 293 if (netif_queue_stopped(bgmac->net_dev)) 294 netif_wake_queue(bgmac->net_dev); 295 } 296 297 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 298 { 299 if (!ring->mmio_base) 300 return; 301 302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 303 if (!bgmac_wait_value(bgmac->core, 304 ring->mmio_base + BGMAC_DMA_RX_STATUS, 305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 306 10000)) 307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 308 ring->mmio_base); 309 } 310 311 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 312 struct bgmac_dma_ring *ring) 313 { 314 u32 ctl; 315 316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 317 if (bgmac->core->id.rev >= 4) { 318 ctl &= ~BGMAC_DMA_RX_BL_MASK; 319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 320 321 ctl &= ~BGMAC_DMA_RX_PC_MASK; 322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 323 324 ctl &= ~BGMAC_DMA_RX_PT_MASK; 325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 326 } 327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 328 ctl |= BGMAC_DMA_RX_ENABLE; 329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 333 } 334 335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 336 struct bgmac_slot_info *slot) 337 { 338 struct device *dma_dev = bgmac->core->dma_dev; 339 dma_addr_t dma_addr; 340 struct bgmac_rx_header *rx; 341 void *buf; 342 343 /* Alloc skb */ 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 345 if (!buf) 346 return -ENOMEM; 347 348 /* Poison - if everything goes fine, hardware will overwrite it */ 349 rx = buf; 350 rx->len = cpu_to_le16(0xdead); 351 rx->flags = cpu_to_le16(0xbeef); 352 353 /* Map skb for the DMA */ 354 dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE, 355 DMA_FROM_DEVICE); 356 if (dma_mapping_error(dma_dev, dma_addr)) { 357 bgmac_err(bgmac, "DMA mapping error\n"); 358 put_page(virt_to_head_page(buf)); 359 return -ENOMEM; 360 } 361 362 /* Update the slot */ 363 slot->buf = buf; 364 slot->dma_addr = dma_addr; 365 366 return 0; 367 } 368 369 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 370 struct bgmac_dma_ring *ring, int desc_idx) 371 { 372 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 373 u32 ctl0 = 0, ctl1 = 0; 374 375 if (desc_idx == ring->num_slots - 1) 376 ctl0 |= BGMAC_DESC_CTL0_EOT; 377 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 378 /* Is there any BGMAC device that requires extension? */ 379 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 380 * B43_DMA64_DCTL1_ADDREXT_MASK; 381 */ 382 383 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 384 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 385 dma_desc->ctl0 = cpu_to_le32(ctl0); 386 dma_desc->ctl1 = cpu_to_le32(ctl1); 387 } 388 389 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 390 int weight) 391 { 392 u32 end_slot; 393 int handled = 0; 394 395 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 396 end_slot &= BGMAC_DMA_RX_STATDPTR; 397 end_slot -= ring->index_base; 398 end_slot &= BGMAC_DMA_RX_STATDPTR; 399 end_slot /= sizeof(struct bgmac_dma_desc); 400 401 ring->end = end_slot; 402 403 while (ring->start != ring->end) { 404 struct device *dma_dev = bgmac->core->dma_dev; 405 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 406 struct bgmac_rx_header *rx = slot->buf; 407 struct sk_buff *skb; 408 void *buf = slot->buf; 409 u16 len, flags; 410 411 /* Unmap buffer to make it accessible to the CPU */ 412 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, 413 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 414 415 /* Get info from the header */ 416 len = le16_to_cpu(rx->len); 417 flags = le16_to_cpu(rx->flags); 418 419 do { 420 dma_addr_t old_dma_addr = slot->dma_addr; 421 int err; 422 423 /* Check for poison and drop or pass the packet */ 424 if (len == 0xdead && flags == 0xbeef) { 425 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 426 ring->start); 427 dma_sync_single_for_device(dma_dev, 428 slot->dma_addr, 429 BGMAC_RX_BUF_SIZE, 430 DMA_FROM_DEVICE); 431 break; 432 } 433 434 /* Omit CRC. */ 435 len -= ETH_FCS_LEN; 436 437 /* Prepare new skb as replacement */ 438 err = bgmac_dma_rx_skb_for_slot(bgmac, slot); 439 if (err) { 440 /* Poison the old skb */ 441 rx->len = cpu_to_le16(0xdead); 442 rx->flags = cpu_to_le16(0xbeef); 443 444 dma_sync_single_for_device(dma_dev, 445 slot->dma_addr, 446 BGMAC_RX_BUF_SIZE, 447 DMA_FROM_DEVICE); 448 break; 449 } 450 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 451 452 /* Unmap old skb, we'll pass it to the netfif */ 453 dma_unmap_single(dma_dev, old_dma_addr, 454 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 455 456 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 457 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); 458 skb_pull(skb, BGMAC_RX_FRAME_OFFSET); 459 460 skb_checksum_none_assert(skb); 461 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 462 napi_gro_receive(&bgmac->napi, skb); 463 handled++; 464 } while (0); 465 466 if (++ring->start >= BGMAC_RX_RING_SLOTS) 467 ring->start = 0; 468 469 if (handled >= weight) /* Should never be greater */ 470 break; 471 } 472 473 return handled; 474 } 475 476 /* Does ring support unaligned addressing? */ 477 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 478 struct bgmac_dma_ring *ring, 479 enum bgmac_dma_ring_type ring_type) 480 { 481 switch (ring_type) { 482 case BGMAC_DMA_RING_TX: 483 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 484 0xff0); 485 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 486 return true; 487 break; 488 case BGMAC_DMA_RING_RX: 489 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 490 0xff0); 491 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 492 return true; 493 break; 494 } 495 return false; 496 } 497 498 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 499 struct bgmac_dma_ring *ring) 500 { 501 struct device *dma_dev = bgmac->core->dma_dev; 502 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 503 struct bgmac_slot_info *slot; 504 int i; 505 506 for (i = 0; i < ring->num_slots; i++) { 507 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 508 509 slot = &ring->slots[i]; 510 dev_kfree_skb(slot->skb); 511 512 if (!slot->dma_addr) 513 continue; 514 515 if (slot->skb) 516 dma_unmap_single(dma_dev, slot->dma_addr, 517 len, DMA_TO_DEVICE); 518 else 519 dma_unmap_page(dma_dev, slot->dma_addr, 520 len, DMA_TO_DEVICE); 521 } 522 } 523 524 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 525 struct bgmac_dma_ring *ring) 526 { 527 struct device *dma_dev = bgmac->core->dma_dev; 528 struct bgmac_slot_info *slot; 529 int i; 530 531 for (i = 0; i < ring->num_slots; i++) { 532 slot = &ring->slots[i]; 533 if (!slot->buf) 534 continue; 535 536 if (slot->dma_addr) 537 dma_unmap_single(dma_dev, slot->dma_addr, 538 BGMAC_RX_BUF_SIZE, 539 DMA_FROM_DEVICE); 540 put_page(virt_to_head_page(slot->buf)); 541 } 542 } 543 544 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 545 struct bgmac_dma_ring *ring) 546 { 547 struct device *dma_dev = bgmac->core->dma_dev; 548 int size; 549 550 if (!ring->cpu_base) 551 return; 552 553 /* Free ring of descriptors */ 554 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 555 dma_free_coherent(dma_dev, size, ring->cpu_base, 556 ring->dma_base); 557 } 558 559 static void bgmac_dma_free(struct bgmac *bgmac) 560 { 561 int i; 562 563 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 564 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 565 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); 566 } 567 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 568 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 569 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); 570 } 571 } 572 573 static int bgmac_dma_alloc(struct bgmac *bgmac) 574 { 575 struct device *dma_dev = bgmac->core->dma_dev; 576 struct bgmac_dma_ring *ring; 577 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 578 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 579 int size; /* ring size: different for Tx and Rx */ 580 int err; 581 int i; 582 583 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 584 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 585 586 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 587 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 588 return -ENOTSUPP; 589 } 590 591 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 592 ring = &bgmac->tx_ring[i]; 593 ring->num_slots = BGMAC_TX_RING_SLOTS; 594 ring->mmio_base = ring_base[i]; 595 596 /* Alloc ring of descriptors */ 597 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 598 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 599 &ring->dma_base, 600 GFP_KERNEL); 601 if (!ring->cpu_base) { 602 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 603 ring->mmio_base); 604 goto err_dma_free; 605 } 606 607 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 608 BGMAC_DMA_RING_TX); 609 if (ring->unaligned) 610 ring->index_base = lower_32_bits(ring->dma_base); 611 else 612 ring->index_base = 0; 613 614 /* No need to alloc TX slots yet */ 615 } 616 617 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 618 int j; 619 620 ring = &bgmac->rx_ring[i]; 621 ring->num_slots = BGMAC_RX_RING_SLOTS; 622 ring->mmio_base = ring_base[i]; 623 624 /* Alloc ring of descriptors */ 625 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 626 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 627 &ring->dma_base, 628 GFP_KERNEL); 629 if (!ring->cpu_base) { 630 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 631 ring->mmio_base); 632 err = -ENOMEM; 633 goto err_dma_free; 634 } 635 636 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 637 BGMAC_DMA_RING_RX); 638 if (ring->unaligned) 639 ring->index_base = lower_32_bits(ring->dma_base); 640 else 641 ring->index_base = 0; 642 643 /* Alloc RX slots */ 644 for (j = 0; j < ring->num_slots; j++) { 645 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 646 if (err) { 647 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 648 goto err_dma_free; 649 } 650 } 651 } 652 653 return 0; 654 655 err_dma_free: 656 bgmac_dma_free(bgmac); 657 return -ENOMEM; 658 } 659 660 static void bgmac_dma_init(struct bgmac *bgmac) 661 { 662 struct bgmac_dma_ring *ring; 663 int i; 664 665 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 666 ring = &bgmac->tx_ring[i]; 667 668 if (!ring->unaligned) 669 bgmac_dma_tx_enable(bgmac, ring); 670 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 671 lower_32_bits(ring->dma_base)); 672 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 673 upper_32_bits(ring->dma_base)); 674 if (ring->unaligned) 675 bgmac_dma_tx_enable(bgmac, ring); 676 677 ring->start = 0; 678 ring->end = 0; /* Points the slot that should *not* be read */ 679 } 680 681 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 682 int j; 683 684 ring = &bgmac->rx_ring[i]; 685 686 if (!ring->unaligned) 687 bgmac_dma_rx_enable(bgmac, ring); 688 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 689 lower_32_bits(ring->dma_base)); 690 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 691 upper_32_bits(ring->dma_base)); 692 if (ring->unaligned) 693 bgmac_dma_rx_enable(bgmac, ring); 694 695 for (j = 0; j < ring->num_slots; j++) 696 bgmac_dma_rx_setup_desc(bgmac, ring, j); 697 698 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 699 ring->index_base + 700 ring->num_slots * sizeof(struct bgmac_dma_desc)); 701 702 ring->start = 0; 703 ring->end = 0; 704 } 705 } 706 707 /************************************************** 708 * PHY ops 709 **************************************************/ 710 711 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 712 { 713 struct bcma_device *core; 714 u16 phy_access_addr; 715 u16 phy_ctl_addr; 716 u32 tmp; 717 718 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 719 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 720 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 721 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 722 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 723 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 724 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 725 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 726 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 727 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 728 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 729 730 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 731 core = bgmac->core->bus->drv_gmac_cmn.core; 732 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 733 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 734 } else { 735 core = bgmac->core; 736 phy_access_addr = BGMAC_PHY_ACCESS; 737 phy_ctl_addr = BGMAC_PHY_CNTL; 738 } 739 740 tmp = bcma_read32(core, phy_ctl_addr); 741 tmp &= ~BGMAC_PC_EPA_MASK; 742 tmp |= phyaddr; 743 bcma_write32(core, phy_ctl_addr, tmp); 744 745 tmp = BGMAC_PA_START; 746 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 747 tmp |= reg << BGMAC_PA_REG_SHIFT; 748 bcma_write32(core, phy_access_addr, tmp); 749 750 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 751 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 752 phyaddr, reg); 753 return 0xffff; 754 } 755 756 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 757 } 758 759 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 760 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 761 { 762 struct bcma_device *core; 763 u16 phy_access_addr; 764 u16 phy_ctl_addr; 765 u32 tmp; 766 767 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 768 core = bgmac->core->bus->drv_gmac_cmn.core; 769 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 770 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 771 } else { 772 core = bgmac->core; 773 phy_access_addr = BGMAC_PHY_ACCESS; 774 phy_ctl_addr = BGMAC_PHY_CNTL; 775 } 776 777 tmp = bcma_read32(core, phy_ctl_addr); 778 tmp &= ~BGMAC_PC_EPA_MASK; 779 tmp |= phyaddr; 780 bcma_write32(core, phy_ctl_addr, tmp); 781 782 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 783 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 784 bgmac_warn(bgmac, "Error setting MDIO int\n"); 785 786 tmp = BGMAC_PA_START; 787 tmp |= BGMAC_PA_WRITE; 788 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 789 tmp |= reg << BGMAC_PA_REG_SHIFT; 790 tmp |= value; 791 bcma_write32(core, phy_access_addr, tmp); 792 793 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 794 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 795 phyaddr, reg); 796 return -ETIMEDOUT; 797 } 798 799 return 0; 800 } 801 802 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 803 static void bgmac_phy_init(struct bgmac *bgmac) 804 { 805 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 806 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 807 u8 i; 808 809 if (ci->id == BCMA_CHIP_ID_BCM5356) { 810 for (i = 0; i < 5; i++) { 811 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 812 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 813 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 814 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 815 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 816 } 817 } 818 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 819 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 820 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 821 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 822 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 823 for (i = 0; i < 5; i++) { 824 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 825 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 826 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 827 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 828 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 829 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 830 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 831 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 832 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 833 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 834 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 835 } 836 } 837 } 838 839 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 840 static void bgmac_phy_reset(struct bgmac *bgmac) 841 { 842 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 843 return; 844 845 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 846 udelay(100); 847 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 848 bgmac_err(bgmac, "PHY reset failed\n"); 849 bgmac_phy_init(bgmac); 850 } 851 852 /************************************************** 853 * Chip ops 854 **************************************************/ 855 856 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 857 * nothing to change? Try if after stabilizng driver. 858 */ 859 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 860 bool force) 861 { 862 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 863 u32 new_val = (cmdcfg & mask) | set; 864 865 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 866 udelay(2); 867 868 if (new_val != cmdcfg || force) 869 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 870 871 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 872 udelay(2); 873 } 874 875 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 876 { 877 u32 tmp; 878 879 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 880 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 881 tmp = (addr[4] << 8) | addr[5]; 882 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 883 } 884 885 static void bgmac_set_rx_mode(struct net_device *net_dev) 886 { 887 struct bgmac *bgmac = netdev_priv(net_dev); 888 889 if (net_dev->flags & IFF_PROMISC) 890 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 891 else 892 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 893 } 894 895 #if 0 /* We don't use that regs yet */ 896 static void bgmac_chip_stats_update(struct bgmac *bgmac) 897 { 898 int i; 899 900 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 901 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 902 bgmac->mib_tx_regs[i] = 903 bgmac_read(bgmac, 904 BGMAC_TX_GOOD_OCTETS + (i * 4)); 905 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 906 bgmac->mib_rx_regs[i] = 907 bgmac_read(bgmac, 908 BGMAC_RX_GOOD_OCTETS + (i * 4)); 909 } 910 911 /* TODO: what else? how to handle BCM4706? Specs are needed */ 912 } 913 #endif 914 915 static void bgmac_clear_mib(struct bgmac *bgmac) 916 { 917 int i; 918 919 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 920 return; 921 922 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 923 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 924 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 925 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 926 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 927 } 928 929 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 930 static void bgmac_mac_speed(struct bgmac *bgmac) 931 { 932 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 933 u32 set = 0; 934 935 switch (bgmac->mac_speed) { 936 case SPEED_10: 937 set |= BGMAC_CMDCFG_ES_10; 938 break; 939 case SPEED_100: 940 set |= BGMAC_CMDCFG_ES_100; 941 break; 942 case SPEED_1000: 943 set |= BGMAC_CMDCFG_ES_1000; 944 break; 945 case SPEED_2500: 946 set |= BGMAC_CMDCFG_ES_2500; 947 break; 948 default: 949 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 950 } 951 952 if (bgmac->mac_duplex == DUPLEX_HALF) 953 set |= BGMAC_CMDCFG_HD; 954 955 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 956 } 957 958 static void bgmac_miiconfig(struct bgmac *bgmac) 959 { 960 struct bcma_device *core = bgmac->core; 961 struct bcma_chipinfo *ci = &core->bus->chipinfo; 962 u8 imode; 963 964 if (ci->id == BCMA_CHIP_ID_BCM4707 || 965 ci->id == BCMA_CHIP_ID_BCM53018) { 966 bcma_awrite32(core, BCMA_IOCTL, 967 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 968 BGMAC_BCMA_IOCTL_SW_CLKEN); 969 bgmac->mac_speed = SPEED_2500; 970 bgmac->mac_duplex = DUPLEX_FULL; 971 bgmac_mac_speed(bgmac); 972 } else { 973 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 974 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 975 if (imode == 0 || imode == 1) { 976 bgmac->mac_speed = SPEED_100; 977 bgmac->mac_duplex = DUPLEX_FULL; 978 bgmac_mac_speed(bgmac); 979 } 980 } 981 } 982 983 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 984 static void bgmac_chip_reset(struct bgmac *bgmac) 985 { 986 struct bcma_device *core = bgmac->core; 987 struct bcma_bus *bus = core->bus; 988 struct bcma_chipinfo *ci = &bus->chipinfo; 989 u32 flags; 990 u32 iost; 991 int i; 992 993 if (bcma_core_is_enabled(core)) { 994 if (!bgmac->stats_grabbed) { 995 /* bgmac_chip_stats_update(bgmac); */ 996 bgmac->stats_grabbed = true; 997 } 998 999 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 1000 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 1001 1002 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1003 udelay(1); 1004 1005 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 1006 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 1007 1008 /* TODO: Clear software multicast filter list */ 1009 } 1010 1011 iost = bcma_aread32(core, BCMA_IOST); 1012 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1013 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1014 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 1015 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 1016 1017 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ 1018 if (ci->id != BCMA_CHIP_ID_BCM4707) { 1019 flags = 0; 1020 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 1021 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 1022 if (!bgmac->has_robosw) 1023 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 1024 } 1025 bcma_core_enable(core, flags); 1026 } 1027 1028 /* Request Misc PLL for corerev > 2 */ 1029 if (core->id.rev > 2 && 1030 ci->id != BCMA_CHIP_ID_BCM4707 && 1031 ci->id != BCMA_CHIP_ID_BCM53018) { 1032 bgmac_set(bgmac, BCMA_CLKCTLST, 1033 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 1034 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1035 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1036 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1037 1000); 1038 } 1039 1040 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1041 ci->id == BCMA_CHIP_ID_BCM4749 || 1042 ci->id == BCMA_CHIP_ID_BCM53572) { 1043 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 1044 u8 et_swtype = 0; 1045 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 1046 BGMAC_CHIPCTL_1_IF_TYPE_MII; 1047 char buf[4]; 1048 1049 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 1050 if (kstrtou8(buf, 0, &et_swtype)) 1051 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 1052 buf); 1053 et_swtype &= 0x0f; 1054 et_swtype <<= 4; 1055 sw_type = et_swtype; 1056 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 1057 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 1058 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1059 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1060 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 1061 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 1062 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 1063 } 1064 bcma_chipco_chipctl_maskset(cc, 1, 1065 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 1066 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 1067 sw_type); 1068 } 1069 1070 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 1071 bcma_awrite32(core, BCMA_IOCTL, 1072 bcma_aread32(core, BCMA_IOCTL) & 1073 ~BGMAC_BCMA_IOCTL_SW_RESET); 1074 1075 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1076 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1077 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1078 * be keps until taking MAC out of the reset. 1079 */ 1080 bgmac_cmdcfg_maskset(bgmac, 1081 ~(BGMAC_CMDCFG_TE | 1082 BGMAC_CMDCFG_RE | 1083 BGMAC_CMDCFG_RPI | 1084 BGMAC_CMDCFG_TAI | 1085 BGMAC_CMDCFG_HD | 1086 BGMAC_CMDCFG_ML | 1087 BGMAC_CMDCFG_CFE | 1088 BGMAC_CMDCFG_RL | 1089 BGMAC_CMDCFG_RED | 1090 BGMAC_CMDCFG_PE | 1091 BGMAC_CMDCFG_TPI | 1092 BGMAC_CMDCFG_PAD_EN | 1093 BGMAC_CMDCFG_PF), 1094 BGMAC_CMDCFG_PROM | 1095 BGMAC_CMDCFG_NLC | 1096 BGMAC_CMDCFG_CFE | 1097 BGMAC_CMDCFG_SR(core->id.rev), 1098 false); 1099 bgmac->mac_speed = SPEED_UNKNOWN; 1100 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1101 1102 bgmac_clear_mib(bgmac); 1103 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1104 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1105 BCMA_GMAC_CMN_PC_MTE); 1106 else 1107 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1108 bgmac_miiconfig(bgmac); 1109 bgmac_phy_init(bgmac); 1110 1111 netdev_reset_queue(bgmac->net_dev); 1112 } 1113 1114 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1115 { 1116 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1117 } 1118 1119 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1120 { 1121 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1122 bgmac_read(bgmac, BGMAC_INT_MASK); 1123 } 1124 1125 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1126 static void bgmac_enable(struct bgmac *bgmac) 1127 { 1128 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1129 u32 cmdcfg; 1130 u32 mode; 1131 u32 rxq_ctl; 1132 u32 fl_ctl; 1133 u16 bp_clk; 1134 u8 mdp; 1135 1136 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1137 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1138 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1139 udelay(2); 1140 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1141 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1142 1143 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1144 BGMAC_DS_MM_SHIFT; 1145 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1146 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1147 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1148 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1149 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1150 1151 switch (ci->id) { 1152 case BCMA_CHIP_ID_BCM5357: 1153 case BCMA_CHIP_ID_BCM4749: 1154 case BCMA_CHIP_ID_BCM53572: 1155 case BCMA_CHIP_ID_BCM4716: 1156 case BCMA_CHIP_ID_BCM47162: 1157 fl_ctl = 0x03cb04cb; 1158 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1159 ci->id == BCMA_CHIP_ID_BCM4749 || 1160 ci->id == BCMA_CHIP_ID_BCM53572) 1161 fl_ctl = 0x2300e1; 1162 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1163 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1164 break; 1165 } 1166 1167 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1168 ci->id != BCMA_CHIP_ID_BCM53018) { 1169 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1170 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1171 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1172 1000000; 1173 mdp = (bp_clk * 128 / 1000) - 3; 1174 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1175 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1176 } 1177 } 1178 1179 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1180 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1181 { 1182 struct bgmac_dma_ring *ring; 1183 int i; 1184 1185 /* 1 interrupt per received frame */ 1186 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1187 1188 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1189 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1190 1191 bgmac_set_rx_mode(bgmac->net_dev); 1192 1193 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1194 1195 if (bgmac->loopback) 1196 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1197 else 1198 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1199 1200 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1201 1202 if (full_init) { 1203 bgmac_dma_init(bgmac); 1204 if (1) /* FIXME: is there any case we don't want IRQs? */ 1205 bgmac_chip_intrs_on(bgmac); 1206 } else { 1207 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1208 ring = &bgmac->rx_ring[i]; 1209 bgmac_dma_rx_enable(bgmac, ring); 1210 } 1211 } 1212 1213 bgmac_enable(bgmac); 1214 } 1215 1216 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1217 { 1218 struct bgmac *bgmac = netdev_priv(dev_id); 1219 1220 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1221 int_status &= bgmac->int_mask; 1222 1223 if (!int_status) 1224 return IRQ_NONE; 1225 1226 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1227 if (int_status) 1228 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); 1229 1230 /* Disable new interrupts until handling existing ones */ 1231 bgmac_chip_intrs_off(bgmac); 1232 1233 napi_schedule(&bgmac->napi); 1234 1235 return IRQ_HANDLED; 1236 } 1237 1238 static int bgmac_poll(struct napi_struct *napi, int weight) 1239 { 1240 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1241 int handled = 0; 1242 1243 /* Ack */ 1244 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1245 1246 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1247 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1248 1249 /* Poll again if more events arrived in the meantime */ 1250 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1251 return handled; 1252 1253 if (handled < weight) { 1254 napi_complete(napi); 1255 bgmac_chip_intrs_on(bgmac); 1256 } 1257 1258 return handled; 1259 } 1260 1261 /************************************************** 1262 * net_device_ops 1263 **************************************************/ 1264 1265 static int bgmac_open(struct net_device *net_dev) 1266 { 1267 struct bgmac *bgmac = netdev_priv(net_dev); 1268 int err = 0; 1269 1270 bgmac_chip_reset(bgmac); 1271 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1272 bgmac_chip_init(bgmac, true); 1273 1274 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1275 KBUILD_MODNAME, net_dev); 1276 if (err < 0) { 1277 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1278 goto err_out; 1279 } 1280 napi_enable(&bgmac->napi); 1281 1282 phy_start(bgmac->phy_dev); 1283 1284 netif_carrier_on(net_dev); 1285 1286 err_out: 1287 return err; 1288 } 1289 1290 static int bgmac_stop(struct net_device *net_dev) 1291 { 1292 struct bgmac *bgmac = netdev_priv(net_dev); 1293 1294 netif_carrier_off(net_dev); 1295 1296 phy_stop(bgmac->phy_dev); 1297 1298 napi_disable(&bgmac->napi); 1299 bgmac_chip_intrs_off(bgmac); 1300 free_irq(bgmac->core->irq, net_dev); 1301 1302 bgmac_chip_reset(bgmac); 1303 1304 return 0; 1305 } 1306 1307 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1308 struct net_device *net_dev) 1309 { 1310 struct bgmac *bgmac = netdev_priv(net_dev); 1311 struct bgmac_dma_ring *ring; 1312 1313 /* No QOS support yet */ 1314 ring = &bgmac->tx_ring[0]; 1315 return bgmac_dma_tx_add(bgmac, ring, skb); 1316 } 1317 1318 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1319 { 1320 struct bgmac *bgmac = netdev_priv(net_dev); 1321 int ret; 1322 1323 ret = eth_prepare_mac_addr_change(net_dev, addr); 1324 if (ret < 0) 1325 return ret; 1326 bgmac_write_mac_address(bgmac, (u8 *)addr); 1327 eth_commit_mac_addr_change(net_dev, addr); 1328 return 0; 1329 } 1330 1331 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1332 { 1333 struct bgmac *bgmac = netdev_priv(net_dev); 1334 1335 if (!netif_running(net_dev)) 1336 return -EINVAL; 1337 1338 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1339 } 1340 1341 static const struct net_device_ops bgmac_netdev_ops = { 1342 .ndo_open = bgmac_open, 1343 .ndo_stop = bgmac_stop, 1344 .ndo_start_xmit = bgmac_start_xmit, 1345 .ndo_set_rx_mode = bgmac_set_rx_mode, 1346 .ndo_set_mac_address = bgmac_set_mac_address, 1347 .ndo_validate_addr = eth_validate_addr, 1348 .ndo_do_ioctl = bgmac_ioctl, 1349 }; 1350 1351 /************************************************** 1352 * ethtool_ops 1353 **************************************************/ 1354 1355 static int bgmac_get_settings(struct net_device *net_dev, 1356 struct ethtool_cmd *cmd) 1357 { 1358 struct bgmac *bgmac = netdev_priv(net_dev); 1359 1360 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1361 } 1362 1363 static int bgmac_set_settings(struct net_device *net_dev, 1364 struct ethtool_cmd *cmd) 1365 { 1366 struct bgmac *bgmac = netdev_priv(net_dev); 1367 1368 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1369 } 1370 1371 static void bgmac_get_drvinfo(struct net_device *net_dev, 1372 struct ethtool_drvinfo *info) 1373 { 1374 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1375 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1376 } 1377 1378 static const struct ethtool_ops bgmac_ethtool_ops = { 1379 .get_settings = bgmac_get_settings, 1380 .set_settings = bgmac_set_settings, 1381 .get_drvinfo = bgmac_get_drvinfo, 1382 }; 1383 1384 /************************************************** 1385 * MII 1386 **************************************************/ 1387 1388 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1389 { 1390 return bgmac_phy_read(bus->priv, mii_id, regnum); 1391 } 1392 1393 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1394 u16 value) 1395 { 1396 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1397 } 1398 1399 static void bgmac_adjust_link(struct net_device *net_dev) 1400 { 1401 struct bgmac *bgmac = netdev_priv(net_dev); 1402 struct phy_device *phy_dev = bgmac->phy_dev; 1403 bool update = false; 1404 1405 if (phy_dev->link) { 1406 if (phy_dev->speed != bgmac->mac_speed) { 1407 bgmac->mac_speed = phy_dev->speed; 1408 update = true; 1409 } 1410 1411 if (phy_dev->duplex != bgmac->mac_duplex) { 1412 bgmac->mac_duplex = phy_dev->duplex; 1413 update = true; 1414 } 1415 } 1416 1417 if (update) { 1418 bgmac_mac_speed(bgmac); 1419 phy_print_status(phy_dev); 1420 } 1421 } 1422 1423 static int bgmac_fixed_phy_register(struct bgmac *bgmac) 1424 { 1425 struct fixed_phy_status fphy_status = { 1426 .link = 1, 1427 .speed = SPEED_1000, 1428 .duplex = DUPLEX_FULL, 1429 }; 1430 struct phy_device *phy_dev; 1431 int err; 1432 1433 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 1434 if (!phy_dev || IS_ERR(phy_dev)) { 1435 bgmac_err(bgmac, "Failed to register fixed PHY device\n"); 1436 return -ENODEV; 1437 } 1438 1439 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1440 PHY_INTERFACE_MODE_MII); 1441 if (err) { 1442 bgmac_err(bgmac, "Connecting PHY failed\n"); 1443 return err; 1444 } 1445 1446 bgmac->phy_dev = phy_dev; 1447 1448 return err; 1449 } 1450 1451 static int bgmac_mii_register(struct bgmac *bgmac) 1452 { 1453 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1454 struct mii_bus *mii_bus; 1455 struct phy_device *phy_dev; 1456 char bus_id[MII_BUS_ID_SIZE + 3]; 1457 int i, err = 0; 1458 1459 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1460 ci->id == BCMA_CHIP_ID_BCM53018) 1461 return bgmac_fixed_phy_register(bgmac); 1462 1463 mii_bus = mdiobus_alloc(); 1464 if (!mii_bus) 1465 return -ENOMEM; 1466 1467 mii_bus->name = "bgmac mii bus"; 1468 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1469 bgmac->core->core_unit); 1470 mii_bus->priv = bgmac; 1471 mii_bus->read = bgmac_mii_read; 1472 mii_bus->write = bgmac_mii_write; 1473 mii_bus->parent = &bgmac->core->dev; 1474 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1475 1476 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 1477 if (!mii_bus->irq) { 1478 err = -ENOMEM; 1479 goto err_free_bus; 1480 } 1481 for (i = 0; i < PHY_MAX_ADDR; i++) 1482 mii_bus->irq[i] = PHY_POLL; 1483 1484 err = mdiobus_register(mii_bus); 1485 if (err) { 1486 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1487 goto err_free_irq; 1488 } 1489 1490 bgmac->mii_bus = mii_bus; 1491 1492 /* Connect to the PHY */ 1493 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1494 bgmac->phyaddr); 1495 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1496 PHY_INTERFACE_MODE_MII); 1497 if (IS_ERR(phy_dev)) { 1498 bgmac_err(bgmac, "PHY connecton failed\n"); 1499 err = PTR_ERR(phy_dev); 1500 goto err_unregister_bus; 1501 } 1502 bgmac->phy_dev = phy_dev; 1503 1504 return err; 1505 1506 err_unregister_bus: 1507 mdiobus_unregister(mii_bus); 1508 err_free_irq: 1509 kfree(mii_bus->irq); 1510 err_free_bus: 1511 mdiobus_free(mii_bus); 1512 return err; 1513 } 1514 1515 static void bgmac_mii_unregister(struct bgmac *bgmac) 1516 { 1517 struct mii_bus *mii_bus = bgmac->mii_bus; 1518 1519 mdiobus_unregister(mii_bus); 1520 kfree(mii_bus->irq); 1521 mdiobus_free(mii_bus); 1522 } 1523 1524 /************************************************** 1525 * BCMA bus ops 1526 **************************************************/ 1527 1528 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1529 static int bgmac_probe(struct bcma_device *core) 1530 { 1531 struct bcma_chipinfo *ci = &core->bus->chipinfo; 1532 struct net_device *net_dev; 1533 struct bgmac *bgmac; 1534 struct ssb_sprom *sprom = &core->bus->sprom; 1535 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1536 int err; 1537 1538 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1539 if (core->core_unit > 1) { 1540 pr_err("Unsupported core_unit %d\n", core->core_unit); 1541 return -ENOTSUPP; 1542 } 1543 1544 if (!is_valid_ether_addr(mac)) { 1545 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1546 eth_random_addr(mac); 1547 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1548 } 1549 1550 /* Allocation and references */ 1551 net_dev = alloc_etherdev(sizeof(*bgmac)); 1552 if (!net_dev) 1553 return -ENOMEM; 1554 net_dev->netdev_ops = &bgmac_netdev_ops; 1555 net_dev->irq = core->irq; 1556 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1557 bgmac = netdev_priv(net_dev); 1558 bgmac->net_dev = net_dev; 1559 bgmac->core = core; 1560 bcma_set_drvdata(core, bgmac); 1561 1562 /* Defaults */ 1563 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1564 1565 /* On BCM4706 we need common core to access PHY */ 1566 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1567 !core->bus->drv_gmac_cmn.core) { 1568 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1569 err = -ENODEV; 1570 goto err_netdev_free; 1571 } 1572 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1573 1574 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1575 sprom->et0phyaddr; 1576 bgmac->phyaddr &= BGMAC_PHY_MASK; 1577 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1578 bgmac_err(bgmac, "No PHY found\n"); 1579 err = -ENODEV; 1580 goto err_netdev_free; 1581 } 1582 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1583 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1584 1585 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1586 bgmac_err(bgmac, "PCI setup not implemented\n"); 1587 err = -ENOTSUPP; 1588 goto err_netdev_free; 1589 } 1590 1591 bgmac_chip_reset(bgmac); 1592 1593 /* For Northstar, we have to take all GMAC core out of reset */ 1594 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1595 ci->id == BCMA_CHIP_ID_BCM53018) { 1596 struct bcma_device *ns_core; 1597 int ns_gmac; 1598 1599 /* Northstar has 4 GMAC cores */ 1600 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1601 /* As Northstar requirement, we have to reset all GMACs 1602 * before accessing one. bgmac_chip_reset() call 1603 * bcma_core_enable() for this core. Then the other 1604 * three GMACs didn't reset. We do it here. 1605 */ 1606 ns_core = bcma_find_core_unit(core->bus, 1607 BCMA_CORE_MAC_GBIT, 1608 ns_gmac); 1609 if (ns_core && !bcma_core_is_enabled(ns_core)) 1610 bcma_core_enable(ns_core, 0); 1611 } 1612 } 1613 1614 err = bgmac_dma_alloc(bgmac); 1615 if (err) { 1616 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1617 goto err_netdev_free; 1618 } 1619 1620 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1621 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1622 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1623 1624 /* TODO: reset the external phy. Specs are needed */ 1625 bgmac_phy_reset(bgmac); 1626 1627 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1628 BGMAC_BFL_ENETROBO); 1629 if (bgmac->has_robosw) 1630 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1631 1632 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1633 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1634 1635 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1636 1637 err = bgmac_mii_register(bgmac); 1638 if (err) { 1639 bgmac_err(bgmac, "Cannot register MDIO\n"); 1640 goto err_dma_free; 1641 } 1642 1643 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1644 net_dev->hw_features = net_dev->features; 1645 net_dev->vlan_features = net_dev->features; 1646 1647 err = register_netdev(bgmac->net_dev); 1648 if (err) { 1649 bgmac_err(bgmac, "Cannot register net device\n"); 1650 goto err_mii_unregister; 1651 } 1652 1653 netif_carrier_off(net_dev); 1654 1655 return 0; 1656 1657 err_mii_unregister: 1658 bgmac_mii_unregister(bgmac); 1659 err_dma_free: 1660 bgmac_dma_free(bgmac); 1661 1662 err_netdev_free: 1663 bcma_set_drvdata(core, NULL); 1664 free_netdev(net_dev); 1665 1666 return err; 1667 } 1668 1669 static void bgmac_remove(struct bcma_device *core) 1670 { 1671 struct bgmac *bgmac = bcma_get_drvdata(core); 1672 1673 unregister_netdev(bgmac->net_dev); 1674 bgmac_mii_unregister(bgmac); 1675 netif_napi_del(&bgmac->napi); 1676 bgmac_dma_free(bgmac); 1677 bcma_set_drvdata(core, NULL); 1678 free_netdev(bgmac->net_dev); 1679 } 1680 1681 static struct bcma_driver bgmac_bcma_driver = { 1682 .name = KBUILD_MODNAME, 1683 .id_table = bgmac_bcma_tbl, 1684 .probe = bgmac_probe, 1685 .remove = bgmac_remove, 1686 }; 1687 1688 static int __init bgmac_init(void) 1689 { 1690 int err; 1691 1692 err = bcma_driver_register(&bgmac_bcma_driver); 1693 if (err) 1694 return err; 1695 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1696 1697 return 0; 1698 } 1699 1700 static void __exit bgmac_exit(void) 1701 { 1702 bcma_driver_unregister(&bgmac_bcma_driver); 1703 } 1704 1705 module_init(bgmac_init) 1706 module_exit(bgmac_exit) 1707 1708 MODULE_AUTHOR("Rafał Miłecki"); 1709 MODULE_LICENSE("GPL"); 1710