1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <bcm47xx_nvram.h> 20 21 static const struct bcma_device_id bgmac_bcma_tbl[] = { 22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORETABLE_END 25 }; 26 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 27 28 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 29 u32 value, int timeout) 30 { 31 u32 val; 32 int i; 33 34 for (i = 0; i < timeout / 10; i++) { 35 val = bcma_read32(core, reg); 36 if ((val & mask) == value) 37 return true; 38 udelay(10); 39 } 40 pr_err("Timeout waiting for reg 0x%X\n", reg); 41 return false; 42 } 43 44 /************************************************** 45 * DMA 46 **************************************************/ 47 48 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 49 { 50 u32 val; 51 int i; 52 53 if (!ring->mmio_base) 54 return; 55 56 /* Suspend DMA TX ring first. 57 * bgmac_wait_value doesn't support waiting for any of few values, so 58 * implement whole loop here. 59 */ 60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 61 BGMAC_DMA_TX_SUSPEND); 62 for (i = 0; i < 10000 / 10; i++) { 63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 64 val &= BGMAC_DMA_TX_STAT; 65 if (val == BGMAC_DMA_TX_STAT_DISABLED || 66 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 67 val == BGMAC_DMA_TX_STAT_STOPPED) { 68 i = 0; 69 break; 70 } 71 udelay(10); 72 } 73 if (i) 74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 75 ring->mmio_base, val); 76 77 /* Remove SUSPEND bit */ 78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 79 if (!bgmac_wait_value(bgmac->core, 80 ring->mmio_base + BGMAC_DMA_TX_STATUS, 81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 82 10000)) { 83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 84 ring->mmio_base); 85 udelay(300); 86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 89 ring->mmio_base); 90 } 91 } 92 93 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 94 struct bgmac_dma_ring *ring) 95 { 96 u32 ctl; 97 98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 99 if (bgmac->core->id.rev >= 4) { 100 ctl &= ~BGMAC_DMA_TX_BL_MASK; 101 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 102 103 ctl &= ~BGMAC_DMA_TX_MR_MASK; 104 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 105 106 ctl &= ~BGMAC_DMA_TX_PC_MASK; 107 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 108 109 ctl &= ~BGMAC_DMA_TX_PT_MASK; 110 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 111 } 112 ctl |= BGMAC_DMA_TX_ENABLE; 113 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 114 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 115 } 116 117 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 118 struct bgmac_dma_ring *ring, 119 struct sk_buff *skb) 120 { 121 struct device *dma_dev = bgmac->core->dma_dev; 122 struct net_device *net_dev = bgmac->net_dev; 123 struct bgmac_dma_desc *dma_desc; 124 struct bgmac_slot_info *slot; 125 u32 ctl0, ctl1; 126 int free_slots; 127 128 if (skb->len > BGMAC_DESC_CTL1_LEN) { 129 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 130 goto err_stop_drop; 131 } 132 133 if (ring->start <= ring->end) 134 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; 135 else 136 free_slots = ring->start - ring->end; 137 if (free_slots == 1) { 138 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 139 netif_stop_queue(net_dev); 140 return NETDEV_TX_BUSY; 141 } 142 143 slot = &ring->slots[ring->end]; 144 slot->skb = skb; 145 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, 146 DMA_TO_DEVICE); 147 if (dma_mapping_error(dma_dev, slot->dma_addr)) { 148 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 149 ring->mmio_base); 150 goto err_stop_drop; 151 } 152 153 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; 154 if (ring->end == ring->num_slots - 1) 155 ctl0 |= BGMAC_DESC_CTL0_EOT; 156 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; 157 158 dma_desc = ring->cpu_base; 159 dma_desc += ring->end; 160 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 161 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 162 dma_desc->ctl0 = cpu_to_le32(ctl0); 163 dma_desc->ctl1 = cpu_to_le32(ctl1); 164 165 netdev_sent_queue(net_dev, skb->len); 166 167 wmb(); 168 169 /* Increase ring->end to point empty slot. We tell hardware the first 170 * slot it should *not* read. 171 */ 172 if (++ring->end >= BGMAC_TX_RING_SLOTS) 173 ring->end = 0; 174 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 175 ring->index_base + 176 ring->end * sizeof(struct bgmac_dma_desc)); 177 178 /* Always keep one slot free to allow detecting bugged calls. */ 179 if (--free_slots == 1) 180 netif_stop_queue(net_dev); 181 182 return NETDEV_TX_OK; 183 184 err_stop_drop: 185 netif_stop_queue(net_dev); 186 dev_kfree_skb(skb); 187 return NETDEV_TX_OK; 188 } 189 190 /* Free transmitted packets */ 191 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 192 { 193 struct device *dma_dev = bgmac->core->dma_dev; 194 int empty_slot; 195 bool freed = false; 196 unsigned bytes_compl = 0, pkts_compl = 0; 197 198 /* The last slot that hardware didn't consume yet */ 199 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 200 empty_slot &= BGMAC_DMA_TX_STATDPTR; 201 empty_slot -= ring->index_base; 202 empty_slot &= BGMAC_DMA_TX_STATDPTR; 203 empty_slot /= sizeof(struct bgmac_dma_desc); 204 205 while (ring->start != empty_slot) { 206 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 207 208 if (slot->skb) { 209 /* Unmap no longer used buffer */ 210 dma_unmap_single(dma_dev, slot->dma_addr, 211 slot->skb->len, DMA_TO_DEVICE); 212 slot->dma_addr = 0; 213 214 bytes_compl += slot->skb->len; 215 pkts_compl++; 216 217 /* Free memory! :) */ 218 dev_kfree_skb(slot->skb); 219 slot->skb = NULL; 220 } else { 221 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", 222 ring->start, ring->end); 223 } 224 225 if (++ring->start >= BGMAC_TX_RING_SLOTS) 226 ring->start = 0; 227 freed = true; 228 } 229 230 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 231 232 if (freed && netif_queue_stopped(bgmac->net_dev)) 233 netif_wake_queue(bgmac->net_dev); 234 } 235 236 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 237 { 238 if (!ring->mmio_base) 239 return; 240 241 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 242 if (!bgmac_wait_value(bgmac->core, 243 ring->mmio_base + BGMAC_DMA_RX_STATUS, 244 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 245 10000)) 246 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 247 ring->mmio_base); 248 } 249 250 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 251 struct bgmac_dma_ring *ring) 252 { 253 u32 ctl; 254 255 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 256 if (bgmac->core->id.rev >= 4) { 257 ctl &= ~BGMAC_DMA_RX_BL_MASK; 258 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 259 260 ctl &= ~BGMAC_DMA_RX_PC_MASK; 261 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 262 263 ctl &= ~BGMAC_DMA_RX_PT_MASK; 264 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 265 } 266 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 267 ctl |= BGMAC_DMA_RX_ENABLE; 268 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 269 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 270 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 271 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 272 } 273 274 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 275 struct bgmac_slot_info *slot) 276 { 277 struct device *dma_dev = bgmac->core->dma_dev; 278 struct sk_buff *skb; 279 dma_addr_t dma_addr; 280 struct bgmac_rx_header *rx; 281 282 /* Alloc skb */ 283 skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); 284 if (!skb) 285 return -ENOMEM; 286 287 /* Poison - if everything goes fine, hardware will overwrite it */ 288 rx = (struct bgmac_rx_header *)skb->data; 289 rx->len = cpu_to_le16(0xdead); 290 rx->flags = cpu_to_le16(0xbeef); 291 292 /* Map skb for the DMA */ 293 dma_addr = dma_map_single(dma_dev, skb->data, 294 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 295 if (dma_mapping_error(dma_dev, dma_addr)) { 296 bgmac_err(bgmac, "DMA mapping error\n"); 297 dev_kfree_skb(skb); 298 return -ENOMEM; 299 } 300 301 /* Update the slot */ 302 slot->skb = skb; 303 slot->dma_addr = dma_addr; 304 305 if (slot->dma_addr & 0xC0000000) 306 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 307 308 return 0; 309 } 310 311 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 312 struct bgmac_dma_ring *ring, int desc_idx) 313 { 314 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 315 u32 ctl0 = 0, ctl1 = 0; 316 317 if (desc_idx == ring->num_slots - 1) 318 ctl0 |= BGMAC_DESC_CTL0_EOT; 319 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 320 /* Is there any BGMAC device that requires extension? */ 321 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 322 * B43_DMA64_DCTL1_ADDREXT_MASK; 323 */ 324 325 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 326 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 327 dma_desc->ctl0 = cpu_to_le32(ctl0); 328 dma_desc->ctl1 = cpu_to_le32(ctl1); 329 } 330 331 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 332 int weight) 333 { 334 u32 end_slot; 335 int handled = 0; 336 337 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 338 end_slot &= BGMAC_DMA_RX_STATDPTR; 339 end_slot -= ring->index_base; 340 end_slot &= BGMAC_DMA_RX_STATDPTR; 341 end_slot /= sizeof(struct bgmac_dma_desc); 342 343 ring->end = end_slot; 344 345 while (ring->start != ring->end) { 346 struct device *dma_dev = bgmac->core->dma_dev; 347 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 348 struct sk_buff *skb = slot->skb; 349 struct bgmac_rx_header *rx; 350 u16 len, flags; 351 352 /* Unmap buffer to make it accessible to the CPU */ 353 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, 354 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 355 356 /* Get info from the header */ 357 rx = (struct bgmac_rx_header *)skb->data; 358 len = le16_to_cpu(rx->len); 359 flags = le16_to_cpu(rx->flags); 360 361 do { 362 dma_addr_t old_dma_addr = slot->dma_addr; 363 int err; 364 365 /* Check for poison and drop or pass the packet */ 366 if (len == 0xdead && flags == 0xbeef) { 367 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 368 ring->start); 369 dma_sync_single_for_device(dma_dev, 370 slot->dma_addr, 371 BGMAC_RX_BUF_SIZE, 372 DMA_FROM_DEVICE); 373 break; 374 } 375 376 /* Omit CRC. */ 377 len -= ETH_FCS_LEN; 378 379 /* Prepare new skb as replacement */ 380 err = bgmac_dma_rx_skb_for_slot(bgmac, slot); 381 if (err) { 382 /* Poison the old skb */ 383 rx->len = cpu_to_le16(0xdead); 384 rx->flags = cpu_to_le16(0xbeef); 385 386 dma_sync_single_for_device(dma_dev, 387 slot->dma_addr, 388 BGMAC_RX_BUF_SIZE, 389 DMA_FROM_DEVICE); 390 break; 391 } 392 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 393 394 /* Unmap old skb, we'll pass it to the netfif */ 395 dma_unmap_single(dma_dev, old_dma_addr, 396 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 397 398 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); 399 skb_pull(skb, BGMAC_RX_FRAME_OFFSET); 400 401 skb_checksum_none_assert(skb); 402 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 403 netif_receive_skb(skb); 404 handled++; 405 } while (0); 406 407 if (++ring->start >= BGMAC_RX_RING_SLOTS) 408 ring->start = 0; 409 410 if (handled >= weight) /* Should never be greater */ 411 break; 412 } 413 414 return handled; 415 } 416 417 /* Does ring support unaligned addressing? */ 418 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 419 struct bgmac_dma_ring *ring, 420 enum bgmac_dma_ring_type ring_type) 421 { 422 switch (ring_type) { 423 case BGMAC_DMA_RING_TX: 424 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 425 0xff0); 426 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 427 return true; 428 break; 429 case BGMAC_DMA_RING_RX: 430 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 431 0xff0); 432 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 433 return true; 434 break; 435 } 436 return false; 437 } 438 439 static void bgmac_dma_ring_free(struct bgmac *bgmac, 440 struct bgmac_dma_ring *ring) 441 { 442 struct device *dma_dev = bgmac->core->dma_dev; 443 struct bgmac_slot_info *slot; 444 int size; 445 int i; 446 447 for (i = 0; i < ring->num_slots; i++) { 448 slot = &ring->slots[i]; 449 if (slot->skb) { 450 if (slot->dma_addr) 451 dma_unmap_single(dma_dev, slot->dma_addr, 452 slot->skb->len, DMA_TO_DEVICE); 453 dev_kfree_skb(slot->skb); 454 } 455 } 456 457 if (ring->cpu_base) { 458 /* Free ring of descriptors */ 459 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 460 dma_free_coherent(dma_dev, size, ring->cpu_base, 461 ring->dma_base); 462 } 463 } 464 465 static void bgmac_dma_free(struct bgmac *bgmac) 466 { 467 int i; 468 469 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 470 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]); 471 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 472 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]); 473 } 474 475 static int bgmac_dma_alloc(struct bgmac *bgmac) 476 { 477 struct device *dma_dev = bgmac->core->dma_dev; 478 struct bgmac_dma_ring *ring; 479 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 480 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 481 int size; /* ring size: different for Tx and Rx */ 482 int err; 483 int i; 484 485 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 486 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 487 488 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 489 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 490 return -ENOTSUPP; 491 } 492 493 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 494 ring = &bgmac->tx_ring[i]; 495 ring->num_slots = BGMAC_TX_RING_SLOTS; 496 ring->mmio_base = ring_base[i]; 497 498 /* Alloc ring of descriptors */ 499 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 500 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 501 &ring->dma_base, 502 GFP_KERNEL); 503 if (!ring->cpu_base) { 504 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 505 ring->mmio_base); 506 goto err_dma_free; 507 } 508 if (ring->dma_base & 0xC0000000) 509 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 510 511 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 512 BGMAC_DMA_RING_TX); 513 if (ring->unaligned) 514 ring->index_base = lower_32_bits(ring->dma_base); 515 else 516 ring->index_base = 0; 517 518 /* No need to alloc TX slots yet */ 519 } 520 521 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 522 int j; 523 524 ring = &bgmac->rx_ring[i]; 525 ring->num_slots = BGMAC_RX_RING_SLOTS; 526 ring->mmio_base = ring_base[i]; 527 528 /* Alloc ring of descriptors */ 529 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 530 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 531 &ring->dma_base, 532 GFP_KERNEL); 533 if (!ring->cpu_base) { 534 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 535 ring->mmio_base); 536 err = -ENOMEM; 537 goto err_dma_free; 538 } 539 if (ring->dma_base & 0xC0000000) 540 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 541 542 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 543 BGMAC_DMA_RING_RX); 544 if (ring->unaligned) 545 ring->index_base = lower_32_bits(ring->dma_base); 546 else 547 ring->index_base = 0; 548 549 /* Alloc RX slots */ 550 for (j = 0; j < ring->num_slots; j++) { 551 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 552 if (err) { 553 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 554 goto err_dma_free; 555 } 556 } 557 } 558 559 return 0; 560 561 err_dma_free: 562 bgmac_dma_free(bgmac); 563 return -ENOMEM; 564 } 565 566 static void bgmac_dma_init(struct bgmac *bgmac) 567 { 568 struct bgmac_dma_ring *ring; 569 int i; 570 571 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 572 ring = &bgmac->tx_ring[i]; 573 574 if (!ring->unaligned) 575 bgmac_dma_tx_enable(bgmac, ring); 576 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 577 lower_32_bits(ring->dma_base)); 578 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 579 upper_32_bits(ring->dma_base)); 580 if (ring->unaligned) 581 bgmac_dma_tx_enable(bgmac, ring); 582 583 ring->start = 0; 584 ring->end = 0; /* Points the slot that should *not* be read */ 585 } 586 587 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 588 int j; 589 590 ring = &bgmac->rx_ring[i]; 591 592 if (!ring->unaligned) 593 bgmac_dma_rx_enable(bgmac, ring); 594 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 595 lower_32_bits(ring->dma_base)); 596 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 597 upper_32_bits(ring->dma_base)); 598 if (ring->unaligned) 599 bgmac_dma_rx_enable(bgmac, ring); 600 601 for (j = 0; j < ring->num_slots; j++) 602 bgmac_dma_rx_setup_desc(bgmac, ring, j); 603 604 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 605 ring->index_base + 606 ring->num_slots * sizeof(struct bgmac_dma_desc)); 607 608 ring->start = 0; 609 ring->end = 0; 610 } 611 } 612 613 /************************************************** 614 * PHY ops 615 **************************************************/ 616 617 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 618 { 619 struct bcma_device *core; 620 u16 phy_access_addr; 621 u16 phy_ctl_addr; 622 u32 tmp; 623 624 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 625 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 626 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 627 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 628 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 629 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 630 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 631 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 632 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 633 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 634 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 635 636 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 637 core = bgmac->core->bus->drv_gmac_cmn.core; 638 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 639 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 640 } else { 641 core = bgmac->core; 642 phy_access_addr = BGMAC_PHY_ACCESS; 643 phy_ctl_addr = BGMAC_PHY_CNTL; 644 } 645 646 tmp = bcma_read32(core, phy_ctl_addr); 647 tmp &= ~BGMAC_PC_EPA_MASK; 648 tmp |= phyaddr; 649 bcma_write32(core, phy_ctl_addr, tmp); 650 651 tmp = BGMAC_PA_START; 652 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 653 tmp |= reg << BGMAC_PA_REG_SHIFT; 654 bcma_write32(core, phy_access_addr, tmp); 655 656 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 657 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 658 phyaddr, reg); 659 return 0xffff; 660 } 661 662 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 663 } 664 665 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 666 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 667 { 668 struct bcma_device *core; 669 u16 phy_access_addr; 670 u16 phy_ctl_addr; 671 u32 tmp; 672 673 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 674 core = bgmac->core->bus->drv_gmac_cmn.core; 675 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 676 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 677 } else { 678 core = bgmac->core; 679 phy_access_addr = BGMAC_PHY_ACCESS; 680 phy_ctl_addr = BGMAC_PHY_CNTL; 681 } 682 683 tmp = bcma_read32(core, phy_ctl_addr); 684 tmp &= ~BGMAC_PC_EPA_MASK; 685 tmp |= phyaddr; 686 bcma_write32(core, phy_ctl_addr, tmp); 687 688 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 689 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 690 bgmac_warn(bgmac, "Error setting MDIO int\n"); 691 692 tmp = BGMAC_PA_START; 693 tmp |= BGMAC_PA_WRITE; 694 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 695 tmp |= reg << BGMAC_PA_REG_SHIFT; 696 tmp |= value; 697 bcma_write32(core, phy_access_addr, tmp); 698 699 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 700 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 701 phyaddr, reg); 702 return -ETIMEDOUT; 703 } 704 705 return 0; 706 } 707 708 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 709 static void bgmac_phy_init(struct bgmac *bgmac) 710 { 711 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 712 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 713 u8 i; 714 715 if (ci->id == BCMA_CHIP_ID_BCM5356) { 716 for (i = 0; i < 5; i++) { 717 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 718 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 719 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 720 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 721 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 722 } 723 } 724 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 725 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 726 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 727 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 728 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 729 for (i = 0; i < 5; i++) { 730 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 731 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 732 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 733 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 734 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 735 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 736 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 737 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 738 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 739 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 740 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 741 } 742 } 743 } 744 745 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 746 static void bgmac_phy_reset(struct bgmac *bgmac) 747 { 748 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 749 return; 750 751 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 752 udelay(100); 753 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 754 bgmac_err(bgmac, "PHY reset failed\n"); 755 bgmac_phy_init(bgmac); 756 } 757 758 /************************************************** 759 * Chip ops 760 **************************************************/ 761 762 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 763 * nothing to change? Try if after stabilizng driver. 764 */ 765 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 766 bool force) 767 { 768 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 769 u32 new_val = (cmdcfg & mask) | set; 770 771 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 772 udelay(2); 773 774 if (new_val != cmdcfg || force) 775 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 776 777 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 778 udelay(2); 779 } 780 781 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 782 { 783 u32 tmp; 784 785 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 786 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 787 tmp = (addr[4] << 8) | addr[5]; 788 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 789 } 790 791 static void bgmac_set_rx_mode(struct net_device *net_dev) 792 { 793 struct bgmac *bgmac = netdev_priv(net_dev); 794 795 if (net_dev->flags & IFF_PROMISC) 796 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 797 else 798 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 799 } 800 801 #if 0 /* We don't use that regs yet */ 802 static void bgmac_chip_stats_update(struct bgmac *bgmac) 803 { 804 int i; 805 806 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 807 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 808 bgmac->mib_tx_regs[i] = 809 bgmac_read(bgmac, 810 BGMAC_TX_GOOD_OCTETS + (i * 4)); 811 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 812 bgmac->mib_rx_regs[i] = 813 bgmac_read(bgmac, 814 BGMAC_RX_GOOD_OCTETS + (i * 4)); 815 } 816 817 /* TODO: what else? how to handle BCM4706? Specs are needed */ 818 } 819 #endif 820 821 static void bgmac_clear_mib(struct bgmac *bgmac) 822 { 823 int i; 824 825 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 826 return; 827 828 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 829 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 830 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 831 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 832 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 833 } 834 835 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 836 static void bgmac_mac_speed(struct bgmac *bgmac) 837 { 838 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 839 u32 set = 0; 840 841 switch (bgmac->mac_speed) { 842 case SPEED_10: 843 set |= BGMAC_CMDCFG_ES_10; 844 break; 845 case SPEED_100: 846 set |= BGMAC_CMDCFG_ES_100; 847 break; 848 case SPEED_1000: 849 set |= BGMAC_CMDCFG_ES_1000; 850 break; 851 default: 852 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 853 } 854 855 if (bgmac->mac_duplex == DUPLEX_HALF) 856 set |= BGMAC_CMDCFG_HD; 857 858 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 859 } 860 861 static void bgmac_miiconfig(struct bgmac *bgmac) 862 { 863 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 864 BGMAC_DS_MM_SHIFT; 865 if (imode == 0 || imode == 1) { 866 bgmac->mac_speed = SPEED_100; 867 bgmac->mac_duplex = DUPLEX_FULL; 868 bgmac_mac_speed(bgmac); 869 } 870 } 871 872 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 873 static void bgmac_chip_reset(struct bgmac *bgmac) 874 { 875 struct bcma_device *core = bgmac->core; 876 struct bcma_bus *bus = core->bus; 877 struct bcma_chipinfo *ci = &bus->chipinfo; 878 u32 flags = 0; 879 u32 iost; 880 int i; 881 882 if (bcma_core_is_enabled(core)) { 883 if (!bgmac->stats_grabbed) { 884 /* bgmac_chip_stats_update(bgmac); */ 885 bgmac->stats_grabbed = true; 886 } 887 888 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 889 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 890 891 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 892 udelay(1); 893 894 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 895 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 896 897 /* TODO: Clear software multicast filter list */ 898 } 899 900 iost = bcma_aread32(core, BCMA_IOST); 901 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 902 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 903 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 904 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 905 906 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 907 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 908 if (!bgmac->has_robosw) 909 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 910 } 911 912 bcma_core_enable(core, flags); 913 914 if (core->id.rev > 2) { 915 bgmac_set(bgmac, BCMA_CLKCTLST, 916 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 917 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 918 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 919 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 920 1000); 921 } 922 923 if (ci->id == BCMA_CHIP_ID_BCM5357 || 924 ci->id == BCMA_CHIP_ID_BCM4749 || 925 ci->id == BCMA_CHIP_ID_BCM53572) { 926 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 927 u8 et_swtype = 0; 928 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 929 BGMAC_CHIPCTL_1_IF_TYPE_MII; 930 char buf[4]; 931 932 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 933 if (kstrtou8(buf, 0, &et_swtype)) 934 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 935 buf); 936 et_swtype &= 0x0f; 937 et_swtype <<= 4; 938 sw_type = et_swtype; 939 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 940 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 941 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 942 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 943 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 944 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 945 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 946 } 947 bcma_chipco_chipctl_maskset(cc, 1, 948 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 949 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 950 sw_type); 951 } 952 953 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 954 bcma_awrite32(core, BCMA_IOCTL, 955 bcma_aread32(core, BCMA_IOCTL) & 956 ~BGMAC_BCMA_IOCTL_SW_RESET); 957 958 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 959 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 960 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 961 * be keps until taking MAC out of the reset. 962 */ 963 bgmac_cmdcfg_maskset(bgmac, 964 ~(BGMAC_CMDCFG_TE | 965 BGMAC_CMDCFG_RE | 966 BGMAC_CMDCFG_RPI | 967 BGMAC_CMDCFG_TAI | 968 BGMAC_CMDCFG_HD | 969 BGMAC_CMDCFG_ML | 970 BGMAC_CMDCFG_CFE | 971 BGMAC_CMDCFG_RL | 972 BGMAC_CMDCFG_RED | 973 BGMAC_CMDCFG_PE | 974 BGMAC_CMDCFG_TPI | 975 BGMAC_CMDCFG_PAD_EN | 976 BGMAC_CMDCFG_PF), 977 BGMAC_CMDCFG_PROM | 978 BGMAC_CMDCFG_NLC | 979 BGMAC_CMDCFG_CFE | 980 BGMAC_CMDCFG_SR(core->id.rev), 981 false); 982 bgmac->mac_speed = SPEED_UNKNOWN; 983 bgmac->mac_duplex = DUPLEX_UNKNOWN; 984 985 bgmac_clear_mib(bgmac); 986 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 987 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 988 BCMA_GMAC_CMN_PC_MTE); 989 else 990 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 991 bgmac_miiconfig(bgmac); 992 bgmac_phy_init(bgmac); 993 994 netdev_reset_queue(bgmac->net_dev); 995 996 bgmac->int_status = 0; 997 } 998 999 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1000 { 1001 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1002 } 1003 1004 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1005 { 1006 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1007 bgmac_read(bgmac, BGMAC_INT_MASK); 1008 } 1009 1010 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1011 static void bgmac_enable(struct bgmac *bgmac) 1012 { 1013 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1014 u32 cmdcfg; 1015 u32 mode; 1016 u32 rxq_ctl; 1017 u32 fl_ctl; 1018 u16 bp_clk; 1019 u8 mdp; 1020 1021 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1022 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1023 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1024 udelay(2); 1025 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1026 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1027 1028 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1029 BGMAC_DS_MM_SHIFT; 1030 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1031 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1032 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1033 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1034 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1035 1036 switch (ci->id) { 1037 case BCMA_CHIP_ID_BCM5357: 1038 case BCMA_CHIP_ID_BCM4749: 1039 case BCMA_CHIP_ID_BCM53572: 1040 case BCMA_CHIP_ID_BCM4716: 1041 case BCMA_CHIP_ID_BCM47162: 1042 fl_ctl = 0x03cb04cb; 1043 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1044 ci->id == BCMA_CHIP_ID_BCM4749 || 1045 ci->id == BCMA_CHIP_ID_BCM53572) 1046 fl_ctl = 0x2300e1; 1047 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1048 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1049 break; 1050 } 1051 1052 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1053 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1054 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000; 1055 mdp = (bp_clk * 128 / 1000) - 3; 1056 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1057 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1058 } 1059 1060 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1061 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1062 { 1063 struct bgmac_dma_ring *ring; 1064 int i; 1065 1066 /* 1 interrupt per received frame */ 1067 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1068 1069 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1070 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1071 1072 bgmac_set_rx_mode(bgmac->net_dev); 1073 1074 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1075 1076 if (bgmac->loopback) 1077 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1078 else 1079 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1080 1081 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1082 1083 if (full_init) { 1084 bgmac_dma_init(bgmac); 1085 if (1) /* FIXME: is there any case we don't want IRQs? */ 1086 bgmac_chip_intrs_on(bgmac); 1087 } else { 1088 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1089 ring = &bgmac->rx_ring[i]; 1090 bgmac_dma_rx_enable(bgmac, ring); 1091 } 1092 } 1093 1094 bgmac_enable(bgmac); 1095 } 1096 1097 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1098 { 1099 struct bgmac *bgmac = netdev_priv(dev_id); 1100 1101 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1102 int_status &= bgmac->int_mask; 1103 1104 if (!int_status) 1105 return IRQ_NONE; 1106 1107 /* Ack */ 1108 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); 1109 1110 /* Disable new interrupts until handling existing ones */ 1111 bgmac_chip_intrs_off(bgmac); 1112 1113 bgmac->int_status = int_status; 1114 1115 napi_schedule(&bgmac->napi); 1116 1117 return IRQ_HANDLED; 1118 } 1119 1120 static int bgmac_poll(struct napi_struct *napi, int weight) 1121 { 1122 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1123 struct bgmac_dma_ring *ring; 1124 int handled = 0; 1125 1126 if (bgmac->int_status & BGMAC_IS_TX0) { 1127 ring = &bgmac->tx_ring[0]; 1128 bgmac_dma_tx_free(bgmac, ring); 1129 bgmac->int_status &= ~BGMAC_IS_TX0; 1130 } 1131 1132 if (bgmac->int_status & BGMAC_IS_RX) { 1133 ring = &bgmac->rx_ring[0]; 1134 handled += bgmac_dma_rx_read(bgmac, ring, weight); 1135 bgmac->int_status &= ~BGMAC_IS_RX; 1136 } 1137 1138 if (bgmac->int_status) { 1139 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); 1140 bgmac->int_status = 0; 1141 } 1142 1143 if (handled < weight) 1144 napi_complete(napi); 1145 1146 bgmac_chip_intrs_on(bgmac); 1147 1148 return handled; 1149 } 1150 1151 /************************************************** 1152 * net_device_ops 1153 **************************************************/ 1154 1155 static int bgmac_open(struct net_device *net_dev) 1156 { 1157 struct bgmac *bgmac = netdev_priv(net_dev); 1158 int err = 0; 1159 1160 bgmac_chip_reset(bgmac); 1161 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1162 bgmac_chip_init(bgmac, true); 1163 1164 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1165 KBUILD_MODNAME, net_dev); 1166 if (err < 0) { 1167 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1168 goto err_out; 1169 } 1170 napi_enable(&bgmac->napi); 1171 1172 phy_start(bgmac->phy_dev); 1173 1174 netif_carrier_on(net_dev); 1175 1176 err_out: 1177 return err; 1178 } 1179 1180 static int bgmac_stop(struct net_device *net_dev) 1181 { 1182 struct bgmac *bgmac = netdev_priv(net_dev); 1183 1184 netif_carrier_off(net_dev); 1185 1186 phy_stop(bgmac->phy_dev); 1187 1188 napi_disable(&bgmac->napi); 1189 bgmac_chip_intrs_off(bgmac); 1190 free_irq(bgmac->core->irq, net_dev); 1191 1192 bgmac_chip_reset(bgmac); 1193 1194 return 0; 1195 } 1196 1197 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1198 struct net_device *net_dev) 1199 { 1200 struct bgmac *bgmac = netdev_priv(net_dev); 1201 struct bgmac_dma_ring *ring; 1202 1203 /* No QOS support yet */ 1204 ring = &bgmac->tx_ring[0]; 1205 return bgmac_dma_tx_add(bgmac, ring, skb); 1206 } 1207 1208 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1209 { 1210 struct bgmac *bgmac = netdev_priv(net_dev); 1211 int ret; 1212 1213 ret = eth_prepare_mac_addr_change(net_dev, addr); 1214 if (ret < 0) 1215 return ret; 1216 bgmac_write_mac_address(bgmac, (u8 *)addr); 1217 eth_commit_mac_addr_change(net_dev, addr); 1218 return 0; 1219 } 1220 1221 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1222 { 1223 struct bgmac *bgmac = netdev_priv(net_dev); 1224 1225 if (!netif_running(net_dev)) 1226 return -EINVAL; 1227 1228 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1229 } 1230 1231 static const struct net_device_ops bgmac_netdev_ops = { 1232 .ndo_open = bgmac_open, 1233 .ndo_stop = bgmac_stop, 1234 .ndo_start_xmit = bgmac_start_xmit, 1235 .ndo_set_rx_mode = bgmac_set_rx_mode, 1236 .ndo_set_mac_address = bgmac_set_mac_address, 1237 .ndo_validate_addr = eth_validate_addr, 1238 .ndo_do_ioctl = bgmac_ioctl, 1239 }; 1240 1241 /************************************************** 1242 * ethtool_ops 1243 **************************************************/ 1244 1245 static int bgmac_get_settings(struct net_device *net_dev, 1246 struct ethtool_cmd *cmd) 1247 { 1248 struct bgmac *bgmac = netdev_priv(net_dev); 1249 1250 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1251 } 1252 1253 static int bgmac_set_settings(struct net_device *net_dev, 1254 struct ethtool_cmd *cmd) 1255 { 1256 struct bgmac *bgmac = netdev_priv(net_dev); 1257 1258 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1259 } 1260 1261 static void bgmac_get_drvinfo(struct net_device *net_dev, 1262 struct ethtool_drvinfo *info) 1263 { 1264 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1265 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1266 } 1267 1268 static const struct ethtool_ops bgmac_ethtool_ops = { 1269 .get_settings = bgmac_get_settings, 1270 .set_settings = bgmac_set_settings, 1271 .get_drvinfo = bgmac_get_drvinfo, 1272 }; 1273 1274 /************************************************** 1275 * MII 1276 **************************************************/ 1277 1278 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1279 { 1280 return bgmac_phy_read(bus->priv, mii_id, regnum); 1281 } 1282 1283 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1284 u16 value) 1285 { 1286 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1287 } 1288 1289 static void bgmac_adjust_link(struct net_device *net_dev) 1290 { 1291 struct bgmac *bgmac = netdev_priv(net_dev); 1292 struct phy_device *phy_dev = bgmac->phy_dev; 1293 bool update = false; 1294 1295 if (phy_dev->link) { 1296 if (phy_dev->speed != bgmac->mac_speed) { 1297 bgmac->mac_speed = phy_dev->speed; 1298 update = true; 1299 } 1300 1301 if (phy_dev->duplex != bgmac->mac_duplex) { 1302 bgmac->mac_duplex = phy_dev->duplex; 1303 update = true; 1304 } 1305 } 1306 1307 if (update) { 1308 bgmac_mac_speed(bgmac); 1309 phy_print_status(phy_dev); 1310 } 1311 } 1312 1313 static int bgmac_mii_register(struct bgmac *bgmac) 1314 { 1315 struct mii_bus *mii_bus; 1316 struct phy_device *phy_dev; 1317 char bus_id[MII_BUS_ID_SIZE + 3]; 1318 int i, err = 0; 1319 1320 mii_bus = mdiobus_alloc(); 1321 if (!mii_bus) 1322 return -ENOMEM; 1323 1324 mii_bus->name = "bgmac mii bus"; 1325 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1326 bgmac->core->core_unit); 1327 mii_bus->priv = bgmac; 1328 mii_bus->read = bgmac_mii_read; 1329 mii_bus->write = bgmac_mii_write; 1330 mii_bus->parent = &bgmac->core->dev; 1331 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1332 1333 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 1334 if (!mii_bus->irq) { 1335 err = -ENOMEM; 1336 goto err_free_bus; 1337 } 1338 for (i = 0; i < PHY_MAX_ADDR; i++) 1339 mii_bus->irq[i] = PHY_POLL; 1340 1341 err = mdiobus_register(mii_bus); 1342 if (err) { 1343 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1344 goto err_free_irq; 1345 } 1346 1347 bgmac->mii_bus = mii_bus; 1348 1349 /* Connect to the PHY */ 1350 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1351 bgmac->phyaddr); 1352 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1353 PHY_INTERFACE_MODE_MII); 1354 if (IS_ERR(phy_dev)) { 1355 bgmac_err(bgmac, "PHY connecton failed\n"); 1356 err = PTR_ERR(phy_dev); 1357 goto err_unregister_bus; 1358 } 1359 bgmac->phy_dev = phy_dev; 1360 1361 return err; 1362 1363 err_unregister_bus: 1364 mdiobus_unregister(mii_bus); 1365 err_free_irq: 1366 kfree(mii_bus->irq); 1367 err_free_bus: 1368 mdiobus_free(mii_bus); 1369 return err; 1370 } 1371 1372 static void bgmac_mii_unregister(struct bgmac *bgmac) 1373 { 1374 struct mii_bus *mii_bus = bgmac->mii_bus; 1375 1376 mdiobus_unregister(mii_bus); 1377 kfree(mii_bus->irq); 1378 mdiobus_free(mii_bus); 1379 } 1380 1381 /************************************************** 1382 * BCMA bus ops 1383 **************************************************/ 1384 1385 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1386 static int bgmac_probe(struct bcma_device *core) 1387 { 1388 struct net_device *net_dev; 1389 struct bgmac *bgmac; 1390 struct ssb_sprom *sprom = &core->bus->sprom; 1391 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1392 int err; 1393 1394 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1395 if (core->core_unit > 1) { 1396 pr_err("Unsupported core_unit %d\n", core->core_unit); 1397 return -ENOTSUPP; 1398 } 1399 1400 if (!is_valid_ether_addr(mac)) { 1401 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1402 eth_random_addr(mac); 1403 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1404 } 1405 1406 /* Allocation and references */ 1407 net_dev = alloc_etherdev(sizeof(*bgmac)); 1408 if (!net_dev) 1409 return -ENOMEM; 1410 net_dev->netdev_ops = &bgmac_netdev_ops; 1411 net_dev->irq = core->irq; 1412 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops); 1413 bgmac = netdev_priv(net_dev); 1414 bgmac->net_dev = net_dev; 1415 bgmac->core = core; 1416 bcma_set_drvdata(core, bgmac); 1417 1418 /* Defaults */ 1419 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1420 1421 /* On BCM4706 we need common core to access PHY */ 1422 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1423 !core->bus->drv_gmac_cmn.core) { 1424 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1425 err = -ENODEV; 1426 goto err_netdev_free; 1427 } 1428 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1429 1430 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1431 sprom->et0phyaddr; 1432 bgmac->phyaddr &= BGMAC_PHY_MASK; 1433 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1434 bgmac_err(bgmac, "No PHY found\n"); 1435 err = -ENODEV; 1436 goto err_netdev_free; 1437 } 1438 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1439 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1440 1441 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1442 bgmac_err(bgmac, "PCI setup not implemented\n"); 1443 err = -ENOTSUPP; 1444 goto err_netdev_free; 1445 } 1446 1447 bgmac_chip_reset(bgmac); 1448 1449 /* For Northstar, we have to take all GMAC core out of reset */ 1450 if (core->id.id == BCMA_CHIP_ID_BCM4707 || 1451 core->id.id == BCMA_CHIP_ID_BCM53018) { 1452 struct bcma_device *ns_core; 1453 int ns_gmac; 1454 1455 /* Northstar has 4 GMAC cores */ 1456 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1457 /* As northstar requirement, we have to reset all GAMCs 1458 * before accessing one. bgmac_chip_reset() call 1459 * bcma_core_enable() for this core. Then the other 1460 * three GAMCs didn't reset. We do it here. 1461 */ 1462 ns_core = bcma_find_core_unit(core->bus, 1463 BCMA_CORE_MAC_GBIT, 1464 ns_gmac); 1465 if (ns_core && !bcma_core_is_enabled(ns_core)) 1466 bcma_core_enable(ns_core, 0); 1467 } 1468 } 1469 1470 err = bgmac_dma_alloc(bgmac); 1471 if (err) { 1472 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1473 goto err_netdev_free; 1474 } 1475 1476 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1477 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1478 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1479 1480 /* TODO: reset the external phy. Specs are needed */ 1481 bgmac_phy_reset(bgmac); 1482 1483 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1484 BGMAC_BFL_ENETROBO); 1485 if (bgmac->has_robosw) 1486 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1487 1488 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1489 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1490 1491 err = bgmac_mii_register(bgmac); 1492 if (err) { 1493 bgmac_err(bgmac, "Cannot register MDIO\n"); 1494 err = -ENOTSUPP; 1495 goto err_dma_free; 1496 } 1497 1498 err = register_netdev(bgmac->net_dev); 1499 if (err) { 1500 bgmac_err(bgmac, "Cannot register net device\n"); 1501 err = -ENOTSUPP; 1502 goto err_mii_unregister; 1503 } 1504 1505 netif_carrier_off(net_dev); 1506 1507 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1508 1509 return 0; 1510 1511 err_mii_unregister: 1512 bgmac_mii_unregister(bgmac); 1513 err_dma_free: 1514 bgmac_dma_free(bgmac); 1515 1516 err_netdev_free: 1517 bcma_set_drvdata(core, NULL); 1518 free_netdev(net_dev); 1519 1520 return err; 1521 } 1522 1523 static void bgmac_remove(struct bcma_device *core) 1524 { 1525 struct bgmac *bgmac = bcma_get_drvdata(core); 1526 1527 netif_napi_del(&bgmac->napi); 1528 unregister_netdev(bgmac->net_dev); 1529 bgmac_mii_unregister(bgmac); 1530 bgmac_dma_free(bgmac); 1531 bcma_set_drvdata(core, NULL); 1532 free_netdev(bgmac->net_dev); 1533 } 1534 1535 static struct bcma_driver bgmac_bcma_driver = { 1536 .name = KBUILD_MODNAME, 1537 .id_table = bgmac_bcma_tbl, 1538 .probe = bgmac_probe, 1539 .remove = bgmac_remove, 1540 }; 1541 1542 static int __init bgmac_init(void) 1543 { 1544 int err; 1545 1546 err = bcma_driver_register(&bgmac_bcma_driver); 1547 if (err) 1548 return err; 1549 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1550 1551 return 0; 1552 } 1553 1554 static void __exit bgmac_exit(void) 1555 { 1556 bcma_driver_unregister(&bgmac_bcma_driver); 1557 } 1558 1559 module_init(bgmac_init) 1560 module_exit(bgmac_exit) 1561 1562 MODULE_AUTHOR("Rafał Miłecki"); 1563 MODULE_LICENSE("GPL"); 1564