1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <bcm47xx_nvram.h> 21 22 static const struct bcma_device_id bgmac_bcma_tbl[] = { 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 28 29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 30 u32 value, int timeout) 31 { 32 u32 val; 33 int i; 34 35 for (i = 0; i < timeout / 10; i++) { 36 val = bcma_read32(core, reg); 37 if ((val & mask) == value) 38 return true; 39 udelay(10); 40 } 41 pr_err("Timeout waiting for reg 0x%X\n", reg); 42 return false; 43 } 44 45 /************************************************** 46 * DMA 47 **************************************************/ 48 49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 50 { 51 u32 val; 52 int i; 53 54 if (!ring->mmio_base) 55 return; 56 57 /* Suspend DMA TX ring first. 58 * bgmac_wait_value doesn't support waiting for any of few values, so 59 * implement whole loop here. 60 */ 61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 62 BGMAC_DMA_TX_SUSPEND); 63 for (i = 0; i < 10000 / 10; i++) { 64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 65 val &= BGMAC_DMA_TX_STAT; 66 if (val == BGMAC_DMA_TX_STAT_DISABLED || 67 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 68 val == BGMAC_DMA_TX_STAT_STOPPED) { 69 i = 0; 70 break; 71 } 72 udelay(10); 73 } 74 if (i) 75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 76 ring->mmio_base, val); 77 78 /* Remove SUSPEND bit */ 79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 80 if (!bgmac_wait_value(bgmac->core, 81 ring->mmio_base + BGMAC_DMA_TX_STATUS, 82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 83 10000)) { 84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 85 ring->mmio_base); 86 udelay(300); 87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 90 ring->mmio_base); 91 } 92 } 93 94 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 95 struct bgmac_dma_ring *ring) 96 { 97 u32 ctl; 98 99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 100 if (bgmac->core->id.rev >= 4) { 101 ctl &= ~BGMAC_DMA_TX_BL_MASK; 102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 103 104 ctl &= ~BGMAC_DMA_TX_MR_MASK; 105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 106 107 ctl &= ~BGMAC_DMA_TX_PC_MASK; 108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 109 110 ctl &= ~BGMAC_DMA_TX_PT_MASK; 111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 112 } 113 ctl |= BGMAC_DMA_TX_ENABLE; 114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 116 } 117 118 static void 119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 120 int i, int len, u32 ctl0) 121 { 122 struct bgmac_slot_info *slot; 123 struct bgmac_dma_desc *dma_desc; 124 u32 ctl1; 125 126 if (i == ring->num_slots - 1) 127 ctl0 |= BGMAC_DESC_CTL0_EOT; 128 129 ctl1 = len & BGMAC_DESC_CTL1_LEN; 130 131 slot = &ring->slots[i]; 132 dma_desc = &ring->cpu_base[i]; 133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 135 dma_desc->ctl0 = cpu_to_le32(ctl0); 136 dma_desc->ctl1 = cpu_to_le32(ctl1); 137 } 138 139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 140 struct bgmac_dma_ring *ring, 141 struct sk_buff *skb) 142 { 143 struct device *dma_dev = bgmac->core->dma_dev; 144 struct net_device *net_dev = bgmac->net_dev; 145 int index = ring->end % BGMAC_TX_RING_SLOTS; 146 struct bgmac_slot_info *slot = &ring->slots[index]; 147 int nr_frags; 148 u32 flags; 149 int i; 150 151 if (skb->len > BGMAC_DESC_CTL1_LEN) { 152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 153 goto err_drop; 154 } 155 156 if (skb->ip_summed == CHECKSUM_PARTIAL) 157 skb_checksum_help(skb); 158 159 nr_frags = skb_shinfo(skb)->nr_frags; 160 161 /* ring->end - ring->start will return the number of valid slots, 162 * even when ring->end overflows 163 */ 164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 166 netif_stop_queue(net_dev); 167 return NETDEV_TX_BUSY; 168 } 169 170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 171 DMA_TO_DEVICE); 172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 173 goto err_dma_head; 174 175 flags = BGMAC_DESC_CTL0_SOF; 176 if (!nr_frags) 177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 178 179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 180 flags = 0; 181 182 for (i = 0; i < nr_frags; i++) { 183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 184 int len = skb_frag_size(frag); 185 186 index = (index + 1) % BGMAC_TX_RING_SLOTS; 187 slot = &ring->slots[index]; 188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 189 len, DMA_TO_DEVICE); 190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 191 goto err_dma; 192 193 if (i == nr_frags - 1) 194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 195 196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 197 } 198 199 slot->skb = skb; 200 ring->end += nr_frags + 1; 201 netdev_sent_queue(net_dev, skb->len); 202 203 wmb(); 204 205 /* Increase ring->end to point empty slot. We tell hardware the first 206 * slot it should *not* read. 207 */ 208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 209 ring->index_base + 210 (ring->end % BGMAC_TX_RING_SLOTS) * 211 sizeof(struct bgmac_dma_desc)); 212 213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 214 netif_stop_queue(net_dev); 215 216 return NETDEV_TX_OK; 217 218 err_dma: 219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 220 DMA_TO_DEVICE); 221 222 while (i > 0) { 223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 224 struct bgmac_slot_info *slot = &ring->slots[index]; 225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 226 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 227 228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 229 } 230 231 err_dma_head: 232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 233 ring->mmio_base); 234 235 err_drop: 236 dev_kfree_skb(skb); 237 return NETDEV_TX_OK; 238 } 239 240 /* Free transmitted packets */ 241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 242 { 243 struct device *dma_dev = bgmac->core->dma_dev; 244 int empty_slot; 245 bool freed = false; 246 unsigned bytes_compl = 0, pkts_compl = 0; 247 248 /* The last slot that hardware didn't consume yet */ 249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 250 empty_slot &= BGMAC_DMA_TX_STATDPTR; 251 empty_slot -= ring->index_base; 252 empty_slot &= BGMAC_DMA_TX_STATDPTR; 253 empty_slot /= sizeof(struct bgmac_dma_desc); 254 255 while (ring->start != ring->end) { 256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 257 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 258 u32 ctl1; 259 int len; 260 261 if (slot_idx == empty_slot) 262 break; 263 264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 265 len = ctl1 & BGMAC_DESC_CTL1_LEN; 266 if (ctl1 & BGMAC_DESC_CTL0_SOF) 267 /* Unmap no longer used buffer */ 268 dma_unmap_single(dma_dev, slot->dma_addr, len, 269 DMA_TO_DEVICE); 270 else 271 dma_unmap_page(dma_dev, slot->dma_addr, len, 272 DMA_TO_DEVICE); 273 274 if (slot->skb) { 275 bytes_compl += slot->skb->len; 276 pkts_compl++; 277 278 /* Free memory! :) */ 279 dev_kfree_skb(slot->skb); 280 slot->skb = NULL; 281 } 282 283 slot->dma_addr = 0; 284 ring->start++; 285 freed = true; 286 } 287 288 if (!pkts_compl) 289 return; 290 291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 292 293 if (netif_queue_stopped(bgmac->net_dev)) 294 netif_wake_queue(bgmac->net_dev); 295 } 296 297 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 298 { 299 if (!ring->mmio_base) 300 return; 301 302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 303 if (!bgmac_wait_value(bgmac->core, 304 ring->mmio_base + BGMAC_DMA_RX_STATUS, 305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 306 10000)) 307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 308 ring->mmio_base); 309 } 310 311 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 312 struct bgmac_dma_ring *ring) 313 { 314 u32 ctl; 315 316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 317 if (bgmac->core->id.rev >= 4) { 318 ctl &= ~BGMAC_DMA_RX_BL_MASK; 319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 320 321 ctl &= ~BGMAC_DMA_RX_PC_MASK; 322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 323 324 ctl &= ~BGMAC_DMA_RX_PT_MASK; 325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 326 } 327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 328 ctl |= BGMAC_DMA_RX_ENABLE; 329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 333 } 334 335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 336 struct bgmac_slot_info *slot) 337 { 338 struct device *dma_dev = bgmac->core->dma_dev; 339 dma_addr_t dma_addr; 340 struct bgmac_rx_header *rx; 341 void *buf; 342 343 /* Alloc skb */ 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 345 if (!buf) 346 return -ENOMEM; 347 348 /* Poison - if everything goes fine, hardware will overwrite it */ 349 rx = buf + BGMAC_RX_BUF_OFFSET; 350 rx->len = cpu_to_le16(0xdead); 351 rx->flags = cpu_to_le16(0xbeef); 352 353 /* Map skb for the DMA */ 354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 356 if (dma_mapping_error(dma_dev, dma_addr)) { 357 bgmac_err(bgmac, "DMA mapping error\n"); 358 put_page(virt_to_head_page(buf)); 359 return -ENOMEM; 360 } 361 362 /* Update the slot */ 363 slot->buf = buf; 364 slot->dma_addr = dma_addr; 365 366 return 0; 367 } 368 369 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 370 struct bgmac_dma_ring *ring, int desc_idx) 371 { 372 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 373 u32 ctl0 = 0, ctl1 = 0; 374 375 if (desc_idx == ring->num_slots - 1) 376 ctl0 |= BGMAC_DESC_CTL0_EOT; 377 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 378 /* Is there any BGMAC device that requires extension? */ 379 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 380 * B43_DMA64_DCTL1_ADDREXT_MASK; 381 */ 382 383 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 384 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 385 dma_desc->ctl0 = cpu_to_le32(ctl0); 386 dma_desc->ctl1 = cpu_to_le32(ctl1); 387 } 388 389 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 390 struct bgmac_slot_info *slot) 391 { 392 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 393 394 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 395 DMA_FROM_DEVICE); 396 rx->len = cpu_to_le16(0xdead); 397 rx->flags = cpu_to_le16(0xbeef); 398 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 399 DMA_FROM_DEVICE); 400 } 401 402 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 403 int weight) 404 { 405 u32 end_slot; 406 int handled = 0; 407 408 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 409 end_slot &= BGMAC_DMA_RX_STATDPTR; 410 end_slot -= ring->index_base; 411 end_slot &= BGMAC_DMA_RX_STATDPTR; 412 end_slot /= sizeof(struct bgmac_dma_desc); 413 414 ring->end = end_slot; 415 416 while (ring->start != ring->end) { 417 struct device *dma_dev = bgmac->core->dma_dev; 418 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 419 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 420 struct sk_buff *skb; 421 void *buf = slot->buf; 422 dma_addr_t dma_addr = slot->dma_addr; 423 u16 len, flags; 424 425 do { 426 /* Prepare new skb as replacement */ 427 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 428 bgmac_dma_rx_poison_buf(dma_dev, slot); 429 break; 430 } 431 432 /* Unmap buffer to make it accessible to the CPU */ 433 dma_unmap_single(dma_dev, dma_addr, 434 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 435 436 /* Get info from the header */ 437 len = le16_to_cpu(rx->len); 438 flags = le16_to_cpu(rx->flags); 439 440 /* Check for poison and drop or pass the packet */ 441 if (len == 0xdead && flags == 0xbeef) { 442 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 443 ring->start); 444 put_page(virt_to_head_page(buf)); 445 break; 446 } 447 448 /* Omit CRC. */ 449 len -= ETH_FCS_LEN; 450 451 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 452 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 453 BGMAC_RX_BUF_OFFSET + len); 454 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 455 BGMAC_RX_BUF_OFFSET); 456 457 skb_checksum_none_assert(skb); 458 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 459 napi_gro_receive(&bgmac->napi, skb); 460 handled++; 461 } while (0); 462 463 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 464 465 if (++ring->start >= BGMAC_RX_RING_SLOTS) 466 ring->start = 0; 467 468 if (handled >= weight) /* Should never be greater */ 469 break; 470 } 471 472 return handled; 473 } 474 475 /* Does ring support unaligned addressing? */ 476 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 477 struct bgmac_dma_ring *ring, 478 enum bgmac_dma_ring_type ring_type) 479 { 480 switch (ring_type) { 481 case BGMAC_DMA_RING_TX: 482 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 483 0xff0); 484 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 485 return true; 486 break; 487 case BGMAC_DMA_RING_RX: 488 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 489 0xff0); 490 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 491 return true; 492 break; 493 } 494 return false; 495 } 496 497 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 498 struct bgmac_dma_ring *ring) 499 { 500 struct device *dma_dev = bgmac->core->dma_dev; 501 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 502 struct bgmac_slot_info *slot; 503 int i; 504 505 for (i = 0; i < ring->num_slots; i++) { 506 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 507 508 slot = &ring->slots[i]; 509 dev_kfree_skb(slot->skb); 510 511 if (!slot->dma_addr) 512 continue; 513 514 if (slot->skb) 515 dma_unmap_single(dma_dev, slot->dma_addr, 516 len, DMA_TO_DEVICE); 517 else 518 dma_unmap_page(dma_dev, slot->dma_addr, 519 len, DMA_TO_DEVICE); 520 } 521 } 522 523 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 524 struct bgmac_dma_ring *ring) 525 { 526 struct device *dma_dev = bgmac->core->dma_dev; 527 struct bgmac_slot_info *slot; 528 int i; 529 530 for (i = 0; i < ring->num_slots; i++) { 531 slot = &ring->slots[i]; 532 if (!slot->dma_addr) 533 continue; 534 535 dma_unmap_single(dma_dev, slot->dma_addr, 536 BGMAC_RX_BUF_SIZE, 537 DMA_FROM_DEVICE); 538 put_page(virt_to_head_page(slot->buf)); 539 slot->dma_addr = 0; 540 } 541 } 542 543 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 544 struct bgmac_dma_ring *ring) 545 { 546 struct device *dma_dev = bgmac->core->dma_dev; 547 int size; 548 549 if (!ring->cpu_base) 550 return; 551 552 /* Free ring of descriptors */ 553 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 554 dma_free_coherent(dma_dev, size, ring->cpu_base, 555 ring->dma_base); 556 } 557 558 static void bgmac_dma_free(struct bgmac *bgmac) 559 { 560 int i; 561 562 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 563 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 564 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); 565 } 566 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 567 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 568 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); 569 } 570 } 571 572 static int bgmac_dma_alloc(struct bgmac *bgmac) 573 { 574 struct device *dma_dev = bgmac->core->dma_dev; 575 struct bgmac_dma_ring *ring; 576 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 577 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 578 int size; /* ring size: different for Tx and Rx */ 579 int err; 580 int i; 581 582 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 583 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 584 585 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 586 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 587 return -ENOTSUPP; 588 } 589 590 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 591 ring = &bgmac->tx_ring[i]; 592 ring->num_slots = BGMAC_TX_RING_SLOTS; 593 ring->mmio_base = ring_base[i]; 594 595 /* Alloc ring of descriptors */ 596 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 597 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 598 &ring->dma_base, 599 GFP_KERNEL); 600 if (!ring->cpu_base) { 601 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 602 ring->mmio_base); 603 goto err_dma_free; 604 } 605 606 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 607 BGMAC_DMA_RING_TX); 608 if (ring->unaligned) 609 ring->index_base = lower_32_bits(ring->dma_base); 610 else 611 ring->index_base = 0; 612 613 /* No need to alloc TX slots yet */ 614 } 615 616 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 617 int j; 618 619 ring = &bgmac->rx_ring[i]; 620 ring->num_slots = BGMAC_RX_RING_SLOTS; 621 ring->mmio_base = ring_base[i]; 622 623 /* Alloc ring of descriptors */ 624 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 625 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 626 &ring->dma_base, 627 GFP_KERNEL); 628 if (!ring->cpu_base) { 629 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 630 ring->mmio_base); 631 err = -ENOMEM; 632 goto err_dma_free; 633 } 634 635 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 636 BGMAC_DMA_RING_RX); 637 if (ring->unaligned) 638 ring->index_base = lower_32_bits(ring->dma_base); 639 else 640 ring->index_base = 0; 641 642 /* Alloc RX slots */ 643 for (j = 0; j < ring->num_slots; j++) { 644 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 645 if (err) { 646 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 647 goto err_dma_free; 648 } 649 } 650 } 651 652 return 0; 653 654 err_dma_free: 655 bgmac_dma_free(bgmac); 656 return -ENOMEM; 657 } 658 659 static void bgmac_dma_init(struct bgmac *bgmac) 660 { 661 struct bgmac_dma_ring *ring; 662 int i; 663 664 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 665 ring = &bgmac->tx_ring[i]; 666 667 if (!ring->unaligned) 668 bgmac_dma_tx_enable(bgmac, ring); 669 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 670 lower_32_bits(ring->dma_base)); 671 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 672 upper_32_bits(ring->dma_base)); 673 if (ring->unaligned) 674 bgmac_dma_tx_enable(bgmac, ring); 675 676 ring->start = 0; 677 ring->end = 0; /* Points the slot that should *not* be read */ 678 } 679 680 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 681 int j; 682 683 ring = &bgmac->rx_ring[i]; 684 685 if (!ring->unaligned) 686 bgmac_dma_rx_enable(bgmac, ring); 687 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 688 lower_32_bits(ring->dma_base)); 689 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 690 upper_32_bits(ring->dma_base)); 691 if (ring->unaligned) 692 bgmac_dma_rx_enable(bgmac, ring); 693 694 for (j = 0; j < ring->num_slots; j++) 695 bgmac_dma_rx_setup_desc(bgmac, ring, j); 696 697 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 698 ring->index_base + 699 ring->num_slots * sizeof(struct bgmac_dma_desc)); 700 701 ring->start = 0; 702 ring->end = 0; 703 } 704 } 705 706 /************************************************** 707 * PHY ops 708 **************************************************/ 709 710 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 711 { 712 struct bcma_device *core; 713 u16 phy_access_addr; 714 u16 phy_ctl_addr; 715 u32 tmp; 716 717 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 718 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 719 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 720 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 721 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 722 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 723 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 724 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 725 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 726 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 727 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 728 729 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 730 core = bgmac->core->bus->drv_gmac_cmn.core; 731 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 732 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 733 } else { 734 core = bgmac->core; 735 phy_access_addr = BGMAC_PHY_ACCESS; 736 phy_ctl_addr = BGMAC_PHY_CNTL; 737 } 738 739 tmp = bcma_read32(core, phy_ctl_addr); 740 tmp &= ~BGMAC_PC_EPA_MASK; 741 tmp |= phyaddr; 742 bcma_write32(core, phy_ctl_addr, tmp); 743 744 tmp = BGMAC_PA_START; 745 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 746 tmp |= reg << BGMAC_PA_REG_SHIFT; 747 bcma_write32(core, phy_access_addr, tmp); 748 749 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 750 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 751 phyaddr, reg); 752 return 0xffff; 753 } 754 755 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 756 } 757 758 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 759 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 760 { 761 struct bcma_device *core; 762 u16 phy_access_addr; 763 u16 phy_ctl_addr; 764 u32 tmp; 765 766 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 767 core = bgmac->core->bus->drv_gmac_cmn.core; 768 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 769 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 770 } else { 771 core = bgmac->core; 772 phy_access_addr = BGMAC_PHY_ACCESS; 773 phy_ctl_addr = BGMAC_PHY_CNTL; 774 } 775 776 tmp = bcma_read32(core, phy_ctl_addr); 777 tmp &= ~BGMAC_PC_EPA_MASK; 778 tmp |= phyaddr; 779 bcma_write32(core, phy_ctl_addr, tmp); 780 781 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 782 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 783 bgmac_warn(bgmac, "Error setting MDIO int\n"); 784 785 tmp = BGMAC_PA_START; 786 tmp |= BGMAC_PA_WRITE; 787 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 788 tmp |= reg << BGMAC_PA_REG_SHIFT; 789 tmp |= value; 790 bcma_write32(core, phy_access_addr, tmp); 791 792 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 793 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 794 phyaddr, reg); 795 return -ETIMEDOUT; 796 } 797 798 return 0; 799 } 800 801 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 802 static void bgmac_phy_init(struct bgmac *bgmac) 803 { 804 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 805 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 806 u8 i; 807 808 if (ci->id == BCMA_CHIP_ID_BCM5356) { 809 for (i = 0; i < 5; i++) { 810 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 811 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 812 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 813 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 814 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 815 } 816 } 817 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 818 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 819 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 820 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 821 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 822 for (i = 0; i < 5; i++) { 823 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 824 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 825 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 826 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 827 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 828 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 829 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 830 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 831 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 832 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 833 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 834 } 835 } 836 } 837 838 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 839 static void bgmac_phy_reset(struct bgmac *bgmac) 840 { 841 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 842 return; 843 844 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 845 udelay(100); 846 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 847 bgmac_err(bgmac, "PHY reset failed\n"); 848 bgmac_phy_init(bgmac); 849 } 850 851 /************************************************** 852 * Chip ops 853 **************************************************/ 854 855 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 856 * nothing to change? Try if after stabilizng driver. 857 */ 858 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 859 bool force) 860 { 861 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 862 u32 new_val = (cmdcfg & mask) | set; 863 864 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 865 udelay(2); 866 867 if (new_val != cmdcfg || force) 868 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 869 870 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 871 udelay(2); 872 } 873 874 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 875 { 876 u32 tmp; 877 878 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 879 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 880 tmp = (addr[4] << 8) | addr[5]; 881 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 882 } 883 884 static void bgmac_set_rx_mode(struct net_device *net_dev) 885 { 886 struct bgmac *bgmac = netdev_priv(net_dev); 887 888 if (net_dev->flags & IFF_PROMISC) 889 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 890 else 891 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 892 } 893 894 #if 0 /* We don't use that regs yet */ 895 static void bgmac_chip_stats_update(struct bgmac *bgmac) 896 { 897 int i; 898 899 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 900 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 901 bgmac->mib_tx_regs[i] = 902 bgmac_read(bgmac, 903 BGMAC_TX_GOOD_OCTETS + (i * 4)); 904 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 905 bgmac->mib_rx_regs[i] = 906 bgmac_read(bgmac, 907 BGMAC_RX_GOOD_OCTETS + (i * 4)); 908 } 909 910 /* TODO: what else? how to handle BCM4706? Specs are needed */ 911 } 912 #endif 913 914 static void bgmac_clear_mib(struct bgmac *bgmac) 915 { 916 int i; 917 918 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 919 return; 920 921 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 922 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 923 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 924 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 925 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 926 } 927 928 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 929 static void bgmac_mac_speed(struct bgmac *bgmac) 930 { 931 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 932 u32 set = 0; 933 934 switch (bgmac->mac_speed) { 935 case SPEED_10: 936 set |= BGMAC_CMDCFG_ES_10; 937 break; 938 case SPEED_100: 939 set |= BGMAC_CMDCFG_ES_100; 940 break; 941 case SPEED_1000: 942 set |= BGMAC_CMDCFG_ES_1000; 943 break; 944 case SPEED_2500: 945 set |= BGMAC_CMDCFG_ES_2500; 946 break; 947 default: 948 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 949 } 950 951 if (bgmac->mac_duplex == DUPLEX_HALF) 952 set |= BGMAC_CMDCFG_HD; 953 954 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 955 } 956 957 static void bgmac_miiconfig(struct bgmac *bgmac) 958 { 959 struct bcma_device *core = bgmac->core; 960 struct bcma_chipinfo *ci = &core->bus->chipinfo; 961 u8 imode; 962 963 if (ci->id == BCMA_CHIP_ID_BCM4707 || 964 ci->id == BCMA_CHIP_ID_BCM53018) { 965 bcma_awrite32(core, BCMA_IOCTL, 966 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 967 BGMAC_BCMA_IOCTL_SW_CLKEN); 968 bgmac->mac_speed = SPEED_2500; 969 bgmac->mac_duplex = DUPLEX_FULL; 970 bgmac_mac_speed(bgmac); 971 } else { 972 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 973 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 974 if (imode == 0 || imode == 1) { 975 bgmac->mac_speed = SPEED_100; 976 bgmac->mac_duplex = DUPLEX_FULL; 977 bgmac_mac_speed(bgmac); 978 } 979 } 980 } 981 982 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 983 static void bgmac_chip_reset(struct bgmac *bgmac) 984 { 985 struct bcma_device *core = bgmac->core; 986 struct bcma_bus *bus = core->bus; 987 struct bcma_chipinfo *ci = &bus->chipinfo; 988 u32 flags; 989 u32 iost; 990 int i; 991 992 if (bcma_core_is_enabled(core)) { 993 if (!bgmac->stats_grabbed) { 994 /* bgmac_chip_stats_update(bgmac); */ 995 bgmac->stats_grabbed = true; 996 } 997 998 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 999 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 1000 1001 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1002 udelay(1); 1003 1004 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 1005 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 1006 1007 /* TODO: Clear software multicast filter list */ 1008 } 1009 1010 iost = bcma_aread32(core, BCMA_IOST); 1011 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1012 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1013 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 1014 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 1015 1016 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ 1017 if (ci->id != BCMA_CHIP_ID_BCM4707) { 1018 flags = 0; 1019 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 1020 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 1021 if (!bgmac->has_robosw) 1022 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 1023 } 1024 bcma_core_enable(core, flags); 1025 } 1026 1027 /* Request Misc PLL for corerev > 2 */ 1028 if (core->id.rev > 2 && 1029 ci->id != BCMA_CHIP_ID_BCM4707 && 1030 ci->id != BCMA_CHIP_ID_BCM53018) { 1031 bgmac_set(bgmac, BCMA_CLKCTLST, 1032 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 1033 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1034 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1035 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1036 1000); 1037 } 1038 1039 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1040 ci->id == BCMA_CHIP_ID_BCM4749 || 1041 ci->id == BCMA_CHIP_ID_BCM53572) { 1042 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 1043 u8 et_swtype = 0; 1044 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 1045 BGMAC_CHIPCTL_1_IF_TYPE_MII; 1046 char buf[4]; 1047 1048 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 1049 if (kstrtou8(buf, 0, &et_swtype)) 1050 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 1051 buf); 1052 et_swtype &= 0x0f; 1053 et_swtype <<= 4; 1054 sw_type = et_swtype; 1055 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 1056 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 1057 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1058 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1059 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 1060 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 1061 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 1062 } 1063 bcma_chipco_chipctl_maskset(cc, 1, 1064 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 1065 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 1066 sw_type); 1067 } 1068 1069 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 1070 bcma_awrite32(core, BCMA_IOCTL, 1071 bcma_aread32(core, BCMA_IOCTL) & 1072 ~BGMAC_BCMA_IOCTL_SW_RESET); 1073 1074 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1075 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1076 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1077 * be keps until taking MAC out of the reset. 1078 */ 1079 bgmac_cmdcfg_maskset(bgmac, 1080 ~(BGMAC_CMDCFG_TE | 1081 BGMAC_CMDCFG_RE | 1082 BGMAC_CMDCFG_RPI | 1083 BGMAC_CMDCFG_TAI | 1084 BGMAC_CMDCFG_HD | 1085 BGMAC_CMDCFG_ML | 1086 BGMAC_CMDCFG_CFE | 1087 BGMAC_CMDCFG_RL | 1088 BGMAC_CMDCFG_RED | 1089 BGMAC_CMDCFG_PE | 1090 BGMAC_CMDCFG_TPI | 1091 BGMAC_CMDCFG_PAD_EN | 1092 BGMAC_CMDCFG_PF), 1093 BGMAC_CMDCFG_PROM | 1094 BGMAC_CMDCFG_NLC | 1095 BGMAC_CMDCFG_CFE | 1096 BGMAC_CMDCFG_SR(core->id.rev), 1097 false); 1098 bgmac->mac_speed = SPEED_UNKNOWN; 1099 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1100 1101 bgmac_clear_mib(bgmac); 1102 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1103 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1104 BCMA_GMAC_CMN_PC_MTE); 1105 else 1106 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1107 bgmac_miiconfig(bgmac); 1108 bgmac_phy_init(bgmac); 1109 1110 netdev_reset_queue(bgmac->net_dev); 1111 } 1112 1113 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1114 { 1115 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1116 } 1117 1118 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1119 { 1120 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1121 bgmac_read(bgmac, BGMAC_INT_MASK); 1122 } 1123 1124 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1125 static void bgmac_enable(struct bgmac *bgmac) 1126 { 1127 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1128 u32 cmdcfg; 1129 u32 mode; 1130 u32 rxq_ctl; 1131 u32 fl_ctl; 1132 u16 bp_clk; 1133 u8 mdp; 1134 1135 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1136 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1137 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1138 udelay(2); 1139 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1140 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1141 1142 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1143 BGMAC_DS_MM_SHIFT; 1144 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1145 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1146 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1147 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1148 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1149 1150 switch (ci->id) { 1151 case BCMA_CHIP_ID_BCM5357: 1152 case BCMA_CHIP_ID_BCM4749: 1153 case BCMA_CHIP_ID_BCM53572: 1154 case BCMA_CHIP_ID_BCM4716: 1155 case BCMA_CHIP_ID_BCM47162: 1156 fl_ctl = 0x03cb04cb; 1157 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1158 ci->id == BCMA_CHIP_ID_BCM4749 || 1159 ci->id == BCMA_CHIP_ID_BCM53572) 1160 fl_ctl = 0x2300e1; 1161 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1162 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1163 break; 1164 } 1165 1166 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1167 ci->id != BCMA_CHIP_ID_BCM53018) { 1168 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1169 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1170 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1171 1000000; 1172 mdp = (bp_clk * 128 / 1000) - 3; 1173 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1174 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1175 } 1176 } 1177 1178 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1179 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1180 { 1181 struct bgmac_dma_ring *ring; 1182 int i; 1183 1184 /* 1 interrupt per received frame */ 1185 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1186 1187 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1188 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1189 1190 bgmac_set_rx_mode(bgmac->net_dev); 1191 1192 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1193 1194 if (bgmac->loopback) 1195 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1196 else 1197 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1198 1199 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1200 1201 if (full_init) { 1202 bgmac_dma_init(bgmac); 1203 if (1) /* FIXME: is there any case we don't want IRQs? */ 1204 bgmac_chip_intrs_on(bgmac); 1205 } else { 1206 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1207 ring = &bgmac->rx_ring[i]; 1208 bgmac_dma_rx_enable(bgmac, ring); 1209 } 1210 } 1211 1212 bgmac_enable(bgmac); 1213 } 1214 1215 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1216 { 1217 struct bgmac *bgmac = netdev_priv(dev_id); 1218 1219 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1220 int_status &= bgmac->int_mask; 1221 1222 if (!int_status) 1223 return IRQ_NONE; 1224 1225 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1226 if (int_status) 1227 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); 1228 1229 /* Disable new interrupts until handling existing ones */ 1230 bgmac_chip_intrs_off(bgmac); 1231 1232 napi_schedule(&bgmac->napi); 1233 1234 return IRQ_HANDLED; 1235 } 1236 1237 static int bgmac_poll(struct napi_struct *napi, int weight) 1238 { 1239 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1240 int handled = 0; 1241 1242 /* Ack */ 1243 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1244 1245 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1246 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1247 1248 /* Poll again if more events arrived in the meantime */ 1249 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1250 return handled; 1251 1252 if (handled < weight) { 1253 napi_complete(napi); 1254 bgmac_chip_intrs_on(bgmac); 1255 } 1256 1257 return handled; 1258 } 1259 1260 /************************************************** 1261 * net_device_ops 1262 **************************************************/ 1263 1264 static int bgmac_open(struct net_device *net_dev) 1265 { 1266 struct bgmac *bgmac = netdev_priv(net_dev); 1267 int err = 0; 1268 1269 bgmac_chip_reset(bgmac); 1270 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1271 bgmac_chip_init(bgmac, true); 1272 1273 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1274 KBUILD_MODNAME, net_dev); 1275 if (err < 0) { 1276 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1277 goto err_out; 1278 } 1279 napi_enable(&bgmac->napi); 1280 1281 phy_start(bgmac->phy_dev); 1282 1283 netif_carrier_on(net_dev); 1284 1285 err_out: 1286 return err; 1287 } 1288 1289 static int bgmac_stop(struct net_device *net_dev) 1290 { 1291 struct bgmac *bgmac = netdev_priv(net_dev); 1292 1293 netif_carrier_off(net_dev); 1294 1295 phy_stop(bgmac->phy_dev); 1296 1297 napi_disable(&bgmac->napi); 1298 bgmac_chip_intrs_off(bgmac); 1299 free_irq(bgmac->core->irq, net_dev); 1300 1301 bgmac_chip_reset(bgmac); 1302 1303 return 0; 1304 } 1305 1306 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1307 struct net_device *net_dev) 1308 { 1309 struct bgmac *bgmac = netdev_priv(net_dev); 1310 struct bgmac_dma_ring *ring; 1311 1312 /* No QOS support yet */ 1313 ring = &bgmac->tx_ring[0]; 1314 return bgmac_dma_tx_add(bgmac, ring, skb); 1315 } 1316 1317 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1318 { 1319 struct bgmac *bgmac = netdev_priv(net_dev); 1320 int ret; 1321 1322 ret = eth_prepare_mac_addr_change(net_dev, addr); 1323 if (ret < 0) 1324 return ret; 1325 bgmac_write_mac_address(bgmac, (u8 *)addr); 1326 eth_commit_mac_addr_change(net_dev, addr); 1327 return 0; 1328 } 1329 1330 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1331 { 1332 struct bgmac *bgmac = netdev_priv(net_dev); 1333 1334 if (!netif_running(net_dev)) 1335 return -EINVAL; 1336 1337 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1338 } 1339 1340 static const struct net_device_ops bgmac_netdev_ops = { 1341 .ndo_open = bgmac_open, 1342 .ndo_stop = bgmac_stop, 1343 .ndo_start_xmit = bgmac_start_xmit, 1344 .ndo_set_rx_mode = bgmac_set_rx_mode, 1345 .ndo_set_mac_address = bgmac_set_mac_address, 1346 .ndo_validate_addr = eth_validate_addr, 1347 .ndo_do_ioctl = bgmac_ioctl, 1348 }; 1349 1350 /************************************************** 1351 * ethtool_ops 1352 **************************************************/ 1353 1354 static int bgmac_get_settings(struct net_device *net_dev, 1355 struct ethtool_cmd *cmd) 1356 { 1357 struct bgmac *bgmac = netdev_priv(net_dev); 1358 1359 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1360 } 1361 1362 static int bgmac_set_settings(struct net_device *net_dev, 1363 struct ethtool_cmd *cmd) 1364 { 1365 struct bgmac *bgmac = netdev_priv(net_dev); 1366 1367 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1368 } 1369 1370 static void bgmac_get_drvinfo(struct net_device *net_dev, 1371 struct ethtool_drvinfo *info) 1372 { 1373 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1374 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1375 } 1376 1377 static const struct ethtool_ops bgmac_ethtool_ops = { 1378 .get_settings = bgmac_get_settings, 1379 .set_settings = bgmac_set_settings, 1380 .get_drvinfo = bgmac_get_drvinfo, 1381 }; 1382 1383 /************************************************** 1384 * MII 1385 **************************************************/ 1386 1387 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1388 { 1389 return bgmac_phy_read(bus->priv, mii_id, regnum); 1390 } 1391 1392 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1393 u16 value) 1394 { 1395 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1396 } 1397 1398 static void bgmac_adjust_link(struct net_device *net_dev) 1399 { 1400 struct bgmac *bgmac = netdev_priv(net_dev); 1401 struct phy_device *phy_dev = bgmac->phy_dev; 1402 bool update = false; 1403 1404 if (phy_dev->link) { 1405 if (phy_dev->speed != bgmac->mac_speed) { 1406 bgmac->mac_speed = phy_dev->speed; 1407 update = true; 1408 } 1409 1410 if (phy_dev->duplex != bgmac->mac_duplex) { 1411 bgmac->mac_duplex = phy_dev->duplex; 1412 update = true; 1413 } 1414 } 1415 1416 if (update) { 1417 bgmac_mac_speed(bgmac); 1418 phy_print_status(phy_dev); 1419 } 1420 } 1421 1422 static int bgmac_fixed_phy_register(struct bgmac *bgmac) 1423 { 1424 struct fixed_phy_status fphy_status = { 1425 .link = 1, 1426 .speed = SPEED_1000, 1427 .duplex = DUPLEX_FULL, 1428 }; 1429 struct phy_device *phy_dev; 1430 int err; 1431 1432 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 1433 if (!phy_dev || IS_ERR(phy_dev)) { 1434 bgmac_err(bgmac, "Failed to register fixed PHY device\n"); 1435 return -ENODEV; 1436 } 1437 1438 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1439 PHY_INTERFACE_MODE_MII); 1440 if (err) { 1441 bgmac_err(bgmac, "Connecting PHY failed\n"); 1442 return err; 1443 } 1444 1445 bgmac->phy_dev = phy_dev; 1446 1447 return err; 1448 } 1449 1450 static int bgmac_mii_register(struct bgmac *bgmac) 1451 { 1452 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1453 struct mii_bus *mii_bus; 1454 struct phy_device *phy_dev; 1455 char bus_id[MII_BUS_ID_SIZE + 3]; 1456 int i, err = 0; 1457 1458 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1459 ci->id == BCMA_CHIP_ID_BCM53018) 1460 return bgmac_fixed_phy_register(bgmac); 1461 1462 mii_bus = mdiobus_alloc(); 1463 if (!mii_bus) 1464 return -ENOMEM; 1465 1466 mii_bus->name = "bgmac mii bus"; 1467 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1468 bgmac->core->core_unit); 1469 mii_bus->priv = bgmac; 1470 mii_bus->read = bgmac_mii_read; 1471 mii_bus->write = bgmac_mii_write; 1472 mii_bus->parent = &bgmac->core->dev; 1473 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1474 1475 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 1476 if (!mii_bus->irq) { 1477 err = -ENOMEM; 1478 goto err_free_bus; 1479 } 1480 for (i = 0; i < PHY_MAX_ADDR; i++) 1481 mii_bus->irq[i] = PHY_POLL; 1482 1483 err = mdiobus_register(mii_bus); 1484 if (err) { 1485 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1486 goto err_free_irq; 1487 } 1488 1489 bgmac->mii_bus = mii_bus; 1490 1491 /* Connect to the PHY */ 1492 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1493 bgmac->phyaddr); 1494 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1495 PHY_INTERFACE_MODE_MII); 1496 if (IS_ERR(phy_dev)) { 1497 bgmac_err(bgmac, "PHY connecton failed\n"); 1498 err = PTR_ERR(phy_dev); 1499 goto err_unregister_bus; 1500 } 1501 bgmac->phy_dev = phy_dev; 1502 1503 return err; 1504 1505 err_unregister_bus: 1506 mdiobus_unregister(mii_bus); 1507 err_free_irq: 1508 kfree(mii_bus->irq); 1509 err_free_bus: 1510 mdiobus_free(mii_bus); 1511 return err; 1512 } 1513 1514 static void bgmac_mii_unregister(struct bgmac *bgmac) 1515 { 1516 struct mii_bus *mii_bus = bgmac->mii_bus; 1517 1518 mdiobus_unregister(mii_bus); 1519 kfree(mii_bus->irq); 1520 mdiobus_free(mii_bus); 1521 } 1522 1523 /************************************************** 1524 * BCMA bus ops 1525 **************************************************/ 1526 1527 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1528 static int bgmac_probe(struct bcma_device *core) 1529 { 1530 struct bcma_chipinfo *ci = &core->bus->chipinfo; 1531 struct net_device *net_dev; 1532 struct bgmac *bgmac; 1533 struct ssb_sprom *sprom = &core->bus->sprom; 1534 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1535 int err; 1536 1537 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1538 if (core->core_unit > 1) { 1539 pr_err("Unsupported core_unit %d\n", core->core_unit); 1540 return -ENOTSUPP; 1541 } 1542 1543 if (!is_valid_ether_addr(mac)) { 1544 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1545 eth_random_addr(mac); 1546 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1547 } 1548 1549 /* Allocation and references */ 1550 net_dev = alloc_etherdev(sizeof(*bgmac)); 1551 if (!net_dev) 1552 return -ENOMEM; 1553 net_dev->netdev_ops = &bgmac_netdev_ops; 1554 net_dev->irq = core->irq; 1555 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1556 bgmac = netdev_priv(net_dev); 1557 bgmac->net_dev = net_dev; 1558 bgmac->core = core; 1559 bcma_set_drvdata(core, bgmac); 1560 1561 /* Defaults */ 1562 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1563 1564 /* On BCM4706 we need common core to access PHY */ 1565 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1566 !core->bus->drv_gmac_cmn.core) { 1567 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1568 err = -ENODEV; 1569 goto err_netdev_free; 1570 } 1571 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1572 1573 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1574 sprom->et0phyaddr; 1575 bgmac->phyaddr &= BGMAC_PHY_MASK; 1576 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1577 bgmac_err(bgmac, "No PHY found\n"); 1578 err = -ENODEV; 1579 goto err_netdev_free; 1580 } 1581 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1582 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1583 1584 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1585 bgmac_err(bgmac, "PCI setup not implemented\n"); 1586 err = -ENOTSUPP; 1587 goto err_netdev_free; 1588 } 1589 1590 bgmac_chip_reset(bgmac); 1591 1592 /* For Northstar, we have to take all GMAC core out of reset */ 1593 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1594 ci->id == BCMA_CHIP_ID_BCM53018) { 1595 struct bcma_device *ns_core; 1596 int ns_gmac; 1597 1598 /* Northstar has 4 GMAC cores */ 1599 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1600 /* As Northstar requirement, we have to reset all GMACs 1601 * before accessing one. bgmac_chip_reset() call 1602 * bcma_core_enable() for this core. Then the other 1603 * three GMACs didn't reset. We do it here. 1604 */ 1605 ns_core = bcma_find_core_unit(core->bus, 1606 BCMA_CORE_MAC_GBIT, 1607 ns_gmac); 1608 if (ns_core && !bcma_core_is_enabled(ns_core)) 1609 bcma_core_enable(ns_core, 0); 1610 } 1611 } 1612 1613 err = bgmac_dma_alloc(bgmac); 1614 if (err) { 1615 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1616 goto err_netdev_free; 1617 } 1618 1619 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1620 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1621 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1622 1623 /* TODO: reset the external phy. Specs are needed */ 1624 bgmac_phy_reset(bgmac); 1625 1626 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1627 BGMAC_BFL_ENETROBO); 1628 if (bgmac->has_robosw) 1629 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1630 1631 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1632 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1633 1634 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1635 1636 err = bgmac_mii_register(bgmac); 1637 if (err) { 1638 bgmac_err(bgmac, "Cannot register MDIO\n"); 1639 goto err_dma_free; 1640 } 1641 1642 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1643 net_dev->hw_features = net_dev->features; 1644 net_dev->vlan_features = net_dev->features; 1645 1646 err = register_netdev(bgmac->net_dev); 1647 if (err) { 1648 bgmac_err(bgmac, "Cannot register net device\n"); 1649 goto err_mii_unregister; 1650 } 1651 1652 netif_carrier_off(net_dev); 1653 1654 return 0; 1655 1656 err_mii_unregister: 1657 bgmac_mii_unregister(bgmac); 1658 err_dma_free: 1659 bgmac_dma_free(bgmac); 1660 1661 err_netdev_free: 1662 bcma_set_drvdata(core, NULL); 1663 free_netdev(net_dev); 1664 1665 return err; 1666 } 1667 1668 static void bgmac_remove(struct bcma_device *core) 1669 { 1670 struct bgmac *bgmac = bcma_get_drvdata(core); 1671 1672 unregister_netdev(bgmac->net_dev); 1673 bgmac_mii_unregister(bgmac); 1674 netif_napi_del(&bgmac->napi); 1675 bgmac_dma_free(bgmac); 1676 bcma_set_drvdata(core, NULL); 1677 free_netdev(bgmac->net_dev); 1678 } 1679 1680 static struct bcma_driver bgmac_bcma_driver = { 1681 .name = KBUILD_MODNAME, 1682 .id_table = bgmac_bcma_tbl, 1683 .probe = bgmac_probe, 1684 .remove = bgmac_remove, 1685 }; 1686 1687 static int __init bgmac_init(void) 1688 { 1689 int err; 1690 1691 err = bcma_driver_register(&bgmac_bcma_driver); 1692 if (err) 1693 return err; 1694 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1695 1696 return 0; 1697 } 1698 1699 static void __exit bgmac_exit(void) 1700 { 1701 bcma_driver_unregister(&bgmac_bcma_driver); 1702 } 1703 1704 module_init(bgmac_init) 1705 module_exit(bgmac_exit) 1706 1707 MODULE_AUTHOR("Rafał Miłecki"); 1708 MODULE_LICENSE("GPL"); 1709