1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <bcm47xx_nvram.h> 21 22 static const struct bcma_device_id bgmac_bcma_tbl[] = { 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 28 29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 30 u32 value, int timeout) 31 { 32 u32 val; 33 int i; 34 35 for (i = 0; i < timeout / 10; i++) { 36 val = bcma_read32(core, reg); 37 if ((val & mask) == value) 38 return true; 39 udelay(10); 40 } 41 pr_err("Timeout waiting for reg 0x%X\n", reg); 42 return false; 43 } 44 45 /************************************************** 46 * DMA 47 **************************************************/ 48 49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 50 { 51 u32 val; 52 int i; 53 54 if (!ring->mmio_base) 55 return; 56 57 /* Suspend DMA TX ring first. 58 * bgmac_wait_value doesn't support waiting for any of few values, so 59 * implement whole loop here. 60 */ 61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 62 BGMAC_DMA_TX_SUSPEND); 63 for (i = 0; i < 10000 / 10; i++) { 64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 65 val &= BGMAC_DMA_TX_STAT; 66 if (val == BGMAC_DMA_TX_STAT_DISABLED || 67 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 68 val == BGMAC_DMA_TX_STAT_STOPPED) { 69 i = 0; 70 break; 71 } 72 udelay(10); 73 } 74 if (i) 75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 76 ring->mmio_base, val); 77 78 /* Remove SUSPEND bit */ 79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 80 if (!bgmac_wait_value(bgmac->core, 81 ring->mmio_base + BGMAC_DMA_TX_STATUS, 82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 83 10000)) { 84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 85 ring->mmio_base); 86 udelay(300); 87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 90 ring->mmio_base); 91 } 92 } 93 94 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 95 struct bgmac_dma_ring *ring) 96 { 97 u32 ctl; 98 99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 100 if (bgmac->core->id.rev >= 4) { 101 ctl &= ~BGMAC_DMA_TX_BL_MASK; 102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 103 104 ctl &= ~BGMAC_DMA_TX_MR_MASK; 105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 106 107 ctl &= ~BGMAC_DMA_TX_PC_MASK; 108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 109 110 ctl &= ~BGMAC_DMA_TX_PT_MASK; 111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 112 } 113 ctl |= BGMAC_DMA_TX_ENABLE; 114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 116 } 117 118 static void 119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 120 int i, int len, u32 ctl0) 121 { 122 struct bgmac_slot_info *slot; 123 struct bgmac_dma_desc *dma_desc; 124 u32 ctl1; 125 126 if (i == ring->num_slots - 1) 127 ctl0 |= BGMAC_DESC_CTL0_EOT; 128 129 ctl1 = len & BGMAC_DESC_CTL1_LEN; 130 131 slot = &ring->slots[i]; 132 dma_desc = &ring->cpu_base[i]; 133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 135 dma_desc->ctl0 = cpu_to_le32(ctl0); 136 dma_desc->ctl1 = cpu_to_le32(ctl1); 137 } 138 139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 140 struct bgmac_dma_ring *ring, 141 struct sk_buff *skb) 142 { 143 struct device *dma_dev = bgmac->core->dma_dev; 144 struct net_device *net_dev = bgmac->net_dev; 145 int index = ring->end % BGMAC_TX_RING_SLOTS; 146 struct bgmac_slot_info *slot = &ring->slots[index]; 147 int nr_frags; 148 u32 flags; 149 int i; 150 151 if (skb->len > BGMAC_DESC_CTL1_LEN) { 152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 153 goto err_drop; 154 } 155 156 if (skb->ip_summed == CHECKSUM_PARTIAL) 157 skb_checksum_help(skb); 158 159 nr_frags = skb_shinfo(skb)->nr_frags; 160 161 /* ring->end - ring->start will return the number of valid slots, 162 * even when ring->end overflows 163 */ 164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 166 netif_stop_queue(net_dev); 167 return NETDEV_TX_BUSY; 168 } 169 170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 171 DMA_TO_DEVICE); 172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 173 goto err_dma_head; 174 175 flags = BGMAC_DESC_CTL0_SOF; 176 if (!nr_frags) 177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 178 179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 180 flags = 0; 181 182 for (i = 0; i < nr_frags; i++) { 183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 184 int len = skb_frag_size(frag); 185 186 index = (index + 1) % BGMAC_TX_RING_SLOTS; 187 slot = &ring->slots[index]; 188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 189 len, DMA_TO_DEVICE); 190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 191 goto err_dma; 192 193 if (i == nr_frags - 1) 194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 195 196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 197 } 198 199 slot->skb = skb; 200 ring->end += nr_frags + 1; 201 netdev_sent_queue(net_dev, skb->len); 202 203 wmb(); 204 205 /* Increase ring->end to point empty slot. We tell hardware the first 206 * slot it should *not* read. 207 */ 208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 209 ring->index_base + 210 (ring->end % BGMAC_TX_RING_SLOTS) * 211 sizeof(struct bgmac_dma_desc)); 212 213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 214 netif_stop_queue(net_dev); 215 216 return NETDEV_TX_OK; 217 218 err_dma: 219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 220 DMA_TO_DEVICE); 221 222 while (i > 0) { 223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 224 struct bgmac_slot_info *slot = &ring->slots[index]; 225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 226 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 227 228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 229 } 230 231 err_dma_head: 232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 233 ring->mmio_base); 234 235 err_drop: 236 dev_kfree_skb(skb); 237 return NETDEV_TX_OK; 238 } 239 240 /* Free transmitted packets */ 241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 242 { 243 struct device *dma_dev = bgmac->core->dma_dev; 244 int empty_slot; 245 bool freed = false; 246 unsigned bytes_compl = 0, pkts_compl = 0; 247 248 /* The last slot that hardware didn't consume yet */ 249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 250 empty_slot &= BGMAC_DMA_TX_STATDPTR; 251 empty_slot -= ring->index_base; 252 empty_slot &= BGMAC_DMA_TX_STATDPTR; 253 empty_slot /= sizeof(struct bgmac_dma_desc); 254 255 while (ring->start != ring->end) { 256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 257 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 258 u32 ctl1; 259 int len; 260 261 if (slot_idx == empty_slot) 262 break; 263 264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 265 len = ctl1 & BGMAC_DESC_CTL1_LEN; 266 if (ctl1 & BGMAC_DESC_CTL0_SOF) 267 /* Unmap no longer used buffer */ 268 dma_unmap_single(dma_dev, slot->dma_addr, len, 269 DMA_TO_DEVICE); 270 else 271 dma_unmap_page(dma_dev, slot->dma_addr, len, 272 DMA_TO_DEVICE); 273 274 if (slot->skb) { 275 bytes_compl += slot->skb->len; 276 pkts_compl++; 277 278 /* Free memory! :) */ 279 dev_kfree_skb(slot->skb); 280 slot->skb = NULL; 281 } 282 283 slot->dma_addr = 0; 284 ring->start++; 285 freed = true; 286 } 287 288 if (!pkts_compl) 289 return; 290 291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 292 293 if (netif_queue_stopped(bgmac->net_dev)) 294 netif_wake_queue(bgmac->net_dev); 295 } 296 297 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 298 { 299 if (!ring->mmio_base) 300 return; 301 302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 303 if (!bgmac_wait_value(bgmac->core, 304 ring->mmio_base + BGMAC_DMA_RX_STATUS, 305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 306 10000)) 307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 308 ring->mmio_base); 309 } 310 311 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 312 struct bgmac_dma_ring *ring) 313 { 314 u32 ctl; 315 316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 317 if (bgmac->core->id.rev >= 4) { 318 ctl &= ~BGMAC_DMA_RX_BL_MASK; 319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 320 321 ctl &= ~BGMAC_DMA_RX_PC_MASK; 322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 323 324 ctl &= ~BGMAC_DMA_RX_PT_MASK; 325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 326 } 327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 328 ctl |= BGMAC_DMA_RX_ENABLE; 329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 333 } 334 335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 336 struct bgmac_slot_info *slot) 337 { 338 struct device *dma_dev = bgmac->core->dma_dev; 339 dma_addr_t dma_addr; 340 struct bgmac_rx_header *rx; 341 void *buf; 342 343 /* Alloc skb */ 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 345 if (!buf) 346 return -ENOMEM; 347 348 /* Poison - if everything goes fine, hardware will overwrite it */ 349 rx = buf + BGMAC_RX_BUF_OFFSET; 350 rx->len = cpu_to_le16(0xdead); 351 rx->flags = cpu_to_le16(0xbeef); 352 353 /* Map skb for the DMA */ 354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 356 if (dma_mapping_error(dma_dev, dma_addr)) { 357 bgmac_err(bgmac, "DMA mapping error\n"); 358 put_page(virt_to_head_page(buf)); 359 return -ENOMEM; 360 } 361 362 /* Update the slot */ 363 slot->buf = buf; 364 slot->dma_addr = dma_addr; 365 366 return 0; 367 } 368 369 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 370 struct bgmac_dma_ring *ring, int desc_idx) 371 { 372 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 373 u32 ctl0 = 0, ctl1 = 0; 374 375 if (desc_idx == ring->num_slots - 1) 376 ctl0 |= BGMAC_DESC_CTL0_EOT; 377 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 378 /* Is there any BGMAC device that requires extension? */ 379 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 380 * B43_DMA64_DCTL1_ADDREXT_MASK; 381 */ 382 383 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 384 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 385 dma_desc->ctl0 = cpu_to_le32(ctl0); 386 dma_desc->ctl1 = cpu_to_le32(ctl1); 387 } 388 389 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 390 int weight) 391 { 392 u32 end_slot; 393 int handled = 0; 394 395 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 396 end_slot &= BGMAC_DMA_RX_STATDPTR; 397 end_slot -= ring->index_base; 398 end_slot &= BGMAC_DMA_RX_STATDPTR; 399 end_slot /= sizeof(struct bgmac_dma_desc); 400 401 ring->end = end_slot; 402 403 while (ring->start != ring->end) { 404 struct device *dma_dev = bgmac->core->dma_dev; 405 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 406 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 407 struct sk_buff *skb; 408 void *buf = slot->buf; 409 u16 len, flags; 410 411 /* Unmap buffer to make it accessible to the CPU */ 412 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, 413 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 414 415 /* Get info from the header */ 416 len = le16_to_cpu(rx->len); 417 flags = le16_to_cpu(rx->flags); 418 419 do { 420 dma_addr_t old_dma_addr = slot->dma_addr; 421 int err; 422 423 /* Check for poison and drop or pass the packet */ 424 if (len == 0xdead && flags == 0xbeef) { 425 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 426 ring->start); 427 dma_sync_single_for_device(dma_dev, 428 slot->dma_addr, 429 BGMAC_RX_BUF_SIZE, 430 DMA_FROM_DEVICE); 431 break; 432 } 433 434 /* Omit CRC. */ 435 len -= ETH_FCS_LEN; 436 437 /* Prepare new skb as replacement */ 438 err = bgmac_dma_rx_skb_for_slot(bgmac, slot); 439 if (err) { 440 /* Poison the old skb */ 441 rx->len = cpu_to_le16(0xdead); 442 rx->flags = cpu_to_le16(0xbeef); 443 444 dma_sync_single_for_device(dma_dev, 445 slot->dma_addr, 446 BGMAC_RX_BUF_SIZE, 447 DMA_FROM_DEVICE); 448 break; 449 } 450 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 451 452 /* Unmap old skb, we'll pass it to the netfif */ 453 dma_unmap_single(dma_dev, old_dma_addr, 454 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 455 456 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 457 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 458 BGMAC_RX_BUF_OFFSET + len); 459 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 460 BGMAC_RX_BUF_OFFSET); 461 462 skb_checksum_none_assert(skb); 463 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 464 napi_gro_receive(&bgmac->napi, skb); 465 handled++; 466 } while (0); 467 468 if (++ring->start >= BGMAC_RX_RING_SLOTS) 469 ring->start = 0; 470 471 if (handled >= weight) /* Should never be greater */ 472 break; 473 } 474 475 return handled; 476 } 477 478 /* Does ring support unaligned addressing? */ 479 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 480 struct bgmac_dma_ring *ring, 481 enum bgmac_dma_ring_type ring_type) 482 { 483 switch (ring_type) { 484 case BGMAC_DMA_RING_TX: 485 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 486 0xff0); 487 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 488 return true; 489 break; 490 case BGMAC_DMA_RING_RX: 491 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 492 0xff0); 493 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 494 return true; 495 break; 496 } 497 return false; 498 } 499 500 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 501 struct bgmac_dma_ring *ring) 502 { 503 struct device *dma_dev = bgmac->core->dma_dev; 504 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 505 struct bgmac_slot_info *slot; 506 int i; 507 508 for (i = 0; i < ring->num_slots; i++) { 509 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 510 511 slot = &ring->slots[i]; 512 dev_kfree_skb(slot->skb); 513 514 if (!slot->dma_addr) 515 continue; 516 517 if (slot->skb) 518 dma_unmap_single(dma_dev, slot->dma_addr, 519 len, DMA_TO_DEVICE); 520 else 521 dma_unmap_page(dma_dev, slot->dma_addr, 522 len, DMA_TO_DEVICE); 523 } 524 } 525 526 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 527 struct bgmac_dma_ring *ring) 528 { 529 struct device *dma_dev = bgmac->core->dma_dev; 530 struct bgmac_slot_info *slot; 531 int i; 532 533 for (i = 0; i < ring->num_slots; i++) { 534 slot = &ring->slots[i]; 535 if (!slot->buf) 536 continue; 537 538 if (slot->dma_addr) 539 dma_unmap_single(dma_dev, slot->dma_addr, 540 BGMAC_RX_BUF_SIZE, 541 DMA_FROM_DEVICE); 542 put_page(virt_to_head_page(slot->buf)); 543 } 544 } 545 546 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 547 struct bgmac_dma_ring *ring) 548 { 549 struct device *dma_dev = bgmac->core->dma_dev; 550 int size; 551 552 if (!ring->cpu_base) 553 return; 554 555 /* Free ring of descriptors */ 556 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 557 dma_free_coherent(dma_dev, size, ring->cpu_base, 558 ring->dma_base); 559 } 560 561 static void bgmac_dma_free(struct bgmac *bgmac) 562 { 563 int i; 564 565 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 566 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 567 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); 568 } 569 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 570 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 571 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); 572 } 573 } 574 575 static int bgmac_dma_alloc(struct bgmac *bgmac) 576 { 577 struct device *dma_dev = bgmac->core->dma_dev; 578 struct bgmac_dma_ring *ring; 579 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 580 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 581 int size; /* ring size: different for Tx and Rx */ 582 int err; 583 int i; 584 585 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 586 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 587 588 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 589 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 590 return -ENOTSUPP; 591 } 592 593 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 594 ring = &bgmac->tx_ring[i]; 595 ring->num_slots = BGMAC_TX_RING_SLOTS; 596 ring->mmio_base = ring_base[i]; 597 598 /* Alloc ring of descriptors */ 599 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 600 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 601 &ring->dma_base, 602 GFP_KERNEL); 603 if (!ring->cpu_base) { 604 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 605 ring->mmio_base); 606 goto err_dma_free; 607 } 608 609 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 610 BGMAC_DMA_RING_TX); 611 if (ring->unaligned) 612 ring->index_base = lower_32_bits(ring->dma_base); 613 else 614 ring->index_base = 0; 615 616 /* No need to alloc TX slots yet */ 617 } 618 619 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 620 int j; 621 622 ring = &bgmac->rx_ring[i]; 623 ring->num_slots = BGMAC_RX_RING_SLOTS; 624 ring->mmio_base = ring_base[i]; 625 626 /* Alloc ring of descriptors */ 627 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 628 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 629 &ring->dma_base, 630 GFP_KERNEL); 631 if (!ring->cpu_base) { 632 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 633 ring->mmio_base); 634 err = -ENOMEM; 635 goto err_dma_free; 636 } 637 638 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 639 BGMAC_DMA_RING_RX); 640 if (ring->unaligned) 641 ring->index_base = lower_32_bits(ring->dma_base); 642 else 643 ring->index_base = 0; 644 645 /* Alloc RX slots */ 646 for (j = 0; j < ring->num_slots; j++) { 647 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 648 if (err) { 649 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 650 goto err_dma_free; 651 } 652 } 653 } 654 655 return 0; 656 657 err_dma_free: 658 bgmac_dma_free(bgmac); 659 return -ENOMEM; 660 } 661 662 static void bgmac_dma_init(struct bgmac *bgmac) 663 { 664 struct bgmac_dma_ring *ring; 665 int i; 666 667 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 668 ring = &bgmac->tx_ring[i]; 669 670 if (!ring->unaligned) 671 bgmac_dma_tx_enable(bgmac, ring); 672 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 673 lower_32_bits(ring->dma_base)); 674 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 675 upper_32_bits(ring->dma_base)); 676 if (ring->unaligned) 677 bgmac_dma_tx_enable(bgmac, ring); 678 679 ring->start = 0; 680 ring->end = 0; /* Points the slot that should *not* be read */ 681 } 682 683 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 684 int j; 685 686 ring = &bgmac->rx_ring[i]; 687 688 if (!ring->unaligned) 689 bgmac_dma_rx_enable(bgmac, ring); 690 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 691 lower_32_bits(ring->dma_base)); 692 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 693 upper_32_bits(ring->dma_base)); 694 if (ring->unaligned) 695 bgmac_dma_rx_enable(bgmac, ring); 696 697 for (j = 0; j < ring->num_slots; j++) 698 bgmac_dma_rx_setup_desc(bgmac, ring, j); 699 700 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 701 ring->index_base + 702 ring->num_slots * sizeof(struct bgmac_dma_desc)); 703 704 ring->start = 0; 705 ring->end = 0; 706 } 707 } 708 709 /************************************************** 710 * PHY ops 711 **************************************************/ 712 713 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 714 { 715 struct bcma_device *core; 716 u16 phy_access_addr; 717 u16 phy_ctl_addr; 718 u32 tmp; 719 720 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 721 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 722 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 723 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 724 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 725 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 726 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 727 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 728 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 729 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 730 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 731 732 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 733 core = bgmac->core->bus->drv_gmac_cmn.core; 734 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 735 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 736 } else { 737 core = bgmac->core; 738 phy_access_addr = BGMAC_PHY_ACCESS; 739 phy_ctl_addr = BGMAC_PHY_CNTL; 740 } 741 742 tmp = bcma_read32(core, phy_ctl_addr); 743 tmp &= ~BGMAC_PC_EPA_MASK; 744 tmp |= phyaddr; 745 bcma_write32(core, phy_ctl_addr, tmp); 746 747 tmp = BGMAC_PA_START; 748 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 749 tmp |= reg << BGMAC_PA_REG_SHIFT; 750 bcma_write32(core, phy_access_addr, tmp); 751 752 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 753 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 754 phyaddr, reg); 755 return 0xffff; 756 } 757 758 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 759 } 760 761 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 762 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 763 { 764 struct bcma_device *core; 765 u16 phy_access_addr; 766 u16 phy_ctl_addr; 767 u32 tmp; 768 769 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 770 core = bgmac->core->bus->drv_gmac_cmn.core; 771 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 772 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 773 } else { 774 core = bgmac->core; 775 phy_access_addr = BGMAC_PHY_ACCESS; 776 phy_ctl_addr = BGMAC_PHY_CNTL; 777 } 778 779 tmp = bcma_read32(core, phy_ctl_addr); 780 tmp &= ~BGMAC_PC_EPA_MASK; 781 tmp |= phyaddr; 782 bcma_write32(core, phy_ctl_addr, tmp); 783 784 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 785 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 786 bgmac_warn(bgmac, "Error setting MDIO int\n"); 787 788 tmp = BGMAC_PA_START; 789 tmp |= BGMAC_PA_WRITE; 790 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 791 tmp |= reg << BGMAC_PA_REG_SHIFT; 792 tmp |= value; 793 bcma_write32(core, phy_access_addr, tmp); 794 795 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 796 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 797 phyaddr, reg); 798 return -ETIMEDOUT; 799 } 800 801 return 0; 802 } 803 804 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 805 static void bgmac_phy_init(struct bgmac *bgmac) 806 { 807 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 808 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 809 u8 i; 810 811 if (ci->id == BCMA_CHIP_ID_BCM5356) { 812 for (i = 0; i < 5; i++) { 813 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 814 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 815 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 816 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 817 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 818 } 819 } 820 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 821 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 822 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 823 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 824 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 825 for (i = 0; i < 5; i++) { 826 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 827 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 828 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 829 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 830 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 831 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 832 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 833 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 834 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 835 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 836 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 837 } 838 } 839 } 840 841 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 842 static void bgmac_phy_reset(struct bgmac *bgmac) 843 { 844 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 845 return; 846 847 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 848 udelay(100); 849 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 850 bgmac_err(bgmac, "PHY reset failed\n"); 851 bgmac_phy_init(bgmac); 852 } 853 854 /************************************************** 855 * Chip ops 856 **************************************************/ 857 858 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 859 * nothing to change? Try if after stabilizng driver. 860 */ 861 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 862 bool force) 863 { 864 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 865 u32 new_val = (cmdcfg & mask) | set; 866 867 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 868 udelay(2); 869 870 if (new_val != cmdcfg || force) 871 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 872 873 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 874 udelay(2); 875 } 876 877 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 878 { 879 u32 tmp; 880 881 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 882 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 883 tmp = (addr[4] << 8) | addr[5]; 884 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 885 } 886 887 static void bgmac_set_rx_mode(struct net_device *net_dev) 888 { 889 struct bgmac *bgmac = netdev_priv(net_dev); 890 891 if (net_dev->flags & IFF_PROMISC) 892 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 893 else 894 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 895 } 896 897 #if 0 /* We don't use that regs yet */ 898 static void bgmac_chip_stats_update(struct bgmac *bgmac) 899 { 900 int i; 901 902 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 903 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 904 bgmac->mib_tx_regs[i] = 905 bgmac_read(bgmac, 906 BGMAC_TX_GOOD_OCTETS + (i * 4)); 907 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 908 bgmac->mib_rx_regs[i] = 909 bgmac_read(bgmac, 910 BGMAC_RX_GOOD_OCTETS + (i * 4)); 911 } 912 913 /* TODO: what else? how to handle BCM4706? Specs are needed */ 914 } 915 #endif 916 917 static void bgmac_clear_mib(struct bgmac *bgmac) 918 { 919 int i; 920 921 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 922 return; 923 924 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 925 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 926 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 927 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 928 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 929 } 930 931 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 932 static void bgmac_mac_speed(struct bgmac *bgmac) 933 { 934 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 935 u32 set = 0; 936 937 switch (bgmac->mac_speed) { 938 case SPEED_10: 939 set |= BGMAC_CMDCFG_ES_10; 940 break; 941 case SPEED_100: 942 set |= BGMAC_CMDCFG_ES_100; 943 break; 944 case SPEED_1000: 945 set |= BGMAC_CMDCFG_ES_1000; 946 break; 947 case SPEED_2500: 948 set |= BGMAC_CMDCFG_ES_2500; 949 break; 950 default: 951 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 952 } 953 954 if (bgmac->mac_duplex == DUPLEX_HALF) 955 set |= BGMAC_CMDCFG_HD; 956 957 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 958 } 959 960 static void bgmac_miiconfig(struct bgmac *bgmac) 961 { 962 struct bcma_device *core = bgmac->core; 963 struct bcma_chipinfo *ci = &core->bus->chipinfo; 964 u8 imode; 965 966 if (ci->id == BCMA_CHIP_ID_BCM4707 || 967 ci->id == BCMA_CHIP_ID_BCM53018) { 968 bcma_awrite32(core, BCMA_IOCTL, 969 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 970 BGMAC_BCMA_IOCTL_SW_CLKEN); 971 bgmac->mac_speed = SPEED_2500; 972 bgmac->mac_duplex = DUPLEX_FULL; 973 bgmac_mac_speed(bgmac); 974 } else { 975 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 976 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 977 if (imode == 0 || imode == 1) { 978 bgmac->mac_speed = SPEED_100; 979 bgmac->mac_duplex = DUPLEX_FULL; 980 bgmac_mac_speed(bgmac); 981 } 982 } 983 } 984 985 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 986 static void bgmac_chip_reset(struct bgmac *bgmac) 987 { 988 struct bcma_device *core = bgmac->core; 989 struct bcma_bus *bus = core->bus; 990 struct bcma_chipinfo *ci = &bus->chipinfo; 991 u32 flags; 992 u32 iost; 993 int i; 994 995 if (bcma_core_is_enabled(core)) { 996 if (!bgmac->stats_grabbed) { 997 /* bgmac_chip_stats_update(bgmac); */ 998 bgmac->stats_grabbed = true; 999 } 1000 1001 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 1002 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 1003 1004 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1005 udelay(1); 1006 1007 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 1008 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 1009 1010 /* TODO: Clear software multicast filter list */ 1011 } 1012 1013 iost = bcma_aread32(core, BCMA_IOST); 1014 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1015 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1016 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 1017 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 1018 1019 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ 1020 if (ci->id != BCMA_CHIP_ID_BCM4707) { 1021 flags = 0; 1022 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 1023 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 1024 if (!bgmac->has_robosw) 1025 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 1026 } 1027 bcma_core_enable(core, flags); 1028 } 1029 1030 /* Request Misc PLL for corerev > 2 */ 1031 if (core->id.rev > 2 && 1032 ci->id != BCMA_CHIP_ID_BCM4707 && 1033 ci->id != BCMA_CHIP_ID_BCM53018) { 1034 bgmac_set(bgmac, BCMA_CLKCTLST, 1035 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 1036 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1037 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1038 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1039 1000); 1040 } 1041 1042 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1043 ci->id == BCMA_CHIP_ID_BCM4749 || 1044 ci->id == BCMA_CHIP_ID_BCM53572) { 1045 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 1046 u8 et_swtype = 0; 1047 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 1048 BGMAC_CHIPCTL_1_IF_TYPE_MII; 1049 char buf[4]; 1050 1051 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 1052 if (kstrtou8(buf, 0, &et_swtype)) 1053 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 1054 buf); 1055 et_swtype &= 0x0f; 1056 et_swtype <<= 4; 1057 sw_type = et_swtype; 1058 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 1059 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 1060 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1061 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1062 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 1063 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 1064 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 1065 } 1066 bcma_chipco_chipctl_maskset(cc, 1, 1067 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 1068 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 1069 sw_type); 1070 } 1071 1072 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 1073 bcma_awrite32(core, BCMA_IOCTL, 1074 bcma_aread32(core, BCMA_IOCTL) & 1075 ~BGMAC_BCMA_IOCTL_SW_RESET); 1076 1077 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1078 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1079 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1080 * be keps until taking MAC out of the reset. 1081 */ 1082 bgmac_cmdcfg_maskset(bgmac, 1083 ~(BGMAC_CMDCFG_TE | 1084 BGMAC_CMDCFG_RE | 1085 BGMAC_CMDCFG_RPI | 1086 BGMAC_CMDCFG_TAI | 1087 BGMAC_CMDCFG_HD | 1088 BGMAC_CMDCFG_ML | 1089 BGMAC_CMDCFG_CFE | 1090 BGMAC_CMDCFG_RL | 1091 BGMAC_CMDCFG_RED | 1092 BGMAC_CMDCFG_PE | 1093 BGMAC_CMDCFG_TPI | 1094 BGMAC_CMDCFG_PAD_EN | 1095 BGMAC_CMDCFG_PF), 1096 BGMAC_CMDCFG_PROM | 1097 BGMAC_CMDCFG_NLC | 1098 BGMAC_CMDCFG_CFE | 1099 BGMAC_CMDCFG_SR(core->id.rev), 1100 false); 1101 bgmac->mac_speed = SPEED_UNKNOWN; 1102 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1103 1104 bgmac_clear_mib(bgmac); 1105 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1106 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1107 BCMA_GMAC_CMN_PC_MTE); 1108 else 1109 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1110 bgmac_miiconfig(bgmac); 1111 bgmac_phy_init(bgmac); 1112 1113 netdev_reset_queue(bgmac->net_dev); 1114 } 1115 1116 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1117 { 1118 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1119 } 1120 1121 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1122 { 1123 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1124 bgmac_read(bgmac, BGMAC_INT_MASK); 1125 } 1126 1127 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1128 static void bgmac_enable(struct bgmac *bgmac) 1129 { 1130 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1131 u32 cmdcfg; 1132 u32 mode; 1133 u32 rxq_ctl; 1134 u32 fl_ctl; 1135 u16 bp_clk; 1136 u8 mdp; 1137 1138 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1139 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1140 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1141 udelay(2); 1142 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1143 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1144 1145 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1146 BGMAC_DS_MM_SHIFT; 1147 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1148 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1149 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1150 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1151 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1152 1153 switch (ci->id) { 1154 case BCMA_CHIP_ID_BCM5357: 1155 case BCMA_CHIP_ID_BCM4749: 1156 case BCMA_CHIP_ID_BCM53572: 1157 case BCMA_CHIP_ID_BCM4716: 1158 case BCMA_CHIP_ID_BCM47162: 1159 fl_ctl = 0x03cb04cb; 1160 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1161 ci->id == BCMA_CHIP_ID_BCM4749 || 1162 ci->id == BCMA_CHIP_ID_BCM53572) 1163 fl_ctl = 0x2300e1; 1164 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1165 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1166 break; 1167 } 1168 1169 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1170 ci->id != BCMA_CHIP_ID_BCM53018) { 1171 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1172 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1173 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1174 1000000; 1175 mdp = (bp_clk * 128 / 1000) - 3; 1176 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1177 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1178 } 1179 } 1180 1181 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1182 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1183 { 1184 struct bgmac_dma_ring *ring; 1185 int i; 1186 1187 /* 1 interrupt per received frame */ 1188 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1189 1190 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1191 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1192 1193 bgmac_set_rx_mode(bgmac->net_dev); 1194 1195 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1196 1197 if (bgmac->loopback) 1198 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1199 else 1200 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1201 1202 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1203 1204 if (full_init) { 1205 bgmac_dma_init(bgmac); 1206 if (1) /* FIXME: is there any case we don't want IRQs? */ 1207 bgmac_chip_intrs_on(bgmac); 1208 } else { 1209 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1210 ring = &bgmac->rx_ring[i]; 1211 bgmac_dma_rx_enable(bgmac, ring); 1212 } 1213 } 1214 1215 bgmac_enable(bgmac); 1216 } 1217 1218 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1219 { 1220 struct bgmac *bgmac = netdev_priv(dev_id); 1221 1222 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1223 int_status &= bgmac->int_mask; 1224 1225 if (!int_status) 1226 return IRQ_NONE; 1227 1228 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1229 if (int_status) 1230 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); 1231 1232 /* Disable new interrupts until handling existing ones */ 1233 bgmac_chip_intrs_off(bgmac); 1234 1235 napi_schedule(&bgmac->napi); 1236 1237 return IRQ_HANDLED; 1238 } 1239 1240 static int bgmac_poll(struct napi_struct *napi, int weight) 1241 { 1242 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1243 int handled = 0; 1244 1245 /* Ack */ 1246 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1247 1248 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1249 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1250 1251 /* Poll again if more events arrived in the meantime */ 1252 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1253 return handled; 1254 1255 if (handled < weight) { 1256 napi_complete(napi); 1257 bgmac_chip_intrs_on(bgmac); 1258 } 1259 1260 return handled; 1261 } 1262 1263 /************************************************** 1264 * net_device_ops 1265 **************************************************/ 1266 1267 static int bgmac_open(struct net_device *net_dev) 1268 { 1269 struct bgmac *bgmac = netdev_priv(net_dev); 1270 int err = 0; 1271 1272 bgmac_chip_reset(bgmac); 1273 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1274 bgmac_chip_init(bgmac, true); 1275 1276 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1277 KBUILD_MODNAME, net_dev); 1278 if (err < 0) { 1279 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1280 goto err_out; 1281 } 1282 napi_enable(&bgmac->napi); 1283 1284 phy_start(bgmac->phy_dev); 1285 1286 netif_carrier_on(net_dev); 1287 1288 err_out: 1289 return err; 1290 } 1291 1292 static int bgmac_stop(struct net_device *net_dev) 1293 { 1294 struct bgmac *bgmac = netdev_priv(net_dev); 1295 1296 netif_carrier_off(net_dev); 1297 1298 phy_stop(bgmac->phy_dev); 1299 1300 napi_disable(&bgmac->napi); 1301 bgmac_chip_intrs_off(bgmac); 1302 free_irq(bgmac->core->irq, net_dev); 1303 1304 bgmac_chip_reset(bgmac); 1305 1306 return 0; 1307 } 1308 1309 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1310 struct net_device *net_dev) 1311 { 1312 struct bgmac *bgmac = netdev_priv(net_dev); 1313 struct bgmac_dma_ring *ring; 1314 1315 /* No QOS support yet */ 1316 ring = &bgmac->tx_ring[0]; 1317 return bgmac_dma_tx_add(bgmac, ring, skb); 1318 } 1319 1320 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1321 { 1322 struct bgmac *bgmac = netdev_priv(net_dev); 1323 int ret; 1324 1325 ret = eth_prepare_mac_addr_change(net_dev, addr); 1326 if (ret < 0) 1327 return ret; 1328 bgmac_write_mac_address(bgmac, (u8 *)addr); 1329 eth_commit_mac_addr_change(net_dev, addr); 1330 return 0; 1331 } 1332 1333 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1334 { 1335 struct bgmac *bgmac = netdev_priv(net_dev); 1336 1337 if (!netif_running(net_dev)) 1338 return -EINVAL; 1339 1340 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1341 } 1342 1343 static const struct net_device_ops bgmac_netdev_ops = { 1344 .ndo_open = bgmac_open, 1345 .ndo_stop = bgmac_stop, 1346 .ndo_start_xmit = bgmac_start_xmit, 1347 .ndo_set_rx_mode = bgmac_set_rx_mode, 1348 .ndo_set_mac_address = bgmac_set_mac_address, 1349 .ndo_validate_addr = eth_validate_addr, 1350 .ndo_do_ioctl = bgmac_ioctl, 1351 }; 1352 1353 /************************************************** 1354 * ethtool_ops 1355 **************************************************/ 1356 1357 static int bgmac_get_settings(struct net_device *net_dev, 1358 struct ethtool_cmd *cmd) 1359 { 1360 struct bgmac *bgmac = netdev_priv(net_dev); 1361 1362 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1363 } 1364 1365 static int bgmac_set_settings(struct net_device *net_dev, 1366 struct ethtool_cmd *cmd) 1367 { 1368 struct bgmac *bgmac = netdev_priv(net_dev); 1369 1370 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1371 } 1372 1373 static void bgmac_get_drvinfo(struct net_device *net_dev, 1374 struct ethtool_drvinfo *info) 1375 { 1376 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1377 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1378 } 1379 1380 static const struct ethtool_ops bgmac_ethtool_ops = { 1381 .get_settings = bgmac_get_settings, 1382 .set_settings = bgmac_set_settings, 1383 .get_drvinfo = bgmac_get_drvinfo, 1384 }; 1385 1386 /************************************************** 1387 * MII 1388 **************************************************/ 1389 1390 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1391 { 1392 return bgmac_phy_read(bus->priv, mii_id, regnum); 1393 } 1394 1395 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1396 u16 value) 1397 { 1398 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1399 } 1400 1401 static void bgmac_adjust_link(struct net_device *net_dev) 1402 { 1403 struct bgmac *bgmac = netdev_priv(net_dev); 1404 struct phy_device *phy_dev = bgmac->phy_dev; 1405 bool update = false; 1406 1407 if (phy_dev->link) { 1408 if (phy_dev->speed != bgmac->mac_speed) { 1409 bgmac->mac_speed = phy_dev->speed; 1410 update = true; 1411 } 1412 1413 if (phy_dev->duplex != bgmac->mac_duplex) { 1414 bgmac->mac_duplex = phy_dev->duplex; 1415 update = true; 1416 } 1417 } 1418 1419 if (update) { 1420 bgmac_mac_speed(bgmac); 1421 phy_print_status(phy_dev); 1422 } 1423 } 1424 1425 static int bgmac_fixed_phy_register(struct bgmac *bgmac) 1426 { 1427 struct fixed_phy_status fphy_status = { 1428 .link = 1, 1429 .speed = SPEED_1000, 1430 .duplex = DUPLEX_FULL, 1431 }; 1432 struct phy_device *phy_dev; 1433 int err; 1434 1435 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 1436 if (!phy_dev || IS_ERR(phy_dev)) { 1437 bgmac_err(bgmac, "Failed to register fixed PHY device\n"); 1438 return -ENODEV; 1439 } 1440 1441 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1442 PHY_INTERFACE_MODE_MII); 1443 if (err) { 1444 bgmac_err(bgmac, "Connecting PHY failed\n"); 1445 return err; 1446 } 1447 1448 bgmac->phy_dev = phy_dev; 1449 1450 return err; 1451 } 1452 1453 static int bgmac_mii_register(struct bgmac *bgmac) 1454 { 1455 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1456 struct mii_bus *mii_bus; 1457 struct phy_device *phy_dev; 1458 char bus_id[MII_BUS_ID_SIZE + 3]; 1459 int i, err = 0; 1460 1461 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1462 ci->id == BCMA_CHIP_ID_BCM53018) 1463 return bgmac_fixed_phy_register(bgmac); 1464 1465 mii_bus = mdiobus_alloc(); 1466 if (!mii_bus) 1467 return -ENOMEM; 1468 1469 mii_bus->name = "bgmac mii bus"; 1470 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1471 bgmac->core->core_unit); 1472 mii_bus->priv = bgmac; 1473 mii_bus->read = bgmac_mii_read; 1474 mii_bus->write = bgmac_mii_write; 1475 mii_bus->parent = &bgmac->core->dev; 1476 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1477 1478 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 1479 if (!mii_bus->irq) { 1480 err = -ENOMEM; 1481 goto err_free_bus; 1482 } 1483 for (i = 0; i < PHY_MAX_ADDR; i++) 1484 mii_bus->irq[i] = PHY_POLL; 1485 1486 err = mdiobus_register(mii_bus); 1487 if (err) { 1488 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1489 goto err_free_irq; 1490 } 1491 1492 bgmac->mii_bus = mii_bus; 1493 1494 /* Connect to the PHY */ 1495 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1496 bgmac->phyaddr); 1497 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1498 PHY_INTERFACE_MODE_MII); 1499 if (IS_ERR(phy_dev)) { 1500 bgmac_err(bgmac, "PHY connecton failed\n"); 1501 err = PTR_ERR(phy_dev); 1502 goto err_unregister_bus; 1503 } 1504 bgmac->phy_dev = phy_dev; 1505 1506 return err; 1507 1508 err_unregister_bus: 1509 mdiobus_unregister(mii_bus); 1510 err_free_irq: 1511 kfree(mii_bus->irq); 1512 err_free_bus: 1513 mdiobus_free(mii_bus); 1514 return err; 1515 } 1516 1517 static void bgmac_mii_unregister(struct bgmac *bgmac) 1518 { 1519 struct mii_bus *mii_bus = bgmac->mii_bus; 1520 1521 mdiobus_unregister(mii_bus); 1522 kfree(mii_bus->irq); 1523 mdiobus_free(mii_bus); 1524 } 1525 1526 /************************************************** 1527 * BCMA bus ops 1528 **************************************************/ 1529 1530 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1531 static int bgmac_probe(struct bcma_device *core) 1532 { 1533 struct bcma_chipinfo *ci = &core->bus->chipinfo; 1534 struct net_device *net_dev; 1535 struct bgmac *bgmac; 1536 struct ssb_sprom *sprom = &core->bus->sprom; 1537 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1538 int err; 1539 1540 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1541 if (core->core_unit > 1) { 1542 pr_err("Unsupported core_unit %d\n", core->core_unit); 1543 return -ENOTSUPP; 1544 } 1545 1546 if (!is_valid_ether_addr(mac)) { 1547 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1548 eth_random_addr(mac); 1549 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1550 } 1551 1552 /* Allocation and references */ 1553 net_dev = alloc_etherdev(sizeof(*bgmac)); 1554 if (!net_dev) 1555 return -ENOMEM; 1556 net_dev->netdev_ops = &bgmac_netdev_ops; 1557 net_dev->irq = core->irq; 1558 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1559 bgmac = netdev_priv(net_dev); 1560 bgmac->net_dev = net_dev; 1561 bgmac->core = core; 1562 bcma_set_drvdata(core, bgmac); 1563 1564 /* Defaults */ 1565 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1566 1567 /* On BCM4706 we need common core to access PHY */ 1568 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1569 !core->bus->drv_gmac_cmn.core) { 1570 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1571 err = -ENODEV; 1572 goto err_netdev_free; 1573 } 1574 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1575 1576 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1577 sprom->et0phyaddr; 1578 bgmac->phyaddr &= BGMAC_PHY_MASK; 1579 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1580 bgmac_err(bgmac, "No PHY found\n"); 1581 err = -ENODEV; 1582 goto err_netdev_free; 1583 } 1584 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1585 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1586 1587 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1588 bgmac_err(bgmac, "PCI setup not implemented\n"); 1589 err = -ENOTSUPP; 1590 goto err_netdev_free; 1591 } 1592 1593 bgmac_chip_reset(bgmac); 1594 1595 /* For Northstar, we have to take all GMAC core out of reset */ 1596 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1597 ci->id == BCMA_CHIP_ID_BCM53018) { 1598 struct bcma_device *ns_core; 1599 int ns_gmac; 1600 1601 /* Northstar has 4 GMAC cores */ 1602 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1603 /* As Northstar requirement, we have to reset all GMACs 1604 * before accessing one. bgmac_chip_reset() call 1605 * bcma_core_enable() for this core. Then the other 1606 * three GMACs didn't reset. We do it here. 1607 */ 1608 ns_core = bcma_find_core_unit(core->bus, 1609 BCMA_CORE_MAC_GBIT, 1610 ns_gmac); 1611 if (ns_core && !bcma_core_is_enabled(ns_core)) 1612 bcma_core_enable(ns_core, 0); 1613 } 1614 } 1615 1616 err = bgmac_dma_alloc(bgmac); 1617 if (err) { 1618 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1619 goto err_netdev_free; 1620 } 1621 1622 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1623 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1624 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1625 1626 /* TODO: reset the external phy. Specs are needed */ 1627 bgmac_phy_reset(bgmac); 1628 1629 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1630 BGMAC_BFL_ENETROBO); 1631 if (bgmac->has_robosw) 1632 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1633 1634 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1635 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1636 1637 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1638 1639 err = bgmac_mii_register(bgmac); 1640 if (err) { 1641 bgmac_err(bgmac, "Cannot register MDIO\n"); 1642 goto err_dma_free; 1643 } 1644 1645 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1646 net_dev->hw_features = net_dev->features; 1647 net_dev->vlan_features = net_dev->features; 1648 1649 err = register_netdev(bgmac->net_dev); 1650 if (err) { 1651 bgmac_err(bgmac, "Cannot register net device\n"); 1652 goto err_mii_unregister; 1653 } 1654 1655 netif_carrier_off(net_dev); 1656 1657 return 0; 1658 1659 err_mii_unregister: 1660 bgmac_mii_unregister(bgmac); 1661 err_dma_free: 1662 bgmac_dma_free(bgmac); 1663 1664 err_netdev_free: 1665 bcma_set_drvdata(core, NULL); 1666 free_netdev(net_dev); 1667 1668 return err; 1669 } 1670 1671 static void bgmac_remove(struct bcma_device *core) 1672 { 1673 struct bgmac *bgmac = bcma_get_drvdata(core); 1674 1675 unregister_netdev(bgmac->net_dev); 1676 bgmac_mii_unregister(bgmac); 1677 netif_napi_del(&bgmac->napi); 1678 bgmac_dma_free(bgmac); 1679 bcma_set_drvdata(core, NULL); 1680 free_netdev(bgmac->net_dev); 1681 } 1682 1683 static struct bcma_driver bgmac_bcma_driver = { 1684 .name = KBUILD_MODNAME, 1685 .id_table = bgmac_bcma_tbl, 1686 .probe = bgmac_probe, 1687 .remove = bgmac_remove, 1688 }; 1689 1690 static int __init bgmac_init(void) 1691 { 1692 int err; 1693 1694 err = bcma_driver_register(&bgmac_bcma_driver); 1695 if (err) 1696 return err; 1697 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1698 1699 return 0; 1700 } 1701 1702 static void __exit bgmac_exit(void) 1703 { 1704 bcma_driver_unregister(&bgmac_bcma_driver); 1705 } 1706 1707 module_init(bgmac_init) 1708 module_exit(bgmac_exit) 1709 1710 MODULE_AUTHOR("Rafał Miłecki"); 1711 MODULE_LICENSE("GPL"); 1712