1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <asm/mach-bcm47xx/nvram.h> 19 20 static const struct bcma_device_id bgmac_bcma_tbl[] = { 21 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 23 BCMA_CORETABLE_END 24 }; 25 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 26 27 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 28 u32 value, int timeout) 29 { 30 u32 val; 31 int i; 32 33 for (i = 0; i < timeout / 10; i++) { 34 val = bcma_read32(core, reg); 35 if ((val & mask) == value) 36 return true; 37 udelay(10); 38 } 39 pr_err("Timeout waiting for reg 0x%X\n", reg); 40 return false; 41 } 42 43 /************************************************** 44 * DMA 45 **************************************************/ 46 47 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 48 { 49 u32 val; 50 int i; 51 52 if (!ring->mmio_base) 53 return; 54 55 /* Suspend DMA TX ring first. 56 * bgmac_wait_value doesn't support waiting for any of few values, so 57 * implement whole loop here. 58 */ 59 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 60 BGMAC_DMA_TX_SUSPEND); 61 for (i = 0; i < 10000 / 10; i++) { 62 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 63 val &= BGMAC_DMA_TX_STAT; 64 if (val == BGMAC_DMA_TX_STAT_DISABLED || 65 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 66 val == BGMAC_DMA_TX_STAT_STOPPED) { 67 i = 0; 68 break; 69 } 70 udelay(10); 71 } 72 if (i) 73 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 74 ring->mmio_base, val); 75 76 /* Remove SUSPEND bit */ 77 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 78 if (!bgmac_wait_value(bgmac->core, 79 ring->mmio_base + BGMAC_DMA_TX_STATUS, 80 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 81 10000)) { 82 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 83 ring->mmio_base); 84 udelay(300); 85 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 86 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 87 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 88 ring->mmio_base); 89 } 90 } 91 92 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 93 struct bgmac_dma_ring *ring) 94 { 95 u32 ctl; 96 97 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 98 ctl |= BGMAC_DMA_TX_ENABLE; 99 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 100 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 101 } 102 103 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 104 struct bgmac_dma_ring *ring, 105 struct sk_buff *skb) 106 { 107 struct device *dma_dev = bgmac->core->dma_dev; 108 struct net_device *net_dev = bgmac->net_dev; 109 struct bgmac_dma_desc *dma_desc; 110 struct bgmac_slot_info *slot; 111 u32 ctl0, ctl1; 112 int free_slots; 113 114 if (skb->len > BGMAC_DESC_CTL1_LEN) { 115 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 116 goto err_stop_drop; 117 } 118 119 if (ring->start <= ring->end) 120 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; 121 else 122 free_slots = ring->start - ring->end; 123 if (free_slots == 1) { 124 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 125 netif_stop_queue(net_dev); 126 return NETDEV_TX_BUSY; 127 } 128 129 slot = &ring->slots[ring->end]; 130 slot->skb = skb; 131 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, 132 DMA_TO_DEVICE); 133 if (dma_mapping_error(dma_dev, slot->dma_addr)) { 134 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 135 ring->mmio_base); 136 goto err_stop_drop; 137 } 138 139 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; 140 if (ring->end == ring->num_slots - 1) 141 ctl0 |= BGMAC_DESC_CTL0_EOT; 142 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; 143 144 dma_desc = ring->cpu_base; 145 dma_desc += ring->end; 146 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 147 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 148 dma_desc->ctl0 = cpu_to_le32(ctl0); 149 dma_desc->ctl1 = cpu_to_le32(ctl1); 150 151 wmb(); 152 153 /* Increase ring->end to point empty slot. We tell hardware the first 154 * slot it should *not* read. 155 */ 156 if (++ring->end >= BGMAC_TX_RING_SLOTS) 157 ring->end = 0; 158 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 159 ring->end * sizeof(struct bgmac_dma_desc)); 160 161 /* Always keep one slot free to allow detecting bugged calls. */ 162 if (--free_slots == 1) 163 netif_stop_queue(net_dev); 164 165 return NETDEV_TX_OK; 166 167 err_stop_drop: 168 netif_stop_queue(net_dev); 169 dev_kfree_skb(skb); 170 return NETDEV_TX_OK; 171 } 172 173 /* Free transmitted packets */ 174 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 175 { 176 struct device *dma_dev = bgmac->core->dma_dev; 177 int empty_slot; 178 bool freed = false; 179 180 /* The last slot that hardware didn't consume yet */ 181 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 182 empty_slot &= BGMAC_DMA_TX_STATDPTR; 183 empty_slot /= sizeof(struct bgmac_dma_desc); 184 185 while (ring->start != empty_slot) { 186 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 187 188 if (slot->skb) { 189 /* Unmap no longer used buffer */ 190 dma_unmap_single(dma_dev, slot->dma_addr, 191 slot->skb->len, DMA_TO_DEVICE); 192 slot->dma_addr = 0; 193 194 /* Free memory! :) */ 195 dev_kfree_skb(slot->skb); 196 slot->skb = NULL; 197 } else { 198 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", 199 ring->start, ring->end); 200 } 201 202 if (++ring->start >= BGMAC_TX_RING_SLOTS) 203 ring->start = 0; 204 freed = true; 205 } 206 207 if (freed && netif_queue_stopped(bgmac->net_dev)) 208 netif_wake_queue(bgmac->net_dev); 209 } 210 211 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 212 { 213 if (!ring->mmio_base) 214 return; 215 216 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 217 if (!bgmac_wait_value(bgmac->core, 218 ring->mmio_base + BGMAC_DMA_RX_STATUS, 219 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 220 10000)) 221 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 222 ring->mmio_base); 223 } 224 225 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 226 struct bgmac_dma_ring *ring) 227 { 228 u32 ctl; 229 230 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 231 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 232 ctl |= BGMAC_DMA_RX_ENABLE; 233 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 234 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 235 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 236 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 237 } 238 239 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 240 struct bgmac_slot_info *slot) 241 { 242 struct device *dma_dev = bgmac->core->dma_dev; 243 struct bgmac_rx_header *rx; 244 245 /* Alloc skb */ 246 slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); 247 if (!slot->skb) { 248 bgmac_err(bgmac, "Allocation of skb failed!\n"); 249 return -ENOMEM; 250 } 251 252 /* Poison - if everything goes fine, hardware will overwrite it */ 253 rx = (struct bgmac_rx_header *)slot->skb->data; 254 rx->len = cpu_to_le16(0xdead); 255 rx->flags = cpu_to_le16(0xbeef); 256 257 /* Map skb for the DMA */ 258 slot->dma_addr = dma_map_single(dma_dev, slot->skb->data, 259 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 260 if (dma_mapping_error(dma_dev, slot->dma_addr)) { 261 bgmac_err(bgmac, "DMA mapping error\n"); 262 return -ENOMEM; 263 } 264 if (slot->dma_addr & 0xC0000000) 265 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 266 267 return 0; 268 } 269 270 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 271 int weight) 272 { 273 u32 end_slot; 274 int handled = 0; 275 276 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 277 end_slot &= BGMAC_DMA_RX_STATDPTR; 278 end_slot /= sizeof(struct bgmac_dma_desc); 279 280 ring->end = end_slot; 281 282 while (ring->start != ring->end) { 283 struct device *dma_dev = bgmac->core->dma_dev; 284 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 285 struct sk_buff *skb = slot->skb; 286 struct sk_buff *new_skb; 287 struct bgmac_rx_header *rx; 288 u16 len, flags; 289 290 /* Unmap buffer to make it accessible to the CPU */ 291 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, 292 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 293 294 /* Get info from the header */ 295 rx = (struct bgmac_rx_header *)skb->data; 296 len = le16_to_cpu(rx->len); 297 flags = le16_to_cpu(rx->flags); 298 299 /* Check for poison and drop or pass the packet */ 300 if (len == 0xdead && flags == 0xbeef) { 301 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 302 ring->start); 303 } else { 304 new_skb = netdev_alloc_skb(bgmac->net_dev, len); 305 if (new_skb) { 306 skb_put(new_skb, len); 307 skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET, 308 new_skb->data, 309 len); 310 new_skb->protocol = 311 eth_type_trans(new_skb, bgmac->net_dev); 312 netif_receive_skb(new_skb); 313 handled++; 314 } else { 315 bgmac->net_dev->stats.rx_dropped++; 316 bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n"); 317 } 318 319 /* Poison the old skb */ 320 rx->len = cpu_to_le16(0xdead); 321 rx->flags = cpu_to_le16(0xbeef); 322 } 323 324 /* Make it back accessible to the hardware */ 325 dma_sync_single_for_device(dma_dev, slot->dma_addr, 326 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 327 328 if (++ring->start >= BGMAC_RX_RING_SLOTS) 329 ring->start = 0; 330 331 if (handled >= weight) /* Should never be greater */ 332 break; 333 } 334 335 return handled; 336 } 337 338 /* Does ring support unaligned addressing? */ 339 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 340 struct bgmac_dma_ring *ring, 341 enum bgmac_dma_ring_type ring_type) 342 { 343 switch (ring_type) { 344 case BGMAC_DMA_RING_TX: 345 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 346 0xff0); 347 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 348 return true; 349 break; 350 case BGMAC_DMA_RING_RX: 351 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 352 0xff0); 353 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 354 return true; 355 break; 356 } 357 return false; 358 } 359 360 static void bgmac_dma_ring_free(struct bgmac *bgmac, 361 struct bgmac_dma_ring *ring) 362 { 363 struct device *dma_dev = bgmac->core->dma_dev; 364 struct bgmac_slot_info *slot; 365 int size; 366 int i; 367 368 for (i = 0; i < ring->num_slots; i++) { 369 slot = &ring->slots[i]; 370 if (slot->skb) { 371 if (slot->dma_addr) 372 dma_unmap_single(dma_dev, slot->dma_addr, 373 slot->skb->len, DMA_TO_DEVICE); 374 dev_kfree_skb(slot->skb); 375 } 376 } 377 378 if (ring->cpu_base) { 379 /* Free ring of descriptors */ 380 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 381 dma_free_coherent(dma_dev, size, ring->cpu_base, 382 ring->dma_base); 383 } 384 } 385 386 static void bgmac_dma_free(struct bgmac *bgmac) 387 { 388 int i; 389 390 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 391 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]); 392 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 393 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]); 394 } 395 396 static int bgmac_dma_alloc(struct bgmac *bgmac) 397 { 398 struct device *dma_dev = bgmac->core->dma_dev; 399 struct bgmac_dma_ring *ring; 400 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 401 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 402 int size; /* ring size: different for Tx and Rx */ 403 int err; 404 int i; 405 406 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 407 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 408 409 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 410 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 411 return -ENOTSUPP; 412 } 413 414 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 415 ring = &bgmac->tx_ring[i]; 416 ring->num_slots = BGMAC_TX_RING_SLOTS; 417 ring->mmio_base = ring_base[i]; 418 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX)) 419 bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n", 420 ring->mmio_base); 421 422 /* Alloc ring of descriptors */ 423 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 424 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 425 &ring->dma_base, 426 GFP_KERNEL); 427 if (!ring->cpu_base) { 428 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 429 ring->mmio_base); 430 goto err_dma_free; 431 } 432 if (ring->dma_base & 0xC0000000) 433 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 434 435 /* No need to alloc TX slots yet */ 436 } 437 438 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 439 ring = &bgmac->rx_ring[i]; 440 ring->num_slots = BGMAC_RX_RING_SLOTS; 441 ring->mmio_base = ring_base[i]; 442 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX)) 443 bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n", 444 ring->mmio_base); 445 446 /* Alloc ring of descriptors */ 447 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 448 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 449 &ring->dma_base, 450 GFP_KERNEL); 451 if (!ring->cpu_base) { 452 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 453 ring->mmio_base); 454 err = -ENOMEM; 455 goto err_dma_free; 456 } 457 if (ring->dma_base & 0xC0000000) 458 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); 459 460 /* Alloc RX slots */ 461 for (i = 0; i < ring->num_slots; i++) { 462 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[i]); 463 if (err) { 464 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 465 goto err_dma_free; 466 } 467 } 468 } 469 470 return 0; 471 472 err_dma_free: 473 bgmac_dma_free(bgmac); 474 return -ENOMEM; 475 } 476 477 static void bgmac_dma_init(struct bgmac *bgmac) 478 { 479 struct bgmac_dma_ring *ring; 480 struct bgmac_dma_desc *dma_desc; 481 u32 ctl0, ctl1; 482 int i; 483 484 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 485 ring = &bgmac->tx_ring[i]; 486 487 /* We don't implement unaligned addressing, so enable first */ 488 bgmac_dma_tx_enable(bgmac, ring); 489 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 490 lower_32_bits(ring->dma_base)); 491 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 492 upper_32_bits(ring->dma_base)); 493 494 ring->start = 0; 495 ring->end = 0; /* Points the slot that should *not* be read */ 496 } 497 498 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 499 ring = &bgmac->rx_ring[i]; 500 501 /* We don't implement unaligned addressing, so enable first */ 502 bgmac_dma_rx_enable(bgmac, ring); 503 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 504 lower_32_bits(ring->dma_base)); 505 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 506 upper_32_bits(ring->dma_base)); 507 508 for (i = 0, dma_desc = ring->cpu_base; i < ring->num_slots; 509 i++, dma_desc++) { 510 ctl0 = ctl1 = 0; 511 512 if (i == ring->num_slots - 1) 513 ctl0 |= BGMAC_DESC_CTL0_EOT; 514 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 515 /* Is there any BGMAC device that requires extension? */ 516 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 517 * B43_DMA64_DCTL1_ADDREXT_MASK; 518 */ 519 520 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[i].dma_addr)); 521 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[i].dma_addr)); 522 dma_desc->ctl0 = cpu_to_le32(ctl0); 523 dma_desc->ctl1 = cpu_to_le32(ctl1); 524 } 525 526 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 527 ring->num_slots * sizeof(struct bgmac_dma_desc)); 528 529 ring->start = 0; 530 ring->end = 0; 531 } 532 } 533 534 /************************************************** 535 * PHY ops 536 **************************************************/ 537 538 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 539 { 540 struct bcma_device *core; 541 u16 phy_access_addr; 542 u16 phy_ctl_addr; 543 u32 tmp; 544 545 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 546 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 547 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 548 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 549 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 550 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 551 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 552 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 553 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 554 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 555 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 556 557 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 558 core = bgmac->core->bus->drv_gmac_cmn.core; 559 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 560 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 561 } else { 562 core = bgmac->core; 563 phy_access_addr = BGMAC_PHY_ACCESS; 564 phy_ctl_addr = BGMAC_PHY_CNTL; 565 } 566 567 tmp = bcma_read32(core, phy_ctl_addr); 568 tmp &= ~BGMAC_PC_EPA_MASK; 569 tmp |= phyaddr; 570 bcma_write32(core, phy_ctl_addr, tmp); 571 572 tmp = BGMAC_PA_START; 573 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 574 tmp |= reg << BGMAC_PA_REG_SHIFT; 575 bcma_write32(core, phy_access_addr, tmp); 576 577 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 578 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 579 phyaddr, reg); 580 return 0xffff; 581 } 582 583 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 584 } 585 586 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 587 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 588 { 589 struct bcma_device *core; 590 u16 phy_access_addr; 591 u16 phy_ctl_addr; 592 u32 tmp; 593 594 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 595 core = bgmac->core->bus->drv_gmac_cmn.core; 596 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 597 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 598 } else { 599 core = bgmac->core; 600 phy_access_addr = BGMAC_PHY_ACCESS; 601 phy_ctl_addr = BGMAC_PHY_CNTL; 602 } 603 604 tmp = bcma_read32(core, phy_ctl_addr); 605 tmp &= ~BGMAC_PC_EPA_MASK; 606 tmp |= phyaddr; 607 bcma_write32(core, phy_ctl_addr, tmp); 608 609 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 610 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 611 bgmac_warn(bgmac, "Error setting MDIO int\n"); 612 613 tmp = BGMAC_PA_START; 614 tmp |= BGMAC_PA_WRITE; 615 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 616 tmp |= reg << BGMAC_PA_REG_SHIFT; 617 tmp |= value; 618 bcma_write32(core, phy_access_addr, tmp); 619 620 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 621 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 622 phyaddr, reg); 623 return -ETIMEDOUT; 624 } 625 626 return 0; 627 } 628 629 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */ 630 static void bgmac_phy_force(struct bgmac *bgmac) 631 { 632 u16 ctl; 633 u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB | 634 BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX); 635 636 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 637 return; 638 639 if (bgmac->autoneg) 640 return; 641 642 ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL); 643 ctl &= mask; 644 if (bgmac->full_duplex) 645 ctl |= BGMAC_PHY_CTL_DUPLEX; 646 if (bgmac->speed == BGMAC_SPEED_100) 647 ctl |= BGMAC_PHY_CTL_SPEED_100; 648 else if (bgmac->speed == BGMAC_SPEED_1000) 649 ctl |= BGMAC_PHY_CTL_SPEED_1000; 650 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl); 651 } 652 653 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */ 654 static void bgmac_phy_advertise(struct bgmac *bgmac) 655 { 656 u16 adv; 657 658 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 659 return; 660 661 if (!bgmac->autoneg) 662 return; 663 664 /* Adv selected 10/100 speeds */ 665 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV); 666 adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL | 667 BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL); 668 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10) 669 adv |= BGMAC_PHY_ADV_10HALF; 670 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100) 671 adv |= BGMAC_PHY_ADV_100HALF; 672 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10) 673 adv |= BGMAC_PHY_ADV_10FULL; 674 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100) 675 adv |= BGMAC_PHY_ADV_100FULL; 676 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv); 677 678 /* Adv selected 1000 speeds */ 679 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2); 680 adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL); 681 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000) 682 adv |= BGMAC_PHY_ADV2_1000HALF; 683 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000) 684 adv |= BGMAC_PHY_ADV2_1000FULL; 685 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv); 686 687 /* Restart */ 688 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, 689 bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) | 690 BGMAC_PHY_CTL_RESTART); 691 } 692 693 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 694 static void bgmac_phy_init(struct bgmac *bgmac) 695 { 696 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 697 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 698 u8 i; 699 700 if (ci->id == BCMA_CHIP_ID_BCM5356) { 701 for (i = 0; i < 5; i++) { 702 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 703 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 704 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 705 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 706 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 707 } 708 } 709 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 710 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 711 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 712 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 713 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 714 for (i = 0; i < 5; i++) { 715 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 716 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 717 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 718 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 719 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 720 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 721 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 722 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 723 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 724 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 725 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 726 } 727 } 728 } 729 730 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 731 static void bgmac_phy_reset(struct bgmac *bgmac) 732 { 733 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 734 return; 735 736 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, 737 BGMAC_PHY_CTL_RESET); 738 udelay(100); 739 if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) & 740 BGMAC_PHY_CTL_RESET) 741 bgmac_err(bgmac, "PHY reset failed\n"); 742 bgmac_phy_init(bgmac); 743 } 744 745 /************************************************** 746 * Chip ops 747 **************************************************/ 748 749 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 750 * nothing to change? Try if after stabilizng driver. 751 */ 752 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 753 bool force) 754 { 755 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 756 u32 new_val = (cmdcfg & mask) | set; 757 758 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR); 759 udelay(2); 760 761 if (new_val != cmdcfg || force) 762 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 763 764 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR); 765 udelay(2); 766 } 767 768 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 769 { 770 u32 tmp; 771 772 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 773 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 774 tmp = (addr[4] << 8) | addr[5]; 775 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 776 } 777 778 static void bgmac_set_rx_mode(struct net_device *net_dev) 779 { 780 struct bgmac *bgmac = netdev_priv(net_dev); 781 782 if (net_dev->flags & IFF_PROMISC) 783 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 784 else 785 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 786 } 787 788 #if 0 /* We don't use that regs yet */ 789 static void bgmac_chip_stats_update(struct bgmac *bgmac) 790 { 791 int i; 792 793 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 794 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 795 bgmac->mib_tx_regs[i] = 796 bgmac_read(bgmac, 797 BGMAC_TX_GOOD_OCTETS + (i * 4)); 798 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 799 bgmac->mib_rx_regs[i] = 800 bgmac_read(bgmac, 801 BGMAC_RX_GOOD_OCTETS + (i * 4)); 802 } 803 804 /* TODO: what else? how to handle BCM4706? Specs are needed */ 805 } 806 #endif 807 808 static void bgmac_clear_mib(struct bgmac *bgmac) 809 { 810 int i; 811 812 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 813 return; 814 815 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 816 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 817 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 818 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 819 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 820 } 821 822 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 823 static void bgmac_speed(struct bgmac *bgmac, int speed) 824 { 825 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 826 u32 set = 0; 827 828 if (speed & BGMAC_SPEED_10) 829 set |= BGMAC_CMDCFG_ES_10; 830 if (speed & BGMAC_SPEED_100) 831 set |= BGMAC_CMDCFG_ES_100; 832 if (speed & BGMAC_SPEED_1000) 833 set |= BGMAC_CMDCFG_ES_1000; 834 if (!bgmac->full_duplex) 835 set |= BGMAC_CMDCFG_HD; 836 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 837 } 838 839 static void bgmac_miiconfig(struct bgmac *bgmac) 840 { 841 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 842 BGMAC_DS_MM_SHIFT; 843 if (imode == 0 || imode == 1) { 844 if (bgmac->autoneg) 845 bgmac_speed(bgmac, BGMAC_SPEED_100); 846 else 847 bgmac_speed(bgmac, bgmac->speed); 848 } 849 } 850 851 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 852 static void bgmac_chip_reset(struct bgmac *bgmac) 853 { 854 struct bcma_device *core = bgmac->core; 855 struct bcma_bus *bus = core->bus; 856 struct bcma_chipinfo *ci = &bus->chipinfo; 857 u32 flags = 0; 858 u32 iost; 859 int i; 860 861 if (bcma_core_is_enabled(core)) { 862 if (!bgmac->stats_grabbed) { 863 /* bgmac_chip_stats_update(bgmac); */ 864 bgmac->stats_grabbed = true; 865 } 866 867 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 868 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 869 870 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 871 udelay(1); 872 873 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 874 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 875 876 /* TODO: Clear software multicast filter list */ 877 } 878 879 iost = bcma_aread32(core, BCMA_IOST); 880 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) || 881 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 882 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) 883 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 884 885 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 886 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 887 if (!bgmac->has_robosw) 888 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 889 } 890 891 bcma_core_enable(core, flags); 892 893 if (core->id.rev > 2) { 894 bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8); 895 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24, 896 1000); 897 } 898 899 if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 || 900 ci->id == BCMA_CHIP_ID_BCM53572) { 901 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 902 u8 et_swtype = 0; 903 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 904 BGMAC_CHIPCTL_1_IF_TYPE_RMII; 905 char buf[2]; 906 907 if (nvram_getenv("et_swtype", buf, 1) > 0) { 908 if (kstrtou8(buf, 0, &et_swtype)) 909 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 910 buf); 911 et_swtype &= 0x0f; 912 et_swtype <<= 4; 913 sw_type = et_swtype; 914 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) { 915 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 916 } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) || 917 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) { 918 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 919 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 920 } 921 bcma_chipco_chipctl_maskset(cc, 1, 922 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 923 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 924 sw_type); 925 } 926 927 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 928 bcma_awrite32(core, BCMA_IOCTL, 929 bcma_aread32(core, BCMA_IOCTL) & 930 ~BGMAC_BCMA_IOCTL_SW_RESET); 931 932 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 933 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 934 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 935 * be keps until taking MAC out of the reset. 936 */ 937 bgmac_cmdcfg_maskset(bgmac, 938 ~(BGMAC_CMDCFG_TE | 939 BGMAC_CMDCFG_RE | 940 BGMAC_CMDCFG_RPI | 941 BGMAC_CMDCFG_TAI | 942 BGMAC_CMDCFG_HD | 943 BGMAC_CMDCFG_ML | 944 BGMAC_CMDCFG_CFE | 945 BGMAC_CMDCFG_RL | 946 BGMAC_CMDCFG_RED | 947 BGMAC_CMDCFG_PE | 948 BGMAC_CMDCFG_TPI | 949 BGMAC_CMDCFG_PAD_EN | 950 BGMAC_CMDCFG_PF), 951 BGMAC_CMDCFG_PROM | 952 BGMAC_CMDCFG_NLC | 953 BGMAC_CMDCFG_CFE | 954 BGMAC_CMDCFG_SR, 955 false); 956 957 bgmac_clear_mib(bgmac); 958 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 959 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 960 BCMA_GMAC_CMN_PC_MTE); 961 else 962 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 963 bgmac_miiconfig(bgmac); 964 bgmac_phy_init(bgmac); 965 966 bgmac->int_status = 0; 967 } 968 969 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 970 { 971 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 972 } 973 974 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 975 { 976 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 977 } 978 979 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 980 static void bgmac_enable(struct bgmac *bgmac) 981 { 982 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 983 u32 cmdcfg; 984 u32 mode; 985 u32 rxq_ctl; 986 u32 fl_ctl; 987 u16 bp_clk; 988 u8 mdp; 989 990 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 991 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 992 BGMAC_CMDCFG_SR, true); 993 udelay(2); 994 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 995 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 996 997 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 998 BGMAC_DS_MM_SHIFT; 999 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1000 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1001 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1002 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1003 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1004 1005 switch (ci->id) { 1006 case BCMA_CHIP_ID_BCM5357: 1007 case BCMA_CHIP_ID_BCM4749: 1008 case BCMA_CHIP_ID_BCM53572: 1009 case BCMA_CHIP_ID_BCM4716: 1010 case BCMA_CHIP_ID_BCM47162: 1011 fl_ctl = 0x03cb04cb; 1012 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1013 ci->id == BCMA_CHIP_ID_BCM4749 || 1014 ci->id == BCMA_CHIP_ID_BCM53572) 1015 fl_ctl = 0x2300e1; 1016 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1017 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1018 break; 1019 } 1020 1021 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1022 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1023 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000; 1024 mdp = (bp_clk * 128 / 1000) - 3; 1025 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1026 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1027 } 1028 1029 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1030 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1031 { 1032 struct bgmac_dma_ring *ring; 1033 int i; 1034 1035 /* 1 interrupt per received frame */ 1036 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1037 1038 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1039 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1040 1041 bgmac_set_rx_mode(bgmac->net_dev); 1042 1043 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1044 1045 if (bgmac->loopback) 1046 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1047 else 1048 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1049 1050 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1051 1052 if (!bgmac->autoneg) { 1053 bgmac_speed(bgmac, bgmac->speed); 1054 bgmac_phy_force(bgmac); 1055 } else if (bgmac->speed) { /* if there is anything to adv */ 1056 bgmac_phy_advertise(bgmac); 1057 } 1058 1059 if (full_init) { 1060 bgmac_dma_init(bgmac); 1061 if (1) /* FIXME: is there any case we don't want IRQs? */ 1062 bgmac_chip_intrs_on(bgmac); 1063 } else { 1064 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1065 ring = &bgmac->rx_ring[i]; 1066 bgmac_dma_rx_enable(bgmac, ring); 1067 } 1068 } 1069 1070 bgmac_enable(bgmac); 1071 } 1072 1073 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1074 { 1075 struct bgmac *bgmac = netdev_priv(dev_id); 1076 1077 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1078 int_status &= bgmac->int_mask; 1079 1080 if (!int_status) 1081 return IRQ_NONE; 1082 1083 /* Ack */ 1084 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); 1085 1086 /* Disable new interrupts until handling existing ones */ 1087 bgmac_chip_intrs_off(bgmac); 1088 1089 bgmac->int_status = int_status; 1090 1091 napi_schedule(&bgmac->napi); 1092 1093 return IRQ_HANDLED; 1094 } 1095 1096 static int bgmac_poll(struct napi_struct *napi, int weight) 1097 { 1098 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1099 struct bgmac_dma_ring *ring; 1100 int handled = 0; 1101 1102 if (bgmac->int_status & BGMAC_IS_TX0) { 1103 ring = &bgmac->tx_ring[0]; 1104 bgmac_dma_tx_free(bgmac, ring); 1105 bgmac->int_status &= ~BGMAC_IS_TX0; 1106 } 1107 1108 if (bgmac->int_status & BGMAC_IS_RX) { 1109 ring = &bgmac->rx_ring[0]; 1110 handled += bgmac_dma_rx_read(bgmac, ring, weight); 1111 bgmac->int_status &= ~BGMAC_IS_RX; 1112 } 1113 1114 if (bgmac->int_status) { 1115 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); 1116 bgmac->int_status = 0; 1117 } 1118 1119 if (handled < weight) 1120 napi_complete(napi); 1121 1122 bgmac_chip_intrs_on(bgmac); 1123 1124 return handled; 1125 } 1126 1127 /************************************************** 1128 * net_device_ops 1129 **************************************************/ 1130 1131 static int bgmac_open(struct net_device *net_dev) 1132 { 1133 struct bgmac *bgmac = netdev_priv(net_dev); 1134 int err = 0; 1135 1136 bgmac_chip_reset(bgmac); 1137 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1138 bgmac_chip_init(bgmac, true); 1139 1140 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1141 KBUILD_MODNAME, net_dev); 1142 if (err < 0) { 1143 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1144 goto err_out; 1145 } 1146 napi_enable(&bgmac->napi); 1147 1148 netif_carrier_on(net_dev); 1149 1150 err_out: 1151 return err; 1152 } 1153 1154 static int bgmac_stop(struct net_device *net_dev) 1155 { 1156 struct bgmac *bgmac = netdev_priv(net_dev); 1157 1158 netif_carrier_off(net_dev); 1159 1160 napi_disable(&bgmac->napi); 1161 bgmac_chip_intrs_off(bgmac); 1162 free_irq(bgmac->core->irq, net_dev); 1163 1164 bgmac_chip_reset(bgmac); 1165 1166 return 0; 1167 } 1168 1169 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1170 struct net_device *net_dev) 1171 { 1172 struct bgmac *bgmac = netdev_priv(net_dev); 1173 struct bgmac_dma_ring *ring; 1174 1175 /* No QOS support yet */ 1176 ring = &bgmac->tx_ring[0]; 1177 return bgmac_dma_tx_add(bgmac, ring, skb); 1178 } 1179 1180 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1181 { 1182 struct bgmac *bgmac = netdev_priv(net_dev); 1183 int ret; 1184 1185 ret = eth_prepare_mac_addr_change(net_dev, addr); 1186 if (ret < 0) 1187 return ret; 1188 bgmac_write_mac_address(bgmac, (u8 *)addr); 1189 eth_commit_mac_addr_change(net_dev, addr); 1190 return 0; 1191 } 1192 1193 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1194 { 1195 struct bgmac *bgmac = netdev_priv(net_dev); 1196 struct mii_ioctl_data *data = if_mii(ifr); 1197 1198 switch (cmd) { 1199 case SIOCGMIIPHY: 1200 data->phy_id = bgmac->phyaddr; 1201 /* fallthru */ 1202 case SIOCGMIIREG: 1203 if (!netif_running(net_dev)) 1204 return -EAGAIN; 1205 data->val_out = bgmac_phy_read(bgmac, data->phy_id, 1206 data->reg_num & 0x1f); 1207 return 0; 1208 case SIOCSMIIREG: 1209 if (!netif_running(net_dev)) 1210 return -EAGAIN; 1211 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f, 1212 data->val_in); 1213 return 0; 1214 default: 1215 return -EOPNOTSUPP; 1216 } 1217 } 1218 1219 static const struct net_device_ops bgmac_netdev_ops = { 1220 .ndo_open = bgmac_open, 1221 .ndo_stop = bgmac_stop, 1222 .ndo_start_xmit = bgmac_start_xmit, 1223 .ndo_set_rx_mode = bgmac_set_rx_mode, 1224 .ndo_set_mac_address = bgmac_set_mac_address, 1225 .ndo_validate_addr = eth_validate_addr, 1226 .ndo_do_ioctl = bgmac_ioctl, 1227 }; 1228 1229 /************************************************** 1230 * ethtool_ops 1231 **************************************************/ 1232 1233 static int bgmac_get_settings(struct net_device *net_dev, 1234 struct ethtool_cmd *cmd) 1235 { 1236 struct bgmac *bgmac = netdev_priv(net_dev); 1237 1238 cmd->supported = SUPPORTED_10baseT_Half | 1239 SUPPORTED_10baseT_Full | 1240 SUPPORTED_100baseT_Half | 1241 SUPPORTED_100baseT_Full | 1242 SUPPORTED_1000baseT_Half | 1243 SUPPORTED_1000baseT_Full | 1244 SUPPORTED_Autoneg; 1245 1246 if (bgmac->autoneg) { 1247 WARN_ON(cmd->advertising); 1248 if (bgmac->full_duplex) { 1249 if (bgmac->speed & BGMAC_SPEED_10) 1250 cmd->advertising |= ADVERTISED_10baseT_Full; 1251 if (bgmac->speed & BGMAC_SPEED_100) 1252 cmd->advertising |= ADVERTISED_100baseT_Full; 1253 if (bgmac->speed & BGMAC_SPEED_1000) 1254 cmd->advertising |= ADVERTISED_1000baseT_Full; 1255 } else { 1256 if (bgmac->speed & BGMAC_SPEED_10) 1257 cmd->advertising |= ADVERTISED_10baseT_Half; 1258 if (bgmac->speed & BGMAC_SPEED_100) 1259 cmd->advertising |= ADVERTISED_100baseT_Half; 1260 if (bgmac->speed & BGMAC_SPEED_1000) 1261 cmd->advertising |= ADVERTISED_1000baseT_Half; 1262 } 1263 } else { 1264 switch (bgmac->speed) { 1265 case BGMAC_SPEED_10: 1266 ethtool_cmd_speed_set(cmd, SPEED_10); 1267 break; 1268 case BGMAC_SPEED_100: 1269 ethtool_cmd_speed_set(cmd, SPEED_100); 1270 break; 1271 case BGMAC_SPEED_1000: 1272 ethtool_cmd_speed_set(cmd, SPEED_1000); 1273 break; 1274 } 1275 } 1276 1277 cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1278 1279 cmd->autoneg = bgmac->autoneg; 1280 1281 return 0; 1282 } 1283 1284 #if 0 1285 static int bgmac_set_settings(struct net_device *net_dev, 1286 struct ethtool_cmd *cmd) 1287 { 1288 struct bgmac *bgmac = netdev_priv(net_dev); 1289 1290 return -1; 1291 } 1292 #endif 1293 1294 static void bgmac_get_drvinfo(struct net_device *net_dev, 1295 struct ethtool_drvinfo *info) 1296 { 1297 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1298 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1299 } 1300 1301 static const struct ethtool_ops bgmac_ethtool_ops = { 1302 .get_settings = bgmac_get_settings, 1303 .get_drvinfo = bgmac_get_drvinfo, 1304 }; 1305 1306 /************************************************** 1307 * BCMA bus ops 1308 **************************************************/ 1309 1310 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1311 static int bgmac_probe(struct bcma_device *core) 1312 { 1313 struct net_device *net_dev; 1314 struct bgmac *bgmac; 1315 struct ssb_sprom *sprom = &core->bus->sprom; 1316 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1317 int err; 1318 1319 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1320 if (core->core_unit > 1) { 1321 pr_err("Unsupported core_unit %d\n", core->core_unit); 1322 return -ENOTSUPP; 1323 } 1324 1325 if (!is_valid_ether_addr(mac)) { 1326 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1327 eth_random_addr(mac); 1328 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1329 } 1330 1331 /* Allocation and references */ 1332 net_dev = alloc_etherdev(sizeof(*bgmac)); 1333 if (!net_dev) 1334 return -ENOMEM; 1335 net_dev->netdev_ops = &bgmac_netdev_ops; 1336 net_dev->irq = core->irq; 1337 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops); 1338 bgmac = netdev_priv(net_dev); 1339 bgmac->net_dev = net_dev; 1340 bgmac->core = core; 1341 bcma_set_drvdata(core, bgmac); 1342 1343 /* Defaults */ 1344 bgmac->autoneg = true; 1345 bgmac->full_duplex = true; 1346 bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000; 1347 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1348 1349 /* On BCM4706 we need common core to access PHY */ 1350 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1351 !core->bus->drv_gmac_cmn.core) { 1352 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1353 err = -ENODEV; 1354 goto err_netdev_free; 1355 } 1356 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1357 1358 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1359 sprom->et0phyaddr; 1360 bgmac->phyaddr &= BGMAC_PHY_MASK; 1361 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1362 bgmac_err(bgmac, "No PHY found\n"); 1363 err = -ENODEV; 1364 goto err_netdev_free; 1365 } 1366 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1367 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1368 1369 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1370 bgmac_err(bgmac, "PCI setup not implemented\n"); 1371 err = -ENOTSUPP; 1372 goto err_netdev_free; 1373 } 1374 1375 bgmac_chip_reset(bgmac); 1376 1377 err = bgmac_dma_alloc(bgmac); 1378 if (err) { 1379 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1380 goto err_netdev_free; 1381 } 1382 1383 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1384 if (nvram_getenv("et0_no_txint", NULL, 0) == 0) 1385 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1386 1387 /* TODO: reset the external phy. Specs are needed */ 1388 bgmac_phy_reset(bgmac); 1389 1390 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1391 BGMAC_BFL_ENETROBO); 1392 if (bgmac->has_robosw) 1393 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1394 1395 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1396 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1397 1398 err = register_netdev(bgmac->net_dev); 1399 if (err) { 1400 bgmac_err(bgmac, "Cannot register net device\n"); 1401 err = -ENOTSUPP; 1402 goto err_dma_free; 1403 } 1404 1405 netif_carrier_off(net_dev); 1406 1407 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1408 1409 return 0; 1410 1411 err_dma_free: 1412 bgmac_dma_free(bgmac); 1413 1414 err_netdev_free: 1415 bcma_set_drvdata(core, NULL); 1416 free_netdev(net_dev); 1417 1418 return err; 1419 } 1420 1421 static void bgmac_remove(struct bcma_device *core) 1422 { 1423 struct bgmac *bgmac = bcma_get_drvdata(core); 1424 1425 netif_napi_del(&bgmac->napi); 1426 unregister_netdev(bgmac->net_dev); 1427 bgmac_dma_free(bgmac); 1428 bcma_set_drvdata(core, NULL); 1429 free_netdev(bgmac->net_dev); 1430 } 1431 1432 static struct bcma_driver bgmac_bcma_driver = { 1433 .name = KBUILD_MODNAME, 1434 .id_table = bgmac_bcma_tbl, 1435 .probe = bgmac_probe, 1436 .remove = bgmac_remove, 1437 }; 1438 1439 static int __init bgmac_init(void) 1440 { 1441 int err; 1442 1443 err = bcma_driver_register(&bgmac_bcma_driver); 1444 if (err) 1445 return err; 1446 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1447 1448 return 0; 1449 } 1450 1451 static void __exit bgmac_exit(void) 1452 { 1453 bcma_driver_unregister(&bgmac_bcma_driver); 1454 } 1455 1456 module_init(bgmac_init) 1457 module_exit(bgmac_exit) 1458 1459 MODULE_AUTHOR("Rafał Miłecki"); 1460 MODULE_LICENSE("GPL"); 1461