1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for BCM963xx builtin Ethernet mac 4 * 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 */ 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/clk.h> 11 #include <linux/etherdevice.h> 12 #include <linux/slab.h> 13 #include <linux/delay.h> 14 #include <linux/ethtool.h> 15 #include <linux/crc32.h> 16 #include <linux/err.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/platform_device.h> 19 #include <linux/if_vlan.h> 20 21 #include <bcm63xx_dev_enet.h> 22 #include "bcm63xx_enet.h" 23 24 static char bcm_enet_driver_name[] = "bcm63xx_enet"; 25 26 static int copybreak __read_mostly = 128; 27 module_param(copybreak, int, 0); 28 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 29 30 /* io registers memory shared between all devices */ 31 static void __iomem *bcm_enet_shared_base[3]; 32 33 /* 34 * io helpers to access mac registers 35 */ 36 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) 37 { 38 return bcm_readl(priv->base + off); 39 } 40 41 static inline void enet_writel(struct bcm_enet_priv *priv, 42 u32 val, u32 off) 43 { 44 bcm_writel(val, priv->base + off); 45 } 46 47 /* 48 * io helpers to access switch registers 49 */ 50 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off) 51 { 52 return bcm_readl(priv->base + off); 53 } 54 55 static inline void enetsw_writel(struct bcm_enet_priv *priv, 56 u32 val, u32 off) 57 { 58 bcm_writel(val, priv->base + off); 59 } 60 61 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off) 62 { 63 return bcm_readw(priv->base + off); 64 } 65 66 static inline void enetsw_writew(struct bcm_enet_priv *priv, 67 u16 val, u32 off) 68 { 69 bcm_writew(val, priv->base + off); 70 } 71 72 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off) 73 { 74 return bcm_readb(priv->base + off); 75 } 76 77 static inline void enetsw_writeb(struct bcm_enet_priv *priv, 78 u8 val, u32 off) 79 { 80 bcm_writeb(val, priv->base + off); 81 } 82 83 84 /* io helpers to access shared registers */ 85 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) 86 { 87 return bcm_readl(bcm_enet_shared_base[0] + off); 88 } 89 90 static inline void enet_dma_writel(struct bcm_enet_priv *priv, 91 u32 val, u32 off) 92 { 93 bcm_writel(val, bcm_enet_shared_base[0] + off); 94 } 95 96 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan) 97 { 98 return bcm_readl(bcm_enet_shared_base[1] + 99 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); 100 } 101 102 static inline void enet_dmac_writel(struct bcm_enet_priv *priv, 103 u32 val, u32 off, int chan) 104 { 105 bcm_writel(val, bcm_enet_shared_base[1] + 106 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); 107 } 108 109 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan) 110 { 111 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); 112 } 113 114 static inline void enet_dmas_writel(struct bcm_enet_priv *priv, 115 u32 val, u32 off, int chan) 116 { 117 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); 118 } 119 120 /* 121 * write given data into mii register and wait for transfer to end 122 * with timeout (average measured transfer time is 25us) 123 */ 124 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) 125 { 126 int limit; 127 128 /* make sure mii interrupt status is cleared */ 129 enet_writel(priv, ENET_IR_MII, ENET_IR_REG); 130 131 enet_writel(priv, data, ENET_MIIDATA_REG); 132 wmb(); 133 134 /* busy wait on mii interrupt bit, with timeout */ 135 limit = 1000; 136 do { 137 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) 138 break; 139 udelay(1); 140 } while (limit-- > 0); 141 142 return (limit < 0) ? 1 : 0; 143 } 144 145 /* 146 * MII internal read callback 147 */ 148 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, 149 int regnum) 150 { 151 u32 tmp, val; 152 153 tmp = regnum << ENET_MIIDATA_REG_SHIFT; 154 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 155 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 156 tmp |= ENET_MIIDATA_OP_READ_MASK; 157 158 if (do_mdio_op(priv, tmp)) 159 return -1; 160 161 val = enet_readl(priv, ENET_MIIDATA_REG); 162 val &= 0xffff; 163 return val; 164 } 165 166 /* 167 * MII internal write callback 168 */ 169 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, 170 int regnum, u16 value) 171 { 172 u32 tmp; 173 174 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; 175 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 176 tmp |= regnum << ENET_MIIDATA_REG_SHIFT; 177 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 178 tmp |= ENET_MIIDATA_OP_WRITE_MASK; 179 180 (void)do_mdio_op(priv, tmp); 181 return 0; 182 } 183 184 /* 185 * MII read callback from phylib 186 */ 187 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, 188 int regnum) 189 { 190 return bcm_enet_mdio_read(bus->priv, mii_id, regnum); 191 } 192 193 /* 194 * MII write callback from phylib 195 */ 196 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, 197 int regnum, u16 value) 198 { 199 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); 200 } 201 202 /* 203 * MII read callback from mii core 204 */ 205 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, 206 int regnum) 207 { 208 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); 209 } 210 211 /* 212 * MII write callback from mii core 213 */ 214 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, 215 int regnum, int value) 216 { 217 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); 218 } 219 220 /* 221 * refill rx queue 222 */ 223 static int bcm_enet_refill_rx(struct net_device *dev, bool napi_mode) 224 { 225 struct bcm_enet_priv *priv; 226 227 priv = netdev_priv(dev); 228 229 while (priv->rx_desc_count < priv->rx_ring_size) { 230 struct bcm_enet_desc *desc; 231 int desc_idx; 232 u32 len_stat; 233 234 desc_idx = priv->rx_dirty_desc; 235 desc = &priv->rx_desc_cpu[desc_idx]; 236 237 if (!priv->rx_buf[desc_idx]) { 238 void *buf; 239 240 if (likely(napi_mode)) 241 buf = napi_alloc_frag(priv->rx_frag_size); 242 else 243 buf = netdev_alloc_frag(priv->rx_frag_size); 244 if (unlikely(!buf)) 245 break; 246 priv->rx_buf[desc_idx] = buf; 247 desc->address = dma_map_single(&priv->pdev->dev, 248 buf + priv->rx_buf_offset, 249 priv->rx_buf_size, 250 DMA_FROM_DEVICE); 251 } 252 253 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT; 254 len_stat |= DMADESC_OWNER_MASK; 255 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { 256 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); 257 priv->rx_dirty_desc = 0; 258 } else { 259 priv->rx_dirty_desc++; 260 } 261 wmb(); 262 desc->len_stat = len_stat; 263 264 priv->rx_desc_count++; 265 266 /* tell dma engine we allocated one buffer */ 267 if (priv->dma_has_sram) 268 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); 269 else 270 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan); 271 } 272 273 /* If rx ring is still empty, set a timer to try allocating 274 * again at a later time. */ 275 if (priv->rx_desc_count == 0 && netif_running(dev)) { 276 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); 277 priv->rx_timeout.expires = jiffies + HZ; 278 add_timer(&priv->rx_timeout); 279 } 280 281 return 0; 282 } 283 284 /* 285 * timer callback to defer refill rx queue in case we're OOM 286 */ 287 static void bcm_enet_refill_rx_timer(struct timer_list *t) 288 { 289 struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout); 290 struct net_device *dev = priv->net_dev; 291 292 spin_lock(&priv->rx_lock); 293 bcm_enet_refill_rx(dev, false); 294 spin_unlock(&priv->rx_lock); 295 } 296 297 /* 298 * extract packet from rx queue 299 */ 300 static int bcm_enet_receive_queue(struct net_device *dev, int budget) 301 { 302 struct bcm_enet_priv *priv; 303 struct list_head rx_list; 304 struct device *kdev; 305 int processed; 306 307 priv = netdev_priv(dev); 308 INIT_LIST_HEAD(&rx_list); 309 kdev = &priv->pdev->dev; 310 processed = 0; 311 312 /* don't scan ring further than number of refilled 313 * descriptor */ 314 if (budget > priv->rx_desc_count) 315 budget = priv->rx_desc_count; 316 317 do { 318 struct bcm_enet_desc *desc; 319 struct sk_buff *skb; 320 int desc_idx; 321 u32 len_stat; 322 unsigned int len; 323 void *buf; 324 325 desc_idx = priv->rx_curr_desc; 326 desc = &priv->rx_desc_cpu[desc_idx]; 327 328 /* make sure we actually read the descriptor status at 329 * each loop */ 330 rmb(); 331 332 len_stat = desc->len_stat; 333 334 /* break if dma ownership belongs to hw */ 335 if (len_stat & DMADESC_OWNER_MASK) 336 break; 337 338 processed++; 339 priv->rx_curr_desc++; 340 if (priv->rx_curr_desc == priv->rx_ring_size) 341 priv->rx_curr_desc = 0; 342 343 /* if the packet does not have start of packet _and_ 344 * end of packet flag set, then just recycle it */ 345 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) != 346 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) { 347 dev->stats.rx_dropped++; 348 continue; 349 } 350 351 /* recycle packet if it's marked as bad */ 352 if (!priv->enet_is_sw && 353 unlikely(len_stat & DMADESC_ERR_MASK)) { 354 dev->stats.rx_errors++; 355 356 if (len_stat & DMADESC_OVSIZE_MASK) 357 dev->stats.rx_length_errors++; 358 if (len_stat & DMADESC_CRC_MASK) 359 dev->stats.rx_crc_errors++; 360 if (len_stat & DMADESC_UNDER_MASK) 361 dev->stats.rx_frame_errors++; 362 if (len_stat & DMADESC_OV_MASK) 363 dev->stats.rx_fifo_errors++; 364 continue; 365 } 366 367 /* valid packet */ 368 buf = priv->rx_buf[desc_idx]; 369 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; 370 /* don't include FCS */ 371 len -= 4; 372 373 if (len < copybreak) { 374 skb = napi_alloc_skb(&priv->napi, len); 375 if (unlikely(!skb)) { 376 /* forget packet, just rearm desc */ 377 dev->stats.rx_dropped++; 378 continue; 379 } 380 381 dma_sync_single_for_cpu(kdev, desc->address, 382 len, DMA_FROM_DEVICE); 383 memcpy(skb->data, buf + priv->rx_buf_offset, len); 384 dma_sync_single_for_device(kdev, desc->address, 385 len, DMA_FROM_DEVICE); 386 } else { 387 dma_unmap_single(kdev, desc->address, 388 priv->rx_buf_size, DMA_FROM_DEVICE); 389 priv->rx_buf[desc_idx] = NULL; 390 391 skb = build_skb(buf, priv->rx_frag_size); 392 if (unlikely(!skb)) { 393 skb_free_frag(buf); 394 dev->stats.rx_dropped++; 395 continue; 396 } 397 skb_reserve(skb, priv->rx_buf_offset); 398 } 399 400 skb_put(skb, len); 401 skb->protocol = eth_type_trans(skb, dev); 402 dev->stats.rx_packets++; 403 dev->stats.rx_bytes += len; 404 list_add_tail(&skb->list, &rx_list); 405 406 } while (processed < budget); 407 408 netif_receive_skb_list(&rx_list); 409 priv->rx_desc_count -= processed; 410 411 if (processed || !priv->rx_desc_count) { 412 bcm_enet_refill_rx(dev, true); 413 414 /* kick rx dma */ 415 enet_dmac_writel(priv, priv->dma_chan_en_mask, 416 ENETDMAC_CHANCFG, priv->rx_chan); 417 } 418 419 return processed; 420 } 421 422 423 /* 424 * try to or force reclaim of transmitted buffers 425 */ 426 static int bcm_enet_tx_reclaim(struct net_device *dev, int force) 427 { 428 struct bcm_enet_priv *priv; 429 unsigned int bytes; 430 int released; 431 432 priv = netdev_priv(dev); 433 bytes = 0; 434 released = 0; 435 436 while (priv->tx_desc_count < priv->tx_ring_size) { 437 struct bcm_enet_desc *desc; 438 struct sk_buff *skb; 439 440 /* We run in a bh and fight against start_xmit, which 441 * is called with bh disabled */ 442 spin_lock(&priv->tx_lock); 443 444 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; 445 446 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { 447 spin_unlock(&priv->tx_lock); 448 break; 449 } 450 451 /* ensure other field of the descriptor were not read 452 * before we checked ownership */ 453 rmb(); 454 455 skb = priv->tx_skb[priv->tx_dirty_desc]; 456 priv->tx_skb[priv->tx_dirty_desc] = NULL; 457 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, 458 DMA_TO_DEVICE); 459 460 priv->tx_dirty_desc++; 461 if (priv->tx_dirty_desc == priv->tx_ring_size) 462 priv->tx_dirty_desc = 0; 463 priv->tx_desc_count++; 464 465 spin_unlock(&priv->tx_lock); 466 467 if (desc->len_stat & DMADESC_UNDER_MASK) 468 dev->stats.tx_errors++; 469 470 bytes += skb->len; 471 dev_kfree_skb(skb); 472 released++; 473 } 474 475 netdev_completed_queue(dev, released, bytes); 476 477 if (netif_queue_stopped(dev) && released) 478 netif_wake_queue(dev); 479 480 return released; 481 } 482 483 /* 484 * poll func, called by network core 485 */ 486 static int bcm_enet_poll(struct napi_struct *napi, int budget) 487 { 488 struct bcm_enet_priv *priv; 489 struct net_device *dev; 490 int rx_work_done; 491 492 priv = container_of(napi, struct bcm_enet_priv, napi); 493 dev = priv->net_dev; 494 495 /* ack interrupts */ 496 enet_dmac_writel(priv, priv->dma_chan_int_mask, 497 ENETDMAC_IR, priv->rx_chan); 498 enet_dmac_writel(priv, priv->dma_chan_int_mask, 499 ENETDMAC_IR, priv->tx_chan); 500 501 /* reclaim sent skb */ 502 bcm_enet_tx_reclaim(dev, 0); 503 504 spin_lock(&priv->rx_lock); 505 rx_work_done = bcm_enet_receive_queue(dev, budget); 506 spin_unlock(&priv->rx_lock); 507 508 if (rx_work_done >= budget) { 509 /* rx queue is not yet empty/clean */ 510 return rx_work_done; 511 } 512 513 /* no more packet in rx/tx queue, remove device from poll 514 * queue */ 515 napi_complete_done(napi, rx_work_done); 516 517 /* restore rx/tx interrupt */ 518 enet_dmac_writel(priv, priv->dma_chan_int_mask, 519 ENETDMAC_IRMASK, priv->rx_chan); 520 enet_dmac_writel(priv, priv->dma_chan_int_mask, 521 ENETDMAC_IRMASK, priv->tx_chan); 522 523 return rx_work_done; 524 } 525 526 /* 527 * mac interrupt handler 528 */ 529 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) 530 { 531 struct net_device *dev; 532 struct bcm_enet_priv *priv; 533 u32 stat; 534 535 dev = dev_id; 536 priv = netdev_priv(dev); 537 538 stat = enet_readl(priv, ENET_IR_REG); 539 if (!(stat & ENET_IR_MIB)) 540 return IRQ_NONE; 541 542 /* clear & mask interrupt */ 543 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 544 enet_writel(priv, 0, ENET_IRMASK_REG); 545 546 /* read mib registers in workqueue */ 547 schedule_work(&priv->mib_update_task); 548 549 return IRQ_HANDLED; 550 } 551 552 /* 553 * rx/tx dma interrupt handler 554 */ 555 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) 556 { 557 struct net_device *dev; 558 struct bcm_enet_priv *priv; 559 560 dev = dev_id; 561 priv = netdev_priv(dev); 562 563 /* mask rx/tx interrupts */ 564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 565 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 566 567 napi_schedule(&priv->napi); 568 569 return IRQ_HANDLED; 570 } 571 572 /* 573 * tx request callback 574 */ 575 static netdev_tx_t 576 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) 577 { 578 struct bcm_enet_priv *priv; 579 struct bcm_enet_desc *desc; 580 u32 len_stat; 581 netdev_tx_t ret; 582 583 priv = netdev_priv(dev); 584 585 /* lock against tx reclaim */ 586 spin_lock(&priv->tx_lock); 587 588 /* make sure the tx hw queue is not full, should not happen 589 * since we stop queue before it's the case */ 590 if (unlikely(!priv->tx_desc_count)) { 591 netif_stop_queue(dev); 592 dev_err(&priv->pdev->dev, "xmit called with no tx desc " 593 "available?\n"); 594 ret = NETDEV_TX_BUSY; 595 goto out_unlock; 596 } 597 598 /* pad small packets sent on a switch device */ 599 if (priv->enet_is_sw && skb->len < 64) { 600 int needed = 64 - skb->len; 601 char *data; 602 603 if (unlikely(skb_tailroom(skb) < needed)) { 604 struct sk_buff *nskb; 605 606 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); 607 if (!nskb) { 608 ret = NETDEV_TX_BUSY; 609 goto out_unlock; 610 } 611 dev_kfree_skb(skb); 612 skb = nskb; 613 } 614 data = skb_put_zero(skb, needed); 615 } 616 617 /* point to the next available desc */ 618 desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; 619 priv->tx_skb[priv->tx_curr_desc] = skb; 620 621 /* fill descriptor */ 622 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, 623 DMA_TO_DEVICE); 624 625 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; 626 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) | 627 DMADESC_APPEND_CRC | 628 DMADESC_OWNER_MASK; 629 630 priv->tx_curr_desc++; 631 if (priv->tx_curr_desc == priv->tx_ring_size) { 632 priv->tx_curr_desc = 0; 633 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); 634 } 635 priv->tx_desc_count--; 636 637 /* dma might be already polling, make sure we update desc 638 * fields in correct order */ 639 wmb(); 640 desc->len_stat = len_stat; 641 wmb(); 642 643 netdev_sent_queue(dev, skb->len); 644 645 /* kick tx dma */ 646 if (!netdev_xmit_more() || !priv->tx_desc_count) 647 enet_dmac_writel(priv, priv->dma_chan_en_mask, 648 ENETDMAC_CHANCFG, priv->tx_chan); 649 650 /* stop queue if no more desc available */ 651 if (!priv->tx_desc_count) 652 netif_stop_queue(dev); 653 654 dev->stats.tx_bytes += skb->len; 655 dev->stats.tx_packets++; 656 ret = NETDEV_TX_OK; 657 658 out_unlock: 659 spin_unlock(&priv->tx_lock); 660 return ret; 661 } 662 663 /* 664 * Change the interface's mac address. 665 */ 666 static int bcm_enet_set_mac_address(struct net_device *dev, void *p) 667 { 668 struct bcm_enet_priv *priv; 669 struct sockaddr *addr = p; 670 u32 val; 671 672 priv = netdev_priv(dev); 673 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 674 675 /* use perfect match register 0 to store my mac address */ 676 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | 677 (dev->dev_addr[4] << 8) | dev->dev_addr[5]; 678 enet_writel(priv, val, ENET_PML_REG(0)); 679 680 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); 681 val |= ENET_PMH_DATAVALID_MASK; 682 enet_writel(priv, val, ENET_PMH_REG(0)); 683 684 return 0; 685 } 686 687 /* 688 * Change rx mode (promiscuous/allmulti) and update multicast list 689 */ 690 static void bcm_enet_set_multicast_list(struct net_device *dev) 691 { 692 struct bcm_enet_priv *priv; 693 struct netdev_hw_addr *ha; 694 u32 val; 695 int i; 696 697 priv = netdev_priv(dev); 698 699 val = enet_readl(priv, ENET_RXCFG_REG); 700 701 if (dev->flags & IFF_PROMISC) 702 val |= ENET_RXCFG_PROMISC_MASK; 703 else 704 val &= ~ENET_RXCFG_PROMISC_MASK; 705 706 /* only 3 perfect match registers left, first one is used for 707 * own mac address */ 708 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3) 709 val |= ENET_RXCFG_ALLMCAST_MASK; 710 else 711 val &= ~ENET_RXCFG_ALLMCAST_MASK; 712 713 /* no need to set perfect match registers if we catch all 714 * multicast */ 715 if (val & ENET_RXCFG_ALLMCAST_MASK) { 716 enet_writel(priv, val, ENET_RXCFG_REG); 717 return; 718 } 719 720 i = 0; 721 netdev_for_each_mc_addr(ha, dev) { 722 u8 *dmi_addr; 723 u32 tmp; 724 725 if (i == 3) 726 break; 727 /* update perfect match registers */ 728 dmi_addr = ha->addr; 729 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | 730 (dmi_addr[4] << 8) | dmi_addr[5]; 731 enet_writel(priv, tmp, ENET_PML_REG(i + 1)); 732 733 tmp = (dmi_addr[0] << 8 | dmi_addr[1]); 734 tmp |= ENET_PMH_DATAVALID_MASK; 735 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1)); 736 } 737 738 for (; i < 3; i++) { 739 enet_writel(priv, 0, ENET_PML_REG(i + 1)); 740 enet_writel(priv, 0, ENET_PMH_REG(i + 1)); 741 } 742 743 enet_writel(priv, val, ENET_RXCFG_REG); 744 } 745 746 /* 747 * set mac duplex parameters 748 */ 749 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) 750 { 751 u32 val; 752 753 val = enet_readl(priv, ENET_TXCTL_REG); 754 if (fullduplex) 755 val |= ENET_TXCTL_FD_MASK; 756 else 757 val &= ~ENET_TXCTL_FD_MASK; 758 enet_writel(priv, val, ENET_TXCTL_REG); 759 } 760 761 /* 762 * set mac flow control parameters 763 */ 764 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) 765 { 766 u32 val; 767 768 /* rx flow control (pause frame handling) */ 769 val = enet_readl(priv, ENET_RXCFG_REG); 770 if (rx_en) 771 val |= ENET_RXCFG_ENFLOW_MASK; 772 else 773 val &= ~ENET_RXCFG_ENFLOW_MASK; 774 enet_writel(priv, val, ENET_RXCFG_REG); 775 776 if (!priv->dma_has_sram) 777 return; 778 779 /* tx flow control (pause frame generation) */ 780 val = enet_dma_readl(priv, ENETDMA_CFG_REG); 781 if (tx_en) 782 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 783 else 784 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 785 enet_dma_writel(priv, val, ENETDMA_CFG_REG); 786 } 787 788 /* 789 * link changed callback (from phylib) 790 */ 791 static void bcm_enet_adjust_phy_link(struct net_device *dev) 792 { 793 struct bcm_enet_priv *priv; 794 struct phy_device *phydev; 795 int status_changed; 796 797 priv = netdev_priv(dev); 798 phydev = dev->phydev; 799 status_changed = 0; 800 801 if (priv->old_link != phydev->link) { 802 status_changed = 1; 803 priv->old_link = phydev->link; 804 } 805 806 /* reflect duplex change in mac configuration */ 807 if (phydev->link && phydev->duplex != priv->old_duplex) { 808 bcm_enet_set_duplex(priv, 809 (phydev->duplex == DUPLEX_FULL) ? 1 : 0); 810 status_changed = 1; 811 priv->old_duplex = phydev->duplex; 812 } 813 814 /* enable flow control if remote advertise it (trust phylib to 815 * check that duplex is full */ 816 if (phydev->link && phydev->pause != priv->old_pause) { 817 int rx_pause_en, tx_pause_en; 818 819 if (phydev->pause) { 820 /* pause was advertised by lpa and us */ 821 rx_pause_en = 1; 822 tx_pause_en = 1; 823 } else if (!priv->pause_auto) { 824 /* pause setting overridden by user */ 825 rx_pause_en = priv->pause_rx; 826 tx_pause_en = priv->pause_tx; 827 } else { 828 rx_pause_en = 0; 829 tx_pause_en = 0; 830 } 831 832 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); 833 status_changed = 1; 834 priv->old_pause = phydev->pause; 835 } 836 837 if (status_changed) { 838 pr_info("%s: link %s", dev->name, phydev->link ? 839 "UP" : "DOWN"); 840 if (phydev->link) 841 pr_cont(" - %d/%s - flow control %s", phydev->speed, 842 DUPLEX_FULL == phydev->duplex ? "full" : "half", 843 phydev->pause == 1 ? "rx&tx" : "off"); 844 845 pr_cont("\n"); 846 } 847 } 848 849 /* 850 * link changed callback (if phylib is not used) 851 */ 852 static void bcm_enet_adjust_link(struct net_device *dev) 853 { 854 struct bcm_enet_priv *priv; 855 856 priv = netdev_priv(dev); 857 bcm_enet_set_duplex(priv, priv->force_duplex_full); 858 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); 859 netif_carrier_on(dev); 860 861 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", 862 dev->name, 863 priv->force_speed_100 ? 100 : 10, 864 priv->force_duplex_full ? "full" : "half", 865 priv->pause_rx ? "rx" : "off", 866 priv->pause_tx ? "tx" : "off"); 867 } 868 869 static void bcm_enet_free_rx_buf_ring(struct device *kdev, struct bcm_enet_priv *priv) 870 { 871 int i; 872 873 for (i = 0; i < priv->rx_ring_size; i++) { 874 struct bcm_enet_desc *desc; 875 876 if (!priv->rx_buf[i]) 877 continue; 878 879 desc = &priv->rx_desc_cpu[i]; 880 dma_unmap_single(kdev, desc->address, priv->rx_buf_size, 881 DMA_FROM_DEVICE); 882 skb_free_frag(priv->rx_buf[i]); 883 } 884 kfree(priv->rx_buf); 885 } 886 887 /* 888 * open callback, allocate dma rings & buffers and start rx operation 889 */ 890 static int bcm_enet_open(struct net_device *dev) 891 { 892 struct bcm_enet_priv *priv; 893 struct sockaddr addr; 894 struct device *kdev; 895 struct phy_device *phydev; 896 int i, ret; 897 unsigned int size; 898 char phy_id[MII_BUS_ID_SIZE + 3]; 899 void *p; 900 u32 val; 901 902 priv = netdev_priv(dev); 903 kdev = &priv->pdev->dev; 904 905 if (priv->has_phy) { 906 /* connect to PHY */ 907 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 908 priv->mii_bus->id, priv->phy_id); 909 910 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, 911 PHY_INTERFACE_MODE_MII); 912 913 if (IS_ERR(phydev)) { 914 dev_err(kdev, "could not attach to PHY\n"); 915 return PTR_ERR(phydev); 916 } 917 918 /* mask with MAC supported features */ 919 phy_support_sym_pause(phydev); 920 phy_set_max_speed(phydev, SPEED_100); 921 phy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx, 922 priv->pause_auto); 923 924 phy_attached_info(phydev); 925 926 priv->old_link = 0; 927 priv->old_duplex = -1; 928 priv->old_pause = -1; 929 } else { 930 phydev = NULL; 931 } 932 933 /* mask all interrupts and request them */ 934 enet_writel(priv, 0, ENET_IRMASK_REG); 935 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 936 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 937 938 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); 939 if (ret) 940 goto out_phy_disconnect; 941 942 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, 943 dev->name, dev); 944 if (ret) 945 goto out_freeirq; 946 947 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, 948 0, dev->name, dev); 949 if (ret) 950 goto out_freeirq_rx; 951 952 /* initialize perfect match registers */ 953 for (i = 0; i < 4; i++) { 954 enet_writel(priv, 0, ENET_PML_REG(i)); 955 enet_writel(priv, 0, ENET_PMH_REG(i)); 956 } 957 958 /* write device mac address */ 959 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); 960 bcm_enet_set_mac_address(dev, &addr); 961 962 /* allocate rx dma ring */ 963 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); 964 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); 965 if (!p) { 966 ret = -ENOMEM; 967 goto out_freeirq_tx; 968 } 969 970 priv->rx_desc_alloc_size = size; 971 priv->rx_desc_cpu = p; 972 973 /* allocate tx dma ring */ 974 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); 975 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); 976 if (!p) { 977 ret = -ENOMEM; 978 goto out_free_rx_ring; 979 } 980 981 priv->tx_desc_alloc_size = size; 982 priv->tx_desc_cpu = p; 983 984 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *), 985 GFP_KERNEL); 986 if (!priv->tx_skb) { 987 ret = -ENOMEM; 988 goto out_free_tx_ring; 989 } 990 991 priv->tx_desc_count = priv->tx_ring_size; 992 priv->tx_dirty_desc = 0; 993 priv->tx_curr_desc = 0; 994 spin_lock_init(&priv->tx_lock); 995 996 /* init & fill rx ring with buffers */ 997 priv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *), 998 GFP_KERNEL); 999 if (!priv->rx_buf) { 1000 ret = -ENOMEM; 1001 goto out_free_tx_skb; 1002 } 1003 1004 priv->rx_desc_count = 0; 1005 priv->rx_dirty_desc = 0; 1006 priv->rx_curr_desc = 0; 1007 1008 /* initialize flow control buffer allocation */ 1009 if (priv->dma_has_sram) 1010 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 1011 ENETDMA_BUFALLOC_REG(priv->rx_chan)); 1012 else 1013 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 1014 ENETDMAC_BUFALLOC, priv->rx_chan); 1015 1016 if (bcm_enet_refill_rx(dev, false)) { 1017 dev_err(kdev, "cannot allocate rx buffer queue\n"); 1018 ret = -ENOMEM; 1019 goto out; 1020 } 1021 1022 /* write rx & tx ring addresses */ 1023 if (priv->dma_has_sram) { 1024 enet_dmas_writel(priv, priv->rx_desc_dma, 1025 ENETDMAS_RSTART_REG, priv->rx_chan); 1026 enet_dmas_writel(priv, priv->tx_desc_dma, 1027 ENETDMAS_RSTART_REG, priv->tx_chan); 1028 } else { 1029 enet_dmac_writel(priv, priv->rx_desc_dma, 1030 ENETDMAC_RSTART, priv->rx_chan); 1031 enet_dmac_writel(priv, priv->tx_desc_dma, 1032 ENETDMAC_RSTART, priv->tx_chan); 1033 } 1034 1035 /* clear remaining state ram for rx & tx channel */ 1036 if (priv->dma_has_sram) { 1037 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); 1038 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); 1039 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); 1040 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); 1041 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); 1042 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); 1043 } else { 1044 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan); 1045 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan); 1046 } 1047 1048 /* set max rx/tx length */ 1049 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); 1050 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); 1051 1052 /* set dma maximum burst len */ 1053 enet_dmac_writel(priv, priv->dma_maxburst, 1054 ENETDMAC_MAXBURST, priv->rx_chan); 1055 enet_dmac_writel(priv, priv->dma_maxburst, 1056 ENETDMAC_MAXBURST, priv->tx_chan); 1057 1058 /* set correct transmit fifo watermark */ 1059 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); 1060 1061 /* set flow control low/high threshold to 1/3 / 2/3 */ 1062 if (priv->dma_has_sram) { 1063 val = priv->rx_ring_size / 3; 1064 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); 1065 val = (priv->rx_ring_size * 2) / 3; 1066 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); 1067 } else { 1068 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan); 1069 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan); 1070 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan); 1071 } 1072 1073 /* all set, enable mac and interrupts, start dma engine and 1074 * kick rx dma channel */ 1075 wmb(); 1076 val = enet_readl(priv, ENET_CTL_REG); 1077 val |= ENET_CTL_ENABLE_MASK; 1078 enet_writel(priv, val, ENET_CTL_REG); 1079 if (priv->dma_has_sram) 1080 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); 1081 enet_dmac_writel(priv, priv->dma_chan_en_mask, 1082 ENETDMAC_CHANCFG, priv->rx_chan); 1083 1084 /* watch "mib counters about to overflow" interrupt */ 1085 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 1086 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 1087 1088 /* watch "packet transferred" interrupt in rx and tx */ 1089 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1090 ENETDMAC_IR, priv->rx_chan); 1091 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1092 ENETDMAC_IR, priv->tx_chan); 1093 1094 /* make sure we enable napi before rx interrupt */ 1095 napi_enable(&priv->napi); 1096 1097 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1098 ENETDMAC_IRMASK, priv->rx_chan); 1099 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1100 ENETDMAC_IRMASK, priv->tx_chan); 1101 1102 if (phydev) 1103 phy_start(phydev); 1104 else 1105 bcm_enet_adjust_link(dev); 1106 1107 netif_start_queue(dev); 1108 return 0; 1109 1110 out: 1111 bcm_enet_free_rx_buf_ring(kdev, priv); 1112 1113 out_free_tx_skb: 1114 kfree(priv->tx_skb); 1115 1116 out_free_tx_ring: 1117 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1118 priv->tx_desc_cpu, priv->tx_desc_dma); 1119 1120 out_free_rx_ring: 1121 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1122 priv->rx_desc_cpu, priv->rx_desc_dma); 1123 1124 out_freeirq_tx: 1125 free_irq(priv->irq_tx, dev); 1126 1127 out_freeirq_rx: 1128 free_irq(priv->irq_rx, dev); 1129 1130 out_freeirq: 1131 free_irq(dev->irq, dev); 1132 1133 out_phy_disconnect: 1134 if (phydev) 1135 phy_disconnect(phydev); 1136 1137 return ret; 1138 } 1139 1140 /* 1141 * disable mac 1142 */ 1143 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) 1144 { 1145 int limit; 1146 u32 val; 1147 1148 val = enet_readl(priv, ENET_CTL_REG); 1149 val |= ENET_CTL_DISABLE_MASK; 1150 enet_writel(priv, val, ENET_CTL_REG); 1151 1152 limit = 1000; 1153 do { 1154 u32 val; 1155 1156 val = enet_readl(priv, ENET_CTL_REG); 1157 if (!(val & ENET_CTL_DISABLE_MASK)) 1158 break; 1159 udelay(1); 1160 } while (limit--); 1161 } 1162 1163 /* 1164 * disable dma in given channel 1165 */ 1166 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) 1167 { 1168 int limit; 1169 1170 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan); 1171 1172 limit = 1000; 1173 do { 1174 u32 val; 1175 1176 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan); 1177 if (!(val & ENETDMAC_CHANCFG_EN_MASK)) 1178 break; 1179 udelay(1); 1180 } while (limit--); 1181 } 1182 1183 /* 1184 * stop callback 1185 */ 1186 static int bcm_enet_stop(struct net_device *dev) 1187 { 1188 struct bcm_enet_priv *priv; 1189 struct device *kdev; 1190 1191 priv = netdev_priv(dev); 1192 kdev = &priv->pdev->dev; 1193 1194 netif_stop_queue(dev); 1195 netdev_reset_queue(dev); 1196 napi_disable(&priv->napi); 1197 if (priv->has_phy) 1198 phy_stop(dev->phydev); 1199 del_timer_sync(&priv->rx_timeout); 1200 1201 /* mask all interrupts */ 1202 enet_writel(priv, 0, ENET_IRMASK_REG); 1203 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 1204 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 1205 1206 /* make sure no mib update is scheduled */ 1207 cancel_work_sync(&priv->mib_update_task); 1208 1209 /* disable dma & mac */ 1210 bcm_enet_disable_dma(priv, priv->tx_chan); 1211 bcm_enet_disable_dma(priv, priv->rx_chan); 1212 bcm_enet_disable_mac(priv); 1213 1214 /* force reclaim of all tx buffers */ 1215 bcm_enet_tx_reclaim(dev, 1); 1216 1217 /* free the rx buffer ring */ 1218 bcm_enet_free_rx_buf_ring(kdev, priv); 1219 1220 /* free remaining allocated memory */ 1221 kfree(priv->tx_skb); 1222 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1223 priv->rx_desc_cpu, priv->rx_desc_dma); 1224 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1225 priv->tx_desc_cpu, priv->tx_desc_dma); 1226 free_irq(priv->irq_tx, dev); 1227 free_irq(priv->irq_rx, dev); 1228 free_irq(dev->irq, dev); 1229 1230 /* release phy */ 1231 if (priv->has_phy) 1232 phy_disconnect(dev->phydev); 1233 1234 return 0; 1235 } 1236 1237 /* 1238 * ethtool callbacks 1239 */ 1240 struct bcm_enet_stats { 1241 char stat_string[ETH_GSTRING_LEN]; 1242 int sizeof_stat; 1243 int stat_offset; 1244 int mib_reg; 1245 }; 1246 1247 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ 1248 offsetof(struct bcm_enet_priv, m) 1249 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \ 1250 offsetof(struct net_device_stats, m) 1251 1252 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { 1253 { "rx_packets", DEV_STAT(rx_packets), -1 }, 1254 { "tx_packets", DEV_STAT(tx_packets), -1 }, 1255 { "rx_bytes", DEV_STAT(rx_bytes), -1 }, 1256 { "tx_bytes", DEV_STAT(tx_bytes), -1 }, 1257 { "rx_errors", DEV_STAT(rx_errors), -1 }, 1258 { "tx_errors", DEV_STAT(tx_errors), -1 }, 1259 { "rx_dropped", DEV_STAT(rx_dropped), -1 }, 1260 { "tx_dropped", DEV_STAT(tx_dropped), -1 }, 1261 1262 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, 1263 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, 1264 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, 1265 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, 1266 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, 1267 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, 1268 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, 1269 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, 1270 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, 1271 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, 1272 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, 1273 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, 1274 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, 1275 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, 1276 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, 1277 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, 1278 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, 1279 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, 1280 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, 1281 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, 1282 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, 1283 1284 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, 1285 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, 1286 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, 1287 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, 1288 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, 1289 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, 1290 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, 1291 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, 1292 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, 1293 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, 1294 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, 1295 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, 1296 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, 1297 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, 1298 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, 1299 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, 1300 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, 1301 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, 1302 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, 1303 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, 1304 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, 1305 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, 1306 1307 }; 1308 1309 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats) 1310 1311 static const u32 unused_mib_regs[] = { 1312 ETH_MIB_TX_ALL_OCTETS, 1313 ETH_MIB_TX_ALL_PKTS, 1314 ETH_MIB_RX_ALL_OCTETS, 1315 ETH_MIB_RX_ALL_PKTS, 1316 }; 1317 1318 1319 static void bcm_enet_get_drvinfo(struct net_device *netdev, 1320 struct ethtool_drvinfo *drvinfo) 1321 { 1322 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver)); 1323 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); 1324 } 1325 1326 static int bcm_enet_get_sset_count(struct net_device *netdev, 1327 int string_set) 1328 { 1329 switch (string_set) { 1330 case ETH_SS_STATS: 1331 return BCM_ENET_STATS_LEN; 1332 default: 1333 return -EINVAL; 1334 } 1335 } 1336 1337 static void bcm_enet_get_strings(struct net_device *netdev, 1338 u32 stringset, u8 *data) 1339 { 1340 int i; 1341 1342 switch (stringset) { 1343 case ETH_SS_STATS: 1344 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1345 memcpy(data + i * ETH_GSTRING_LEN, 1346 bcm_enet_gstrings_stats[i].stat_string, 1347 ETH_GSTRING_LEN); 1348 } 1349 break; 1350 } 1351 } 1352 1353 static void update_mib_counters(struct bcm_enet_priv *priv) 1354 { 1355 int i; 1356 1357 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1358 const struct bcm_enet_stats *s; 1359 u32 val; 1360 char *p; 1361 1362 s = &bcm_enet_gstrings_stats[i]; 1363 if (s->mib_reg == -1) 1364 continue; 1365 1366 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); 1367 p = (char *)priv + s->stat_offset; 1368 1369 if (s->sizeof_stat == sizeof(u64)) 1370 *(u64 *)p += val; 1371 else 1372 *(u32 *)p += val; 1373 } 1374 1375 /* also empty unused mib counters to make sure mib counter 1376 * overflow interrupt is cleared */ 1377 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) 1378 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); 1379 } 1380 1381 static void bcm_enet_update_mib_counters_defer(struct work_struct *t) 1382 { 1383 struct bcm_enet_priv *priv; 1384 1385 priv = container_of(t, struct bcm_enet_priv, mib_update_task); 1386 mutex_lock(&priv->mib_update_lock); 1387 update_mib_counters(priv); 1388 mutex_unlock(&priv->mib_update_lock); 1389 1390 /* reenable mib interrupt */ 1391 if (netif_running(priv->net_dev)) 1392 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 1393 } 1394 1395 static void bcm_enet_get_ethtool_stats(struct net_device *netdev, 1396 struct ethtool_stats *stats, 1397 u64 *data) 1398 { 1399 struct bcm_enet_priv *priv; 1400 int i; 1401 1402 priv = netdev_priv(netdev); 1403 1404 mutex_lock(&priv->mib_update_lock); 1405 update_mib_counters(priv); 1406 1407 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1408 const struct bcm_enet_stats *s; 1409 char *p; 1410 1411 s = &bcm_enet_gstrings_stats[i]; 1412 if (s->mib_reg == -1) 1413 p = (char *)&netdev->stats; 1414 else 1415 p = (char *)priv; 1416 p += s->stat_offset; 1417 data[i] = (s->sizeof_stat == sizeof(u64)) ? 1418 *(u64 *)p : *(u32 *)p; 1419 } 1420 mutex_unlock(&priv->mib_update_lock); 1421 } 1422 1423 static int bcm_enet_nway_reset(struct net_device *dev) 1424 { 1425 struct bcm_enet_priv *priv; 1426 1427 priv = netdev_priv(dev); 1428 if (priv->has_phy) 1429 return phy_ethtool_nway_reset(dev); 1430 1431 return -EOPNOTSUPP; 1432 } 1433 1434 static int bcm_enet_get_link_ksettings(struct net_device *dev, 1435 struct ethtool_link_ksettings *cmd) 1436 { 1437 struct bcm_enet_priv *priv; 1438 u32 supported, advertising; 1439 1440 priv = netdev_priv(dev); 1441 1442 if (priv->has_phy) { 1443 if (!dev->phydev) 1444 return -ENODEV; 1445 1446 phy_ethtool_ksettings_get(dev->phydev, cmd); 1447 1448 return 0; 1449 } else { 1450 cmd->base.autoneg = 0; 1451 cmd->base.speed = (priv->force_speed_100) ? 1452 SPEED_100 : SPEED_10; 1453 cmd->base.duplex = (priv->force_duplex_full) ? 1454 DUPLEX_FULL : DUPLEX_HALF; 1455 supported = ADVERTISED_10baseT_Half | 1456 ADVERTISED_10baseT_Full | 1457 ADVERTISED_100baseT_Half | 1458 ADVERTISED_100baseT_Full; 1459 advertising = 0; 1460 ethtool_convert_legacy_u32_to_link_mode( 1461 cmd->link_modes.supported, supported); 1462 ethtool_convert_legacy_u32_to_link_mode( 1463 cmd->link_modes.advertising, advertising); 1464 cmd->base.port = PORT_MII; 1465 } 1466 return 0; 1467 } 1468 1469 static int bcm_enet_set_link_ksettings(struct net_device *dev, 1470 const struct ethtool_link_ksettings *cmd) 1471 { 1472 struct bcm_enet_priv *priv; 1473 1474 priv = netdev_priv(dev); 1475 if (priv->has_phy) { 1476 if (!dev->phydev) 1477 return -ENODEV; 1478 return phy_ethtool_ksettings_set(dev->phydev, cmd); 1479 } else { 1480 1481 if (cmd->base.autoneg || 1482 (cmd->base.speed != SPEED_100 && 1483 cmd->base.speed != SPEED_10) || 1484 cmd->base.port != PORT_MII) 1485 return -EINVAL; 1486 1487 priv->force_speed_100 = 1488 (cmd->base.speed == SPEED_100) ? 1 : 0; 1489 priv->force_duplex_full = 1490 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0; 1491 1492 if (netif_running(dev)) 1493 bcm_enet_adjust_link(dev); 1494 return 0; 1495 } 1496 } 1497 1498 static void bcm_enet_get_ringparam(struct net_device *dev, 1499 struct ethtool_ringparam *ering) 1500 { 1501 struct bcm_enet_priv *priv; 1502 1503 priv = netdev_priv(dev); 1504 1505 /* rx/tx ring is actually only limited by memory */ 1506 ering->rx_max_pending = 8192; 1507 ering->tx_max_pending = 8192; 1508 ering->rx_pending = priv->rx_ring_size; 1509 ering->tx_pending = priv->tx_ring_size; 1510 } 1511 1512 static int bcm_enet_set_ringparam(struct net_device *dev, 1513 struct ethtool_ringparam *ering) 1514 { 1515 struct bcm_enet_priv *priv; 1516 int was_running; 1517 1518 priv = netdev_priv(dev); 1519 1520 was_running = 0; 1521 if (netif_running(dev)) { 1522 bcm_enet_stop(dev); 1523 was_running = 1; 1524 } 1525 1526 priv->rx_ring_size = ering->rx_pending; 1527 priv->tx_ring_size = ering->tx_pending; 1528 1529 if (was_running) { 1530 int err; 1531 1532 err = bcm_enet_open(dev); 1533 if (err) 1534 dev_close(dev); 1535 else 1536 bcm_enet_set_multicast_list(dev); 1537 } 1538 return 0; 1539 } 1540 1541 static void bcm_enet_get_pauseparam(struct net_device *dev, 1542 struct ethtool_pauseparam *ecmd) 1543 { 1544 struct bcm_enet_priv *priv; 1545 1546 priv = netdev_priv(dev); 1547 ecmd->autoneg = priv->pause_auto; 1548 ecmd->rx_pause = priv->pause_rx; 1549 ecmd->tx_pause = priv->pause_tx; 1550 } 1551 1552 static int bcm_enet_set_pauseparam(struct net_device *dev, 1553 struct ethtool_pauseparam *ecmd) 1554 { 1555 struct bcm_enet_priv *priv; 1556 1557 priv = netdev_priv(dev); 1558 1559 if (priv->has_phy) { 1560 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { 1561 /* asymetric pause mode not supported, 1562 * actually possible but integrated PHY has RO 1563 * asym_pause bit */ 1564 return -EINVAL; 1565 } 1566 } else { 1567 /* no pause autoneg on direct mii connection */ 1568 if (ecmd->autoneg) 1569 return -EINVAL; 1570 } 1571 1572 priv->pause_auto = ecmd->autoneg; 1573 priv->pause_rx = ecmd->rx_pause; 1574 priv->pause_tx = ecmd->tx_pause; 1575 1576 return 0; 1577 } 1578 1579 static const struct ethtool_ops bcm_enet_ethtool_ops = { 1580 .get_strings = bcm_enet_get_strings, 1581 .get_sset_count = bcm_enet_get_sset_count, 1582 .get_ethtool_stats = bcm_enet_get_ethtool_stats, 1583 .nway_reset = bcm_enet_nway_reset, 1584 .get_drvinfo = bcm_enet_get_drvinfo, 1585 .get_link = ethtool_op_get_link, 1586 .get_ringparam = bcm_enet_get_ringparam, 1587 .set_ringparam = bcm_enet_set_ringparam, 1588 .get_pauseparam = bcm_enet_get_pauseparam, 1589 .set_pauseparam = bcm_enet_set_pauseparam, 1590 .get_link_ksettings = bcm_enet_get_link_ksettings, 1591 .set_link_ksettings = bcm_enet_set_link_ksettings, 1592 }; 1593 1594 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1595 { 1596 struct bcm_enet_priv *priv; 1597 1598 priv = netdev_priv(dev); 1599 if (priv->has_phy) { 1600 if (!dev->phydev) 1601 return -ENODEV; 1602 return phy_mii_ioctl(dev->phydev, rq, cmd); 1603 } else { 1604 struct mii_if_info mii; 1605 1606 mii.dev = dev; 1607 mii.mdio_read = bcm_enet_mdio_read_mii; 1608 mii.mdio_write = bcm_enet_mdio_write_mii; 1609 mii.phy_id = 0; 1610 mii.phy_id_mask = 0x3f; 1611 mii.reg_num_mask = 0x1f; 1612 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); 1613 } 1614 } 1615 1616 /* 1617 * adjust mtu, can't be called while device is running 1618 */ 1619 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) 1620 { 1621 struct bcm_enet_priv *priv = netdev_priv(dev); 1622 int actual_mtu = new_mtu; 1623 1624 if (netif_running(dev)) 1625 return -EBUSY; 1626 1627 /* add ethernet header + vlan tag size */ 1628 actual_mtu += VLAN_ETH_HLEN; 1629 1630 /* 1631 * setup maximum size before we get overflow mark in 1632 * descriptor, note that this will not prevent reception of 1633 * big frames, they will be split into multiple buffers 1634 * anyway 1635 */ 1636 priv->hw_mtu = actual_mtu; 1637 1638 /* 1639 * align rx buffer size to dma burst len, account FCS since 1640 * it's appended 1641 */ 1642 priv->rx_buf_size = ALIGN(actual_mtu + ETH_FCS_LEN, 1643 priv->dma_maxburst * 4); 1644 1645 priv->rx_frag_size = SKB_DATA_ALIGN(priv->rx_buf_offset + priv->rx_buf_size) + 1646 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1647 1648 dev->mtu = new_mtu; 1649 return 0; 1650 } 1651 1652 /* 1653 * preinit hardware to allow mii operation while device is down 1654 */ 1655 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) 1656 { 1657 u32 val; 1658 int limit; 1659 1660 /* make sure mac is disabled */ 1661 bcm_enet_disable_mac(priv); 1662 1663 /* soft reset mac */ 1664 val = ENET_CTL_SRESET_MASK; 1665 enet_writel(priv, val, ENET_CTL_REG); 1666 wmb(); 1667 1668 limit = 1000; 1669 do { 1670 val = enet_readl(priv, ENET_CTL_REG); 1671 if (!(val & ENET_CTL_SRESET_MASK)) 1672 break; 1673 udelay(1); 1674 } while (limit--); 1675 1676 /* select correct mii interface */ 1677 val = enet_readl(priv, ENET_CTL_REG); 1678 if (priv->use_external_mii) 1679 val |= ENET_CTL_EPHYSEL_MASK; 1680 else 1681 val &= ~ENET_CTL_EPHYSEL_MASK; 1682 enet_writel(priv, val, ENET_CTL_REG); 1683 1684 /* turn on mdc clock */ 1685 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | 1686 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); 1687 1688 /* set mib counters to self-clear when read */ 1689 val = enet_readl(priv, ENET_MIBCTL_REG); 1690 val |= ENET_MIBCTL_RDCLEAR_MASK; 1691 enet_writel(priv, val, ENET_MIBCTL_REG); 1692 } 1693 1694 static const struct net_device_ops bcm_enet_ops = { 1695 .ndo_open = bcm_enet_open, 1696 .ndo_stop = bcm_enet_stop, 1697 .ndo_start_xmit = bcm_enet_start_xmit, 1698 .ndo_set_mac_address = bcm_enet_set_mac_address, 1699 .ndo_set_rx_mode = bcm_enet_set_multicast_list, 1700 .ndo_do_ioctl = bcm_enet_ioctl, 1701 .ndo_change_mtu = bcm_enet_change_mtu, 1702 }; 1703 1704 /* 1705 * allocate netdevice, request register memory and register device. 1706 */ 1707 static int bcm_enet_probe(struct platform_device *pdev) 1708 { 1709 struct bcm_enet_priv *priv; 1710 struct net_device *dev; 1711 struct bcm63xx_enet_platform_data *pd; 1712 struct resource *res_irq, *res_irq_rx, *res_irq_tx; 1713 struct mii_bus *bus; 1714 int i, ret; 1715 1716 if (!bcm_enet_shared_base[0]) 1717 return -EPROBE_DEFER; 1718 1719 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1720 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 1721 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); 1722 if (!res_irq || !res_irq_rx || !res_irq_tx) 1723 return -ENODEV; 1724 1725 dev = alloc_etherdev(sizeof(*priv)); 1726 if (!dev) 1727 return -ENOMEM; 1728 priv = netdev_priv(dev); 1729 1730 priv->enet_is_sw = false; 1731 priv->dma_maxburst = BCMENET_DMA_MAXBURST; 1732 priv->rx_buf_offset = NET_SKB_PAD; 1733 1734 ret = bcm_enet_change_mtu(dev, dev->mtu); 1735 if (ret) 1736 goto out; 1737 1738 priv->base = devm_platform_ioremap_resource(pdev, 0); 1739 if (IS_ERR(priv->base)) { 1740 ret = PTR_ERR(priv->base); 1741 goto out; 1742 } 1743 1744 dev->irq = priv->irq = res_irq->start; 1745 priv->irq_rx = res_irq_rx->start; 1746 priv->irq_tx = res_irq_tx->start; 1747 1748 priv->mac_clk = devm_clk_get(&pdev->dev, "enet"); 1749 if (IS_ERR(priv->mac_clk)) { 1750 ret = PTR_ERR(priv->mac_clk); 1751 goto out; 1752 } 1753 ret = clk_prepare_enable(priv->mac_clk); 1754 if (ret) 1755 goto out; 1756 1757 /* initialize default and fetch platform data */ 1758 priv->rx_ring_size = BCMENET_DEF_RX_DESC; 1759 priv->tx_ring_size = BCMENET_DEF_TX_DESC; 1760 1761 pd = dev_get_platdata(&pdev->dev); 1762 if (pd) { 1763 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 1764 priv->has_phy = pd->has_phy; 1765 priv->phy_id = pd->phy_id; 1766 priv->has_phy_interrupt = pd->has_phy_interrupt; 1767 priv->phy_interrupt = pd->phy_interrupt; 1768 priv->use_external_mii = !pd->use_internal_phy; 1769 priv->pause_auto = pd->pause_auto; 1770 priv->pause_rx = pd->pause_rx; 1771 priv->pause_tx = pd->pause_tx; 1772 priv->force_duplex_full = pd->force_duplex_full; 1773 priv->force_speed_100 = pd->force_speed_100; 1774 priv->dma_chan_en_mask = pd->dma_chan_en_mask; 1775 priv->dma_chan_int_mask = pd->dma_chan_int_mask; 1776 priv->dma_chan_width = pd->dma_chan_width; 1777 priv->dma_has_sram = pd->dma_has_sram; 1778 priv->dma_desc_shift = pd->dma_desc_shift; 1779 priv->rx_chan = pd->rx_chan; 1780 priv->tx_chan = pd->tx_chan; 1781 } 1782 1783 if (priv->has_phy && !priv->use_external_mii) { 1784 /* using internal PHY, enable clock */ 1785 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy"); 1786 if (IS_ERR(priv->phy_clk)) { 1787 ret = PTR_ERR(priv->phy_clk); 1788 priv->phy_clk = NULL; 1789 goto out_disable_clk_mac; 1790 } 1791 ret = clk_prepare_enable(priv->phy_clk); 1792 if (ret) 1793 goto out_disable_clk_mac; 1794 } 1795 1796 /* do minimal hardware init to be able to probe mii bus */ 1797 bcm_enet_hw_preinit(priv); 1798 1799 /* MII bus registration */ 1800 if (priv->has_phy) { 1801 1802 priv->mii_bus = mdiobus_alloc(); 1803 if (!priv->mii_bus) { 1804 ret = -ENOMEM; 1805 goto out_uninit_hw; 1806 } 1807 1808 bus = priv->mii_bus; 1809 bus->name = "bcm63xx_enet MII bus"; 1810 bus->parent = &pdev->dev; 1811 bus->priv = priv; 1812 bus->read = bcm_enet_mdio_read_phylib; 1813 bus->write = bcm_enet_mdio_write_phylib; 1814 sprintf(bus->id, "%s-%d", pdev->name, pdev->id); 1815 1816 /* only probe bus where we think the PHY is, because 1817 * the mdio read operation return 0 instead of 0xffff 1818 * if a slave is not present on hw */ 1819 bus->phy_mask = ~(1 << priv->phy_id); 1820 1821 if (priv->has_phy_interrupt) 1822 bus->irq[priv->phy_id] = priv->phy_interrupt; 1823 1824 ret = mdiobus_register(bus); 1825 if (ret) { 1826 dev_err(&pdev->dev, "unable to register mdio bus\n"); 1827 goto out_free_mdio; 1828 } 1829 } else { 1830 1831 /* run platform code to initialize PHY device */ 1832 if (pd && pd->mii_config && 1833 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, 1834 bcm_enet_mdio_write_mii)) { 1835 dev_err(&pdev->dev, "unable to configure mdio bus\n"); 1836 goto out_uninit_hw; 1837 } 1838 } 1839 1840 spin_lock_init(&priv->rx_lock); 1841 1842 /* init rx timeout (used for oom) */ 1843 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0); 1844 1845 /* init the mib update lock&work */ 1846 mutex_init(&priv->mib_update_lock); 1847 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); 1848 1849 /* zero mib counters */ 1850 for (i = 0; i < ENET_MIB_REG_COUNT; i++) 1851 enet_writel(priv, 0, ENET_MIB_REG(i)); 1852 1853 /* register netdevice */ 1854 dev->netdev_ops = &bcm_enet_ops; 1855 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); 1856 1857 dev->ethtool_ops = &bcm_enet_ethtool_ops; 1858 /* MTU range: 46 - 2028 */ 1859 dev->min_mtu = ETH_ZLEN - ETH_HLEN; 1860 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN; 1861 SET_NETDEV_DEV(dev, &pdev->dev); 1862 1863 ret = register_netdev(dev); 1864 if (ret) 1865 goto out_unregister_mdio; 1866 1867 netif_carrier_off(dev); 1868 platform_set_drvdata(pdev, dev); 1869 priv->pdev = pdev; 1870 priv->net_dev = dev; 1871 1872 return 0; 1873 1874 out_unregister_mdio: 1875 if (priv->mii_bus) 1876 mdiobus_unregister(priv->mii_bus); 1877 1878 out_free_mdio: 1879 if (priv->mii_bus) 1880 mdiobus_free(priv->mii_bus); 1881 1882 out_uninit_hw: 1883 /* turn off mdc clock */ 1884 enet_writel(priv, 0, ENET_MIISC_REG); 1885 clk_disable_unprepare(priv->phy_clk); 1886 1887 out_disable_clk_mac: 1888 clk_disable_unprepare(priv->mac_clk); 1889 out: 1890 free_netdev(dev); 1891 return ret; 1892 } 1893 1894 1895 /* 1896 * exit func, stops hardware and unregisters netdevice 1897 */ 1898 static int bcm_enet_remove(struct platform_device *pdev) 1899 { 1900 struct bcm_enet_priv *priv; 1901 struct net_device *dev; 1902 1903 /* stop netdevice */ 1904 dev = platform_get_drvdata(pdev); 1905 priv = netdev_priv(dev); 1906 unregister_netdev(dev); 1907 1908 /* turn off mdc clock */ 1909 enet_writel(priv, 0, ENET_MIISC_REG); 1910 1911 if (priv->has_phy) { 1912 mdiobus_unregister(priv->mii_bus); 1913 mdiobus_free(priv->mii_bus); 1914 } else { 1915 struct bcm63xx_enet_platform_data *pd; 1916 1917 pd = dev_get_platdata(&pdev->dev); 1918 if (pd && pd->mii_config) 1919 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, 1920 bcm_enet_mdio_write_mii); 1921 } 1922 1923 /* disable hw block clocks */ 1924 clk_disable_unprepare(priv->phy_clk); 1925 clk_disable_unprepare(priv->mac_clk); 1926 1927 free_netdev(dev); 1928 return 0; 1929 } 1930 1931 struct platform_driver bcm63xx_enet_driver = { 1932 .probe = bcm_enet_probe, 1933 .remove = bcm_enet_remove, 1934 .driver = { 1935 .name = "bcm63xx_enet", 1936 .owner = THIS_MODULE, 1937 }, 1938 }; 1939 1940 /* 1941 * switch mii access callbacks 1942 */ 1943 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv, 1944 int ext, int phy_id, int location) 1945 { 1946 u32 reg; 1947 int ret; 1948 1949 spin_lock_bh(&priv->enetsw_mdio_lock); 1950 enetsw_writel(priv, 0, ENETSW_MDIOC_REG); 1951 1952 reg = ENETSW_MDIOC_RD_MASK | 1953 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | 1954 (location << ENETSW_MDIOC_REG_SHIFT); 1955 1956 if (ext) 1957 reg |= ENETSW_MDIOC_EXT_MASK; 1958 1959 enetsw_writel(priv, reg, ENETSW_MDIOC_REG); 1960 udelay(50); 1961 ret = enetsw_readw(priv, ENETSW_MDIOD_REG); 1962 spin_unlock_bh(&priv->enetsw_mdio_lock); 1963 return ret; 1964 } 1965 1966 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv, 1967 int ext, int phy_id, int location, 1968 uint16_t data) 1969 { 1970 u32 reg; 1971 1972 spin_lock_bh(&priv->enetsw_mdio_lock); 1973 enetsw_writel(priv, 0, ENETSW_MDIOC_REG); 1974 1975 reg = ENETSW_MDIOC_WR_MASK | 1976 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | 1977 (location << ENETSW_MDIOC_REG_SHIFT); 1978 1979 if (ext) 1980 reg |= ENETSW_MDIOC_EXT_MASK; 1981 1982 reg |= data; 1983 1984 enetsw_writel(priv, reg, ENETSW_MDIOC_REG); 1985 udelay(50); 1986 spin_unlock_bh(&priv->enetsw_mdio_lock); 1987 } 1988 1989 static inline int bcm_enet_port_is_rgmii(int portid) 1990 { 1991 return portid >= ENETSW_RGMII_PORT0; 1992 } 1993 1994 /* 1995 * enet sw PHY polling 1996 */ 1997 static void swphy_poll_timer(struct timer_list *t) 1998 { 1999 struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll); 2000 unsigned int i; 2001 2002 for (i = 0; i < priv->num_ports; i++) { 2003 struct bcm63xx_enetsw_port *port; 2004 int val, j, up, advertise, lpa, speed, duplex, media; 2005 int external_phy = bcm_enet_port_is_rgmii(i); 2006 u8 override; 2007 2008 port = &priv->used_ports[i]; 2009 if (!port->used) 2010 continue; 2011 2012 if (port->bypass_link) 2013 continue; 2014 2015 /* dummy read to clear */ 2016 for (j = 0; j < 2; j++) 2017 val = bcmenet_sw_mdio_read(priv, external_phy, 2018 port->phy_id, MII_BMSR); 2019 2020 if (val == 0xffff) 2021 continue; 2022 2023 up = (val & BMSR_LSTATUS) ? 1 : 0; 2024 if (!(up ^ priv->sw_port_link[i])) 2025 continue; 2026 2027 priv->sw_port_link[i] = up; 2028 2029 /* link changed */ 2030 if (!up) { 2031 dev_info(&priv->pdev->dev, "link DOWN on %s\n", 2032 port->name); 2033 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, 2034 ENETSW_PORTOV_REG(i)); 2035 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | 2036 ENETSW_PTCTRL_TXDIS_MASK, 2037 ENETSW_PTCTRL_REG(i)); 2038 continue; 2039 } 2040 2041 advertise = bcmenet_sw_mdio_read(priv, external_phy, 2042 port->phy_id, MII_ADVERTISE); 2043 2044 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id, 2045 MII_LPA); 2046 2047 /* figure out media and duplex from advertise and LPA values */ 2048 media = mii_nway_result(lpa & advertise); 2049 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 2050 2051 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) 2052 speed = 100; 2053 else 2054 speed = 10; 2055 2056 if (val & BMSR_ESTATEN) { 2057 advertise = bcmenet_sw_mdio_read(priv, external_phy, 2058 port->phy_id, MII_CTRL1000); 2059 2060 lpa = bcmenet_sw_mdio_read(priv, external_phy, 2061 port->phy_id, MII_STAT1000); 2062 2063 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF) 2064 && lpa & (LPA_1000FULL | LPA_1000HALF)) { 2065 speed = 1000; 2066 duplex = (lpa & LPA_1000FULL); 2067 } 2068 } 2069 2070 dev_info(&priv->pdev->dev, 2071 "link UP on %s, %dMbps, %s-duplex\n", 2072 port->name, speed, duplex ? "full" : "half"); 2073 2074 override = ENETSW_PORTOV_ENABLE_MASK | 2075 ENETSW_PORTOV_LINKUP_MASK; 2076 2077 if (speed == 1000) 2078 override |= ENETSW_IMPOV_1000_MASK; 2079 else if (speed == 100) 2080 override |= ENETSW_IMPOV_100_MASK; 2081 if (duplex) 2082 override |= ENETSW_IMPOV_FDX_MASK; 2083 2084 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); 2085 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); 2086 } 2087 2088 priv->swphy_poll.expires = jiffies + HZ; 2089 add_timer(&priv->swphy_poll); 2090 } 2091 2092 /* 2093 * open callback, allocate dma rings & buffers and start rx operation 2094 */ 2095 static int bcm_enetsw_open(struct net_device *dev) 2096 { 2097 struct bcm_enet_priv *priv; 2098 struct device *kdev; 2099 int i, ret; 2100 unsigned int size; 2101 void *p; 2102 u32 val; 2103 2104 priv = netdev_priv(dev); 2105 kdev = &priv->pdev->dev; 2106 2107 /* mask all interrupts and request them */ 2108 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 2109 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 2110 2111 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 2112 0, dev->name, dev); 2113 if (ret) 2114 goto out_freeirq; 2115 2116 if (priv->irq_tx != -1) { 2117 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, 2118 0, dev->name, dev); 2119 if (ret) 2120 goto out_freeirq_rx; 2121 } 2122 2123 /* allocate rx dma ring */ 2124 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); 2125 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); 2126 if (!p) { 2127 dev_err(kdev, "cannot allocate rx ring %u\n", size); 2128 ret = -ENOMEM; 2129 goto out_freeirq_tx; 2130 } 2131 2132 priv->rx_desc_alloc_size = size; 2133 priv->rx_desc_cpu = p; 2134 2135 /* allocate tx dma ring */ 2136 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); 2137 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); 2138 if (!p) { 2139 dev_err(kdev, "cannot allocate tx ring\n"); 2140 ret = -ENOMEM; 2141 goto out_free_rx_ring; 2142 } 2143 2144 priv->tx_desc_alloc_size = size; 2145 priv->tx_desc_cpu = p; 2146 2147 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *), 2148 GFP_KERNEL); 2149 if (!priv->tx_skb) { 2150 dev_err(kdev, "cannot allocate tx skb queue\n"); 2151 ret = -ENOMEM; 2152 goto out_free_tx_ring; 2153 } 2154 2155 priv->tx_desc_count = priv->tx_ring_size; 2156 priv->tx_dirty_desc = 0; 2157 priv->tx_curr_desc = 0; 2158 spin_lock_init(&priv->tx_lock); 2159 2160 /* init & fill rx ring with buffers */ 2161 priv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *), 2162 GFP_KERNEL); 2163 if (!priv->rx_buf) { 2164 dev_err(kdev, "cannot allocate rx buffer queue\n"); 2165 ret = -ENOMEM; 2166 goto out_free_tx_skb; 2167 } 2168 2169 priv->rx_desc_count = 0; 2170 priv->rx_dirty_desc = 0; 2171 priv->rx_curr_desc = 0; 2172 2173 /* disable all ports */ 2174 for (i = 0; i < priv->num_ports; i++) { 2175 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, 2176 ENETSW_PORTOV_REG(i)); 2177 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | 2178 ENETSW_PTCTRL_TXDIS_MASK, 2179 ENETSW_PTCTRL_REG(i)); 2180 2181 priv->sw_port_link[i] = 0; 2182 } 2183 2184 /* reset mib */ 2185 val = enetsw_readb(priv, ENETSW_GMCR_REG); 2186 val |= ENETSW_GMCR_RST_MIB_MASK; 2187 enetsw_writeb(priv, val, ENETSW_GMCR_REG); 2188 mdelay(1); 2189 val &= ~ENETSW_GMCR_RST_MIB_MASK; 2190 enetsw_writeb(priv, val, ENETSW_GMCR_REG); 2191 mdelay(1); 2192 2193 /* force CPU port state */ 2194 val = enetsw_readb(priv, ENETSW_IMPOV_REG); 2195 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; 2196 enetsw_writeb(priv, val, ENETSW_IMPOV_REG); 2197 2198 /* enable switch forward engine */ 2199 val = enetsw_readb(priv, ENETSW_SWMODE_REG); 2200 val |= ENETSW_SWMODE_FWD_EN_MASK; 2201 enetsw_writeb(priv, val, ENETSW_SWMODE_REG); 2202 2203 /* enable jumbo on all ports */ 2204 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); 2205 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); 2206 2207 /* initialize flow control buffer allocation */ 2208 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 2209 ENETDMA_BUFALLOC_REG(priv->rx_chan)); 2210 2211 if (bcm_enet_refill_rx(dev, false)) { 2212 dev_err(kdev, "cannot allocate rx buffer queue\n"); 2213 ret = -ENOMEM; 2214 goto out; 2215 } 2216 2217 /* write rx & tx ring addresses */ 2218 enet_dmas_writel(priv, priv->rx_desc_dma, 2219 ENETDMAS_RSTART_REG, priv->rx_chan); 2220 enet_dmas_writel(priv, priv->tx_desc_dma, 2221 ENETDMAS_RSTART_REG, priv->tx_chan); 2222 2223 /* clear remaining state ram for rx & tx channel */ 2224 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); 2225 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); 2226 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); 2227 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); 2228 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); 2229 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); 2230 2231 /* set dma maximum burst len */ 2232 enet_dmac_writel(priv, priv->dma_maxburst, 2233 ENETDMAC_MAXBURST, priv->rx_chan); 2234 enet_dmac_writel(priv, priv->dma_maxburst, 2235 ENETDMAC_MAXBURST, priv->tx_chan); 2236 2237 /* set flow control low/high threshold to 1/3 / 2/3 */ 2238 val = priv->rx_ring_size / 3; 2239 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); 2240 val = (priv->rx_ring_size * 2) / 3; 2241 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); 2242 2243 /* all set, enable mac and interrupts, start dma engine and 2244 * kick rx dma channel 2245 */ 2246 wmb(); 2247 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); 2248 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK, 2249 ENETDMAC_CHANCFG, priv->rx_chan); 2250 2251 /* watch "packet transferred" interrupt in rx and tx */ 2252 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2253 ENETDMAC_IR, priv->rx_chan); 2254 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2255 ENETDMAC_IR, priv->tx_chan); 2256 2257 /* make sure we enable napi before rx interrupt */ 2258 napi_enable(&priv->napi); 2259 2260 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2261 ENETDMAC_IRMASK, priv->rx_chan); 2262 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2263 ENETDMAC_IRMASK, priv->tx_chan); 2264 2265 netif_carrier_on(dev); 2266 netif_start_queue(dev); 2267 2268 /* apply override config for bypass_link ports here. */ 2269 for (i = 0; i < priv->num_ports; i++) { 2270 struct bcm63xx_enetsw_port *port; 2271 u8 override; 2272 port = &priv->used_ports[i]; 2273 if (!port->used) 2274 continue; 2275 2276 if (!port->bypass_link) 2277 continue; 2278 2279 override = ENETSW_PORTOV_ENABLE_MASK | 2280 ENETSW_PORTOV_LINKUP_MASK; 2281 2282 switch (port->force_speed) { 2283 case 1000: 2284 override |= ENETSW_IMPOV_1000_MASK; 2285 break; 2286 case 100: 2287 override |= ENETSW_IMPOV_100_MASK; 2288 break; 2289 case 10: 2290 break; 2291 default: 2292 pr_warn("invalid forced speed on port %s: assume 10\n", 2293 port->name); 2294 break; 2295 } 2296 2297 if (port->force_duplex_full) 2298 override |= ENETSW_IMPOV_FDX_MASK; 2299 2300 2301 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); 2302 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); 2303 } 2304 2305 /* start phy polling timer */ 2306 timer_setup(&priv->swphy_poll, swphy_poll_timer, 0); 2307 mod_timer(&priv->swphy_poll, jiffies); 2308 return 0; 2309 2310 out: 2311 bcm_enet_free_rx_buf_ring(kdev, priv); 2312 2313 out_free_tx_skb: 2314 kfree(priv->tx_skb); 2315 2316 out_free_tx_ring: 2317 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 2318 priv->tx_desc_cpu, priv->tx_desc_dma); 2319 2320 out_free_rx_ring: 2321 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 2322 priv->rx_desc_cpu, priv->rx_desc_dma); 2323 2324 out_freeirq_tx: 2325 if (priv->irq_tx != -1) 2326 free_irq(priv->irq_tx, dev); 2327 2328 out_freeirq_rx: 2329 free_irq(priv->irq_rx, dev); 2330 2331 out_freeirq: 2332 return ret; 2333 } 2334 2335 /* stop callback */ 2336 static int bcm_enetsw_stop(struct net_device *dev) 2337 { 2338 struct bcm_enet_priv *priv; 2339 struct device *kdev; 2340 2341 priv = netdev_priv(dev); 2342 kdev = &priv->pdev->dev; 2343 2344 del_timer_sync(&priv->swphy_poll); 2345 netif_stop_queue(dev); 2346 netdev_reset_queue(dev); 2347 napi_disable(&priv->napi); 2348 del_timer_sync(&priv->rx_timeout); 2349 2350 /* mask all interrupts */ 2351 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 2352 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 2353 2354 /* disable dma & mac */ 2355 bcm_enet_disable_dma(priv, priv->tx_chan); 2356 bcm_enet_disable_dma(priv, priv->rx_chan); 2357 2358 /* force reclaim of all tx buffers */ 2359 bcm_enet_tx_reclaim(dev, 1); 2360 2361 /* free the rx buffer ring */ 2362 bcm_enet_free_rx_buf_ring(kdev, priv); 2363 2364 /* free remaining allocated memory */ 2365 kfree(priv->tx_skb); 2366 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 2367 priv->rx_desc_cpu, priv->rx_desc_dma); 2368 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 2369 priv->tx_desc_cpu, priv->tx_desc_dma); 2370 if (priv->irq_tx != -1) 2371 free_irq(priv->irq_tx, dev); 2372 free_irq(priv->irq_rx, dev); 2373 2374 return 0; 2375 } 2376 2377 /* try to sort out phy external status by walking the used_port field 2378 * in the bcm_enet_priv structure. in case the phy address is not 2379 * assigned to any physical port on the switch, assume it is external 2380 * (and yell at the user). 2381 */ 2382 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id) 2383 { 2384 int i; 2385 2386 for (i = 0; i < priv->num_ports; ++i) { 2387 if (!priv->used_ports[i].used) 2388 continue; 2389 if (priv->used_ports[i].phy_id == phy_id) 2390 return bcm_enet_port_is_rgmii(i); 2391 } 2392 2393 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n", 2394 phy_id); 2395 return 1; 2396 } 2397 2398 /* can't use bcmenet_sw_mdio_read directly as we need to sort out 2399 * external/internal status of the given phy_id first. 2400 */ 2401 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id, 2402 int location) 2403 { 2404 struct bcm_enet_priv *priv; 2405 2406 priv = netdev_priv(dev); 2407 return bcmenet_sw_mdio_read(priv, 2408 bcm_enetsw_phy_is_external(priv, phy_id), 2409 phy_id, location); 2410 } 2411 2412 /* can't use bcmenet_sw_mdio_write directly as we need to sort out 2413 * external/internal status of the given phy_id first. 2414 */ 2415 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id, 2416 int location, 2417 int val) 2418 { 2419 struct bcm_enet_priv *priv; 2420 2421 priv = netdev_priv(dev); 2422 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id), 2423 phy_id, location, val); 2424 } 2425 2426 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2427 { 2428 struct mii_if_info mii; 2429 2430 mii.dev = dev; 2431 mii.mdio_read = bcm_enetsw_mii_mdio_read; 2432 mii.mdio_write = bcm_enetsw_mii_mdio_write; 2433 mii.phy_id = 0; 2434 mii.phy_id_mask = 0x3f; 2435 mii.reg_num_mask = 0x1f; 2436 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); 2437 2438 } 2439 2440 static const struct net_device_ops bcm_enetsw_ops = { 2441 .ndo_open = bcm_enetsw_open, 2442 .ndo_stop = bcm_enetsw_stop, 2443 .ndo_start_xmit = bcm_enet_start_xmit, 2444 .ndo_change_mtu = bcm_enet_change_mtu, 2445 .ndo_do_ioctl = bcm_enetsw_ioctl, 2446 }; 2447 2448 2449 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = { 2450 { "rx_packets", DEV_STAT(rx_packets), -1 }, 2451 { "tx_packets", DEV_STAT(tx_packets), -1 }, 2452 { "rx_bytes", DEV_STAT(rx_bytes), -1 }, 2453 { "tx_bytes", DEV_STAT(tx_bytes), -1 }, 2454 { "rx_errors", DEV_STAT(rx_errors), -1 }, 2455 { "tx_errors", DEV_STAT(tx_errors), -1 }, 2456 { "rx_dropped", DEV_STAT(rx_dropped), -1 }, 2457 { "tx_dropped", DEV_STAT(tx_dropped), -1 }, 2458 2459 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT }, 2460 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST }, 2461 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST }, 2462 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT }, 2463 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 }, 2464 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 }, 2465 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 }, 2466 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 }, 2467 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023}, 2468 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max), 2469 ETHSW_MIB_RX_1024_1522 }, 2470 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047), 2471 ETHSW_MIB_RX_1523_2047 }, 2472 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095), 2473 ETHSW_MIB_RX_2048_4095 }, 2474 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191), 2475 ETHSW_MIB_RX_4096_8191 }, 2476 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728), 2477 ETHSW_MIB_RX_8192_9728 }, 2478 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR }, 2479 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC }, 2480 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP }, 2481 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND }, 2482 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE }, 2483 2484 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT }, 2485 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST }, 2486 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT }, 2487 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT }, 2488 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE }, 2489 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS }, 2490 2491 }; 2492 2493 #define BCM_ENETSW_STATS_LEN \ 2494 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats)) 2495 2496 static void bcm_enetsw_get_strings(struct net_device *netdev, 2497 u32 stringset, u8 *data) 2498 { 2499 int i; 2500 2501 switch (stringset) { 2502 case ETH_SS_STATS: 2503 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2504 memcpy(data + i * ETH_GSTRING_LEN, 2505 bcm_enetsw_gstrings_stats[i].stat_string, 2506 ETH_GSTRING_LEN); 2507 } 2508 break; 2509 } 2510 } 2511 2512 static int bcm_enetsw_get_sset_count(struct net_device *netdev, 2513 int string_set) 2514 { 2515 switch (string_set) { 2516 case ETH_SS_STATS: 2517 return BCM_ENETSW_STATS_LEN; 2518 default: 2519 return -EINVAL; 2520 } 2521 } 2522 2523 static void bcm_enetsw_get_drvinfo(struct net_device *netdev, 2524 struct ethtool_drvinfo *drvinfo) 2525 { 2526 strncpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver)); 2527 strncpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); 2528 } 2529 2530 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev, 2531 struct ethtool_stats *stats, 2532 u64 *data) 2533 { 2534 struct bcm_enet_priv *priv; 2535 int i; 2536 2537 priv = netdev_priv(netdev); 2538 2539 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2540 const struct bcm_enet_stats *s; 2541 u32 lo, hi; 2542 char *p; 2543 int reg; 2544 2545 s = &bcm_enetsw_gstrings_stats[i]; 2546 2547 reg = s->mib_reg; 2548 if (reg == -1) 2549 continue; 2550 2551 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg)); 2552 p = (char *)priv + s->stat_offset; 2553 2554 if (s->sizeof_stat == sizeof(u64)) { 2555 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1)); 2556 *(u64 *)p = ((u64)hi << 32 | lo); 2557 } else { 2558 *(u32 *)p = lo; 2559 } 2560 } 2561 2562 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2563 const struct bcm_enet_stats *s; 2564 char *p; 2565 2566 s = &bcm_enetsw_gstrings_stats[i]; 2567 2568 if (s->mib_reg == -1) 2569 p = (char *)&netdev->stats + s->stat_offset; 2570 else 2571 p = (char *)priv + s->stat_offset; 2572 2573 data[i] = (s->sizeof_stat == sizeof(u64)) ? 2574 *(u64 *)p : *(u32 *)p; 2575 } 2576 } 2577 2578 static void bcm_enetsw_get_ringparam(struct net_device *dev, 2579 struct ethtool_ringparam *ering) 2580 { 2581 struct bcm_enet_priv *priv; 2582 2583 priv = netdev_priv(dev); 2584 2585 /* rx/tx ring is actually only limited by memory */ 2586 ering->rx_max_pending = 8192; 2587 ering->tx_max_pending = 8192; 2588 ering->rx_mini_max_pending = 0; 2589 ering->rx_jumbo_max_pending = 0; 2590 ering->rx_pending = priv->rx_ring_size; 2591 ering->tx_pending = priv->tx_ring_size; 2592 } 2593 2594 static int bcm_enetsw_set_ringparam(struct net_device *dev, 2595 struct ethtool_ringparam *ering) 2596 { 2597 struct bcm_enet_priv *priv; 2598 int was_running; 2599 2600 priv = netdev_priv(dev); 2601 2602 was_running = 0; 2603 if (netif_running(dev)) { 2604 bcm_enetsw_stop(dev); 2605 was_running = 1; 2606 } 2607 2608 priv->rx_ring_size = ering->rx_pending; 2609 priv->tx_ring_size = ering->tx_pending; 2610 2611 if (was_running) { 2612 int err; 2613 2614 err = bcm_enetsw_open(dev); 2615 if (err) 2616 dev_close(dev); 2617 } 2618 return 0; 2619 } 2620 2621 static const struct ethtool_ops bcm_enetsw_ethtool_ops = { 2622 .get_strings = bcm_enetsw_get_strings, 2623 .get_sset_count = bcm_enetsw_get_sset_count, 2624 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats, 2625 .get_drvinfo = bcm_enetsw_get_drvinfo, 2626 .get_ringparam = bcm_enetsw_get_ringparam, 2627 .set_ringparam = bcm_enetsw_set_ringparam, 2628 }; 2629 2630 /* allocate netdevice, request register memory and register device. */ 2631 static int bcm_enetsw_probe(struct platform_device *pdev) 2632 { 2633 struct bcm_enet_priv *priv; 2634 struct net_device *dev; 2635 struct bcm63xx_enetsw_platform_data *pd; 2636 struct resource *res_mem; 2637 int ret, irq_rx, irq_tx; 2638 2639 if (!bcm_enet_shared_base[0]) 2640 return -EPROBE_DEFER; 2641 2642 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2643 irq_rx = platform_get_irq(pdev, 0); 2644 irq_tx = platform_get_irq(pdev, 1); 2645 if (!res_mem || irq_rx < 0) 2646 return -ENODEV; 2647 2648 ret = 0; 2649 dev = alloc_etherdev(sizeof(*priv)); 2650 if (!dev) 2651 return -ENOMEM; 2652 priv = netdev_priv(dev); 2653 2654 /* initialize default and fetch platform data */ 2655 priv->enet_is_sw = true; 2656 priv->irq_rx = irq_rx; 2657 priv->irq_tx = irq_tx; 2658 priv->rx_ring_size = BCMENET_DEF_RX_DESC; 2659 priv->tx_ring_size = BCMENET_DEF_TX_DESC; 2660 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST; 2661 priv->rx_buf_offset = NET_SKB_PAD + NET_IP_ALIGN; 2662 2663 pd = dev_get_platdata(&pdev->dev); 2664 if (pd) { 2665 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 2666 memcpy(priv->used_ports, pd->used_ports, 2667 sizeof(pd->used_ports)); 2668 priv->num_ports = pd->num_ports; 2669 priv->dma_has_sram = pd->dma_has_sram; 2670 priv->dma_chan_en_mask = pd->dma_chan_en_mask; 2671 priv->dma_chan_int_mask = pd->dma_chan_int_mask; 2672 priv->dma_chan_width = pd->dma_chan_width; 2673 } 2674 2675 ret = bcm_enet_change_mtu(dev, dev->mtu); 2676 if (ret) 2677 goto out; 2678 2679 priv->base = devm_ioremap_resource(&pdev->dev, res_mem); 2680 if (IS_ERR(priv->base)) { 2681 ret = PTR_ERR(priv->base); 2682 goto out; 2683 } 2684 2685 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw"); 2686 if (IS_ERR(priv->mac_clk)) { 2687 ret = PTR_ERR(priv->mac_clk); 2688 goto out; 2689 } 2690 ret = clk_prepare_enable(priv->mac_clk); 2691 if (ret) 2692 goto out; 2693 2694 priv->rx_chan = 0; 2695 priv->tx_chan = 1; 2696 spin_lock_init(&priv->rx_lock); 2697 2698 /* init rx timeout (used for oom) */ 2699 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0); 2700 2701 /* register netdevice */ 2702 dev->netdev_ops = &bcm_enetsw_ops; 2703 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); 2704 dev->ethtool_ops = &bcm_enetsw_ethtool_ops; 2705 SET_NETDEV_DEV(dev, &pdev->dev); 2706 2707 spin_lock_init(&priv->enetsw_mdio_lock); 2708 2709 ret = register_netdev(dev); 2710 if (ret) 2711 goto out_disable_clk; 2712 2713 netif_carrier_off(dev); 2714 platform_set_drvdata(pdev, dev); 2715 priv->pdev = pdev; 2716 priv->net_dev = dev; 2717 2718 return 0; 2719 2720 out_disable_clk: 2721 clk_disable_unprepare(priv->mac_clk); 2722 out: 2723 free_netdev(dev); 2724 return ret; 2725 } 2726 2727 2728 /* exit func, stops hardware and unregisters netdevice */ 2729 static int bcm_enetsw_remove(struct platform_device *pdev) 2730 { 2731 struct bcm_enet_priv *priv; 2732 struct net_device *dev; 2733 2734 /* stop netdevice */ 2735 dev = platform_get_drvdata(pdev); 2736 priv = netdev_priv(dev); 2737 unregister_netdev(dev); 2738 2739 clk_disable_unprepare(priv->mac_clk); 2740 2741 free_netdev(dev); 2742 return 0; 2743 } 2744 2745 struct platform_driver bcm63xx_enetsw_driver = { 2746 .probe = bcm_enetsw_probe, 2747 .remove = bcm_enetsw_remove, 2748 .driver = { 2749 .name = "bcm63xx_enetsw", 2750 .owner = THIS_MODULE, 2751 }, 2752 }; 2753 2754 /* reserve & remap memory space shared between all macs */ 2755 static int bcm_enet_shared_probe(struct platform_device *pdev) 2756 { 2757 void __iomem *p[3]; 2758 unsigned int i; 2759 2760 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base)); 2761 2762 for (i = 0; i < 3; i++) { 2763 p[i] = devm_platform_ioremap_resource(pdev, i); 2764 if (IS_ERR(p[i])) 2765 return PTR_ERR(p[i]); 2766 } 2767 2768 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base)); 2769 2770 return 0; 2771 } 2772 2773 static int bcm_enet_shared_remove(struct platform_device *pdev) 2774 { 2775 return 0; 2776 } 2777 2778 /* this "shared" driver is needed because both macs share a single 2779 * address space 2780 */ 2781 struct platform_driver bcm63xx_enet_shared_driver = { 2782 .probe = bcm_enet_shared_probe, 2783 .remove = bcm_enet_shared_remove, 2784 .driver = { 2785 .name = "bcm63xx_enet_shared", 2786 .owner = THIS_MODULE, 2787 }, 2788 }; 2789 2790 static struct platform_driver * const drivers[] = { 2791 &bcm63xx_enet_shared_driver, 2792 &bcm63xx_enet_driver, 2793 &bcm63xx_enetsw_driver, 2794 }; 2795 2796 /* entry point */ 2797 static int __init bcm_enet_init(void) 2798 { 2799 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 2800 } 2801 2802 static void __exit bcm_enet_exit(void) 2803 { 2804 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 2805 } 2806 2807 2808 module_init(bcm_enet_init); 2809 module_exit(bcm_enet_exit); 2810 2811 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); 2812 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 2813 MODULE_LICENSE("GPL"); 2814