1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 16 #include "bcm4908_enet.h" 17 #include "unimac.h" 18 19 #define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG 20 #define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG 21 #define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM 22 #define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM 23 24 #define ENET_TX_BDS_NUM 200 25 #define ENET_RX_BDS_NUM 200 26 #define ENET_RX_BDS_NUM_MAX 8192 27 28 #define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ 29 ENET_DMA_CH_CFG_INT_NO_DESC | \ 30 ENET_DMA_CH_CFG_INT_BUFF_DONE) 31 #define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ 32 33 #define ENET_MTU_MAX ETH_DATA_LEN /* Is it possible to support 2044? */ 34 #define BRCM_MAX_TAG_LEN 6 35 #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ 36 ETH_FCS_LEN + 4) /* 32 */ 37 38 struct bcm4908_enet_dma_ring_bd { 39 __le32 ctl; 40 __le32 addr; 41 } __packed; 42 43 struct bcm4908_enet_dma_ring_slot { 44 struct sk_buff *skb; 45 unsigned int len; 46 dma_addr_t dma_addr; 47 }; 48 49 struct bcm4908_enet_dma_ring { 50 int is_tx; 51 int read_idx; 52 int write_idx; 53 int length; 54 u16 cfg_block; 55 u16 st_ram_block; 56 57 union { 58 void *cpu_addr; 59 struct bcm4908_enet_dma_ring_bd *buf_desc; 60 }; 61 dma_addr_t dma_addr; 62 63 struct bcm4908_enet_dma_ring_slot *slots; 64 }; 65 66 struct bcm4908_enet { 67 struct device *dev; 68 struct net_device *netdev; 69 struct napi_struct napi; 70 void __iomem *base; 71 72 struct bcm4908_enet_dma_ring tx_ring; 73 struct bcm4908_enet_dma_ring rx_ring; 74 }; 75 76 /*** 77 * R/W ops 78 */ 79 80 static u32 enet_read(struct bcm4908_enet *enet, u16 offset) 81 { 82 return readl(enet->base + offset); 83 } 84 85 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) 86 { 87 writel(value, enet->base + offset); 88 } 89 90 static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) 91 { 92 u32 val; 93 94 WARN_ON(set & ~mask); 95 96 val = enet_read(enet, offset); 97 val = (val & ~mask) | (set & mask); 98 enet_write(enet, offset, val); 99 } 100 101 static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) 102 { 103 enet_maskset(enet, offset, set, set); 104 } 105 106 static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) 107 { 108 return enet_read(enet, ENET_UNIMAC + offset); 109 } 110 111 static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) 112 { 113 enet_write(enet, ENET_UNIMAC + offset, value); 114 } 115 116 static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) 117 { 118 enet_set(enet, ENET_UNIMAC + offset, set); 119 } 120 121 /*** 122 * Helpers 123 */ 124 125 static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet) 126 { 127 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); 128 } 129 130 static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet) 131 { 132 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); 133 } 134 135 static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet) 136 { 137 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); 138 } 139 140 static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) 141 { 142 enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); 143 } 144 145 /*** 146 * DMA 147 */ 148 149 static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet, 150 struct bcm4908_enet_dma_ring *ring) 151 { 152 int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 153 struct device *dev = enet->dev; 154 155 ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); 156 if (!ring->cpu_addr) 157 return -ENOMEM; 158 159 if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { 160 dev_err(dev, "Invalid DMA ring alignment\n"); 161 goto err_free_buf_descs; 162 } 163 164 ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); 165 if (!ring->slots) 166 goto err_free_buf_descs; 167 168 ring->read_idx = 0; 169 ring->write_idx = 0; 170 171 return 0; 172 173 err_free_buf_descs: 174 dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); 175 ring->cpu_addr = NULL; 176 return -ENOMEM; 177 } 178 179 static void bcm4908_enet_dma_free(struct bcm4908_enet *enet) 180 { 181 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 182 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 183 struct device *dev = enet->dev; 184 int size; 185 186 size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 187 if (rx_ring->cpu_addr) 188 dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); 189 kfree(rx_ring->slots); 190 191 size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 192 if (tx_ring->cpu_addr) 193 dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); 194 kfree(tx_ring->slots); 195 } 196 197 static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet) 198 { 199 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 200 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 201 struct device *dev = enet->dev; 202 int err; 203 204 tx_ring->length = ENET_TX_BDS_NUM; 205 tx_ring->is_tx = 1; 206 tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; 207 tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; 208 err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); 209 if (err) { 210 dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); 211 return err; 212 } 213 214 rx_ring->length = ENET_RX_BDS_NUM; 215 rx_ring->is_tx = 0; 216 rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; 217 rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; 218 err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); 219 if (err) { 220 dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); 221 bcm4908_enet_dma_free(enet); 222 return err; 223 } 224 225 return 0; 226 } 227 228 static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet) 229 { 230 struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; 231 int i; 232 233 /* Disable the DMA controller and channel */ 234 for (i = 0; i < ARRAY_SIZE(rings); i++) 235 enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); 236 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); 237 238 /* Reset channels state */ 239 for (i = 0; i < ARRAY_SIZE(rings); i++) { 240 struct bcm4908_enet_dma_ring *ring = rings[i]; 241 242 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); 243 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); 244 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); 245 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); 246 } 247 } 248 249 static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx) 250 { 251 struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; 252 struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; 253 struct device *dev = enet->dev; 254 u32 tmp; 255 int err; 256 257 slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD; 258 259 slot->skb = netdev_alloc_skb(enet->netdev, slot->len); 260 if (!slot->skb) 261 return -ENOMEM; 262 263 slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); 264 err = dma_mapping_error(dev, slot->dma_addr); 265 if (err) { 266 dev_err(dev, "Failed to map DMA buffer: %d\n", err); 267 kfree_skb(slot->skb); 268 slot->skb = NULL; 269 return err; 270 } 271 272 tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 273 tmp |= DMA_CTL_STATUS_OWN; 274 if (idx == enet->rx_ring.length - 1) 275 tmp |= DMA_CTL_STATUS_WRAP; 276 buf_desc->ctl = cpu_to_le32(tmp); 277 buf_desc->addr = cpu_to_le32(slot->dma_addr); 278 279 return 0; 280 } 281 282 static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet, 283 struct bcm4908_enet_dma_ring *ring) 284 { 285 int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ 286 int reset_subch = ring->is_tx ? 1 : 0; 287 288 /* Reset the DMA channel */ 289 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); 290 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); 291 292 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 293 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); 294 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); 295 296 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 297 (uint32_t)ring->dma_addr); 298 } 299 300 static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet) 301 { 302 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 303 struct bcm4908_enet_dma_ring_slot *slot; 304 struct device *dev = enet->dev; 305 int i; 306 307 for (i = rx_ring->length - 1; i >= 0; i--) { 308 slot = &rx_ring->slots[i]; 309 if (!slot->skb) 310 continue; 311 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); 312 kfree_skb(slot->skb); 313 slot->skb = NULL; 314 } 315 } 316 317 static int bcm4908_enet_dma_init(struct bcm4908_enet *enet) 318 { 319 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 320 struct device *dev = enet->dev; 321 int err; 322 int i; 323 324 for (i = 0; i < rx_ring->length; i++) { 325 err = bcm4908_enet_dma_alloc_rx_buf(enet, i); 326 if (err) { 327 dev_err(dev, "Failed to alloc RX buffer: %d\n", err); 328 bcm4908_enet_dma_uninit(enet); 329 return err; 330 } 331 } 332 333 bcm4908_enet_dma_ring_init(enet, &enet->tx_ring); 334 bcm4908_enet_dma_ring_init(enet, &enet->rx_ring); 335 336 return 0; 337 } 338 339 static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet, 340 struct bcm4908_enet_dma_ring *ring) 341 { 342 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 343 } 344 345 static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet, 346 struct bcm4908_enet_dma_ring *ring) 347 { 348 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 349 } 350 351 static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet, 352 struct bcm4908_enet_dma_ring *ring) 353 { 354 enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 355 } 356 357 static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet, 358 struct bcm4908_enet_dma_ring *ring) 359 { 360 unsigned long deadline; 361 u32 tmp; 362 363 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 364 365 deadline = jiffies + usecs_to_jiffies(2000); 366 do { 367 tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); 368 if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) 369 return; 370 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 371 usleep_range(10, 30); 372 } while (!time_after_eq(jiffies, deadline)); 373 374 dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); 375 } 376 377 /*** 378 * Ethernet driver 379 */ 380 381 static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet) 382 { 383 u32 cmd; 384 385 bcm4908_enet_set_mtu(enet, enet->netdev->mtu); 386 387 cmd = enet_umac_read(enet, UMAC_CMD); 388 enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); 389 enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); 390 391 enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); 392 enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); 393 394 enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); 395 enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); 396 397 cmd = enet_umac_read(enet, UMAC_CMD); 398 cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); 399 cmd &= ~CMD_TX_EN; 400 cmd &= ~CMD_RX_EN; 401 cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; 402 enet_umac_write(enet, UMAC_CMD, cmd); 403 404 enet_maskset(enet, ENET_GMAC_STATUS, 405 ENET_GMAC_STATUS_ETH_SPEED_MASK | 406 ENET_GMAC_STATUS_HD | 407 ENET_GMAC_STATUS_AUTO_CFG_EN | 408 ENET_GMAC_STATUS_LINK_UP, 409 ENET_GMAC_STATUS_ETH_SPEED_1000 | 410 ENET_GMAC_STATUS_AUTO_CFG_EN | 411 ENET_GMAC_STATUS_LINK_UP); 412 } 413 414 static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id) 415 { 416 struct bcm4908_enet *enet = dev_id; 417 418 bcm4908_enet_intrs_off(enet); 419 bcm4908_enet_intrs_ack(enet); 420 421 napi_schedule(&enet->napi); 422 423 return IRQ_HANDLED; 424 } 425 426 static int bcm4908_enet_open(struct net_device *netdev) 427 { 428 struct bcm4908_enet *enet = netdev_priv(netdev); 429 struct device *dev = enet->dev; 430 int err; 431 432 err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet); 433 if (err) { 434 dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); 435 return err; 436 } 437 438 bcm4908_enet_gmac_init(enet); 439 bcm4908_enet_dma_reset(enet); 440 bcm4908_enet_dma_init(enet); 441 442 enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); 443 444 enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); 445 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); 446 bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); 447 448 napi_enable(&enet->napi); 449 netif_carrier_on(netdev); 450 netif_start_queue(netdev); 451 452 bcm4908_enet_intrs_ack(enet); 453 bcm4908_enet_intrs_on(enet); 454 455 return 0; 456 } 457 458 static int bcm4908_enet_stop(struct net_device *netdev) 459 { 460 struct bcm4908_enet *enet = netdev_priv(netdev); 461 462 netif_stop_queue(netdev); 463 netif_carrier_off(netdev); 464 napi_disable(&enet->napi); 465 466 bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); 467 bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); 468 469 bcm4908_enet_dma_uninit(enet); 470 471 free_irq(enet->netdev->irq, enet); 472 473 return 0; 474 } 475 476 static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) 477 { 478 struct bcm4908_enet *enet = netdev_priv(netdev); 479 struct bcm4908_enet_dma_ring *ring = &enet->tx_ring; 480 struct bcm4908_enet_dma_ring_slot *slot; 481 struct device *dev = enet->dev; 482 struct bcm4908_enet_dma_ring_bd *buf_desc; 483 int free_buf_descs; 484 u32 tmp; 485 486 /* Free transmitted skbs */ 487 while (ring->read_idx != ring->write_idx) { 488 buf_desc = &ring->buf_desc[ring->read_idx]; 489 if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) 490 break; 491 slot = &ring->slots[ring->read_idx]; 492 493 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); 494 dev_kfree_skb(slot->skb); 495 if (++ring->read_idx == ring->length) 496 ring->read_idx = 0; 497 } 498 499 /* Don't use the last empty buf descriptor */ 500 if (ring->read_idx <= ring->write_idx) 501 free_buf_descs = ring->read_idx - ring->write_idx + ring->length; 502 else 503 free_buf_descs = ring->read_idx - ring->write_idx; 504 if (free_buf_descs < 2) 505 return NETDEV_TX_BUSY; 506 507 /* Hardware removes OWN bit after sending data */ 508 buf_desc = &ring->buf_desc[ring->write_idx]; 509 if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { 510 netif_stop_queue(netdev); 511 return NETDEV_TX_BUSY; 512 } 513 514 slot = &ring->slots[ring->write_idx]; 515 slot->skb = skb; 516 slot->len = skb->len; 517 slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); 518 if (unlikely(dma_mapping_error(dev, slot->dma_addr))) 519 return NETDEV_TX_BUSY; 520 521 tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 522 tmp |= DMA_CTL_STATUS_OWN; 523 tmp |= DMA_CTL_STATUS_SOP; 524 tmp |= DMA_CTL_STATUS_EOP; 525 tmp |= DMA_CTL_STATUS_APPEND_CRC; 526 if (ring->write_idx + 1 == ring->length - 1) 527 tmp |= DMA_CTL_STATUS_WRAP; 528 529 buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); 530 buf_desc->ctl = cpu_to_le32(tmp); 531 532 bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring); 533 534 if (++ring->write_idx == ring->length - 1) 535 ring->write_idx = 0; 536 enet->netdev->stats.tx_bytes += skb->len; 537 enet->netdev->stats.tx_packets++; 538 539 return NETDEV_TX_OK; 540 } 541 542 static int bcm4908_enet_poll(struct napi_struct *napi, int weight) 543 { 544 struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi); 545 struct device *dev = enet->dev; 546 int handled = 0; 547 548 while (handled < weight) { 549 struct bcm4908_enet_dma_ring_bd *buf_desc; 550 struct bcm4908_enet_dma_ring_slot slot; 551 u32 ctl; 552 int len; 553 int err; 554 555 buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; 556 ctl = le32_to_cpu(buf_desc->ctl); 557 if (ctl & DMA_CTL_STATUS_OWN) 558 break; 559 560 slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; 561 562 /* Provide new buffer before unpinning the old one */ 563 err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); 564 if (err) 565 break; 566 567 if (++enet->rx_ring.read_idx == enet->rx_ring.length) 568 enet->rx_ring.read_idx = 0; 569 570 len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 571 572 if (len < ETH_ZLEN || 573 (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { 574 kfree_skb(slot.skb); 575 enet->netdev->stats.rx_dropped++; 576 break; 577 } 578 579 dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); 580 581 skb_put(slot.skb, len - ETH_FCS_LEN); 582 slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); 583 netif_receive_skb(slot.skb); 584 585 enet->netdev->stats.rx_packets++; 586 enet->netdev->stats.rx_bytes += len; 587 588 handled++; 589 } 590 591 if (handled < weight) { 592 napi_complete_done(napi, handled); 593 bcm4908_enet_intrs_on(enet); 594 } 595 596 /* Hardware could disable ring if it run out of descriptors */ 597 bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); 598 599 return handled; 600 } 601 602 static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu) 603 { 604 struct bcm4908_enet *enet = netdev_priv(netdev); 605 606 bcm4908_enet_set_mtu(enet, new_mtu); 607 608 return 0; 609 } 610 611 static const struct net_device_ops bcm4908_enet_netdev_ops = { 612 .ndo_open = bcm4908_enet_open, 613 .ndo_stop = bcm4908_enet_stop, 614 .ndo_start_xmit = bcm4908_enet_start_xmit, 615 .ndo_set_mac_address = eth_mac_addr, 616 .ndo_change_mtu = bcm4908_enet_change_mtu, 617 }; 618 619 static int bcm4908_enet_probe(struct platform_device *pdev) 620 { 621 struct device *dev = &pdev->dev; 622 struct net_device *netdev; 623 struct bcm4908_enet *enet; 624 int err; 625 626 netdev = devm_alloc_etherdev(dev, sizeof(*enet)); 627 if (!netdev) 628 return -ENOMEM; 629 630 enet = netdev_priv(netdev); 631 enet->dev = dev; 632 enet->netdev = netdev; 633 634 enet->base = devm_platform_ioremap_resource(pdev, 0); 635 if (IS_ERR(enet->base)) { 636 dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); 637 return PTR_ERR(enet->base); 638 } 639 640 netdev->irq = platform_get_irq_byname(pdev, "rx"); 641 if (netdev->irq < 0) 642 return netdev->irq; 643 644 dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 645 646 err = bcm4908_enet_dma_alloc(enet); 647 if (err) 648 return err; 649 650 SET_NETDEV_DEV(netdev, &pdev->dev); 651 eth_hw_addr_random(netdev); 652 netdev->netdev_ops = &bcm4908_enet_netdev_ops; 653 netdev->min_mtu = ETH_ZLEN; 654 netdev->mtu = ETH_DATA_LEN; 655 netdev->max_mtu = ENET_MTU_MAX; 656 netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64); 657 658 err = register_netdev(netdev); 659 if (err) { 660 bcm4908_enet_dma_free(enet); 661 return err; 662 } 663 664 platform_set_drvdata(pdev, enet); 665 666 return 0; 667 } 668 669 static int bcm4908_enet_remove(struct platform_device *pdev) 670 { 671 struct bcm4908_enet *enet = platform_get_drvdata(pdev); 672 673 unregister_netdev(enet->netdev); 674 netif_napi_del(&enet->napi); 675 bcm4908_enet_dma_free(enet); 676 677 return 0; 678 } 679 680 static const struct of_device_id bcm4908_enet_of_match[] = { 681 { .compatible = "brcm,bcm4908-enet"}, 682 {}, 683 }; 684 685 static struct platform_driver bcm4908_enet_driver = { 686 .driver = { 687 .name = "bcm4908_enet", 688 .of_match_table = bcm4908_enet_of_match, 689 }, 690 .probe = bcm4908_enet_probe, 691 .remove = bcm4908_enet_remove, 692 }; 693 module_platform_driver(bcm4908_enet_driver); 694 695 MODULE_LICENSE("GPL v2"); 696 MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match); 697