1 /* 2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23 #include <linux/atomic.h> 24 #include <linux/crc32.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/hardirq.h> 29 #include <linux/if_vlan.h> 30 #include <linux/in.h> 31 #include <linux/interrupt.h> 32 #include <linux/ip.h> 33 #include <linux/irqflags.h> 34 #include <linux/irqreturn.h> 35 #include <linux/mii.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/pm.h> 41 #include <linux/skbuff.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/string.h> 45 #include <linux/tcp.h> 46 #include <linux/timer.h> 47 #include <linux/types.h> 48 #include <linux/workqueue.h> 49 50 #include "atl2.h" 51 52 #define ATL2_DRV_VERSION "2.2.3" 53 54 static const char atl2_driver_name[] = "atl2"; 55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; 56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; 57 static const char atl2_driver_version[] = ATL2_DRV_VERSION; 58 59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 61 MODULE_LICENSE("GPL"); 62 MODULE_VERSION(ATL2_DRV_VERSION); 63 64 /* 65 * atl2_pci_tbl - PCI Device ID Table 66 */ 67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = { 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 69 /* required last entry */ 70 {0,} 71 }; 72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 73 74 static void atl2_set_ethtool_ops(struct net_device *netdev); 75 76 static void atl2_check_options(struct atl2_adapter *adapter); 77 78 /* 79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 80 * @adapter: board private structure to initialize 81 * 82 * atl2_sw_init initializes the Adapter private data structure. 83 * Fields are initialized based on PCI device information and 84 * OS network device settings (MTU size). 85 */ 86 static int __devinit atl2_sw_init(struct atl2_adapter *adapter) 87 { 88 struct atl2_hw *hw = &adapter->hw; 89 struct pci_dev *pdev = adapter->pdev; 90 91 /* PCI config space info */ 92 hw->vendor_id = pdev->vendor; 93 hw->device_id = pdev->device; 94 hw->subsystem_vendor_id = pdev->subsystem_vendor; 95 hw->subsystem_id = pdev->subsystem_device; 96 hw->revision_id = pdev->revision; 97 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 99 100 adapter->wol = 0; 101 adapter->ict = 50000; /* ~100ms */ 102 adapter->link_speed = SPEED_0; /* hardware init */ 103 adapter->link_duplex = FULL_DUPLEX; 104 105 hw->phy_configured = false; 106 hw->preamble_len = 7; 107 hw->ipgt = 0x60; 108 hw->min_ifg = 0x50; 109 hw->ipgr1 = 0x40; 110 hw->ipgr2 = 0x60; 111 hw->retry_buf = 2; 112 hw->max_retry = 0xf; 113 hw->lcol = 0x37; 114 hw->jam_ipg = 7; 115 hw->fc_rxd_hi = 0; 116 hw->fc_rxd_lo = 0; 117 hw->max_frame_size = adapter->netdev->mtu; 118 119 spin_lock_init(&adapter->stats_lock); 120 121 set_bit(__ATL2_DOWN, &adapter->flags); 122 123 return 0; 124 } 125 126 /* 127 * atl2_set_multi - Multicast and Promiscuous mode set 128 * @netdev: network interface device structure 129 * 130 * The set_multi entry point is called whenever the multicast address 131 * list or the network interface flags are updated. This routine is 132 * responsible for configuring the hardware for proper multicast, 133 * promiscuous mode, and all-multi behavior. 134 */ 135 static void atl2_set_multi(struct net_device *netdev) 136 { 137 struct atl2_adapter *adapter = netdev_priv(netdev); 138 struct atl2_hw *hw = &adapter->hw; 139 struct netdev_hw_addr *ha; 140 u32 rctl; 141 u32 hash_value; 142 143 /* Check for Promiscuous and All Multicast modes */ 144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 145 146 if (netdev->flags & IFF_PROMISC) { 147 rctl |= MAC_CTRL_PROMIS_EN; 148 } else if (netdev->flags & IFF_ALLMULTI) { 149 rctl |= MAC_CTRL_MC_ALL_EN; 150 rctl &= ~MAC_CTRL_PROMIS_EN; 151 } else 152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 153 154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 155 156 /* clear the old settings from the multicast hash table */ 157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 159 160 /* comoute mc addresses' hash value ,and put it into hash table */ 161 netdev_for_each_mc_addr(ha, netdev) { 162 hash_value = atl2_hash_mc_addr(hw, ha->addr); 163 atl2_hash_set(hw, hash_value); 164 } 165 } 166 167 static void init_ring_ptrs(struct atl2_adapter *adapter) 168 { 169 /* Read / Write Ptr Initialize: */ 170 adapter->txd_write_ptr = 0; 171 atomic_set(&adapter->txd_read_ptr, 0); 172 173 adapter->rxd_read_ptr = 0; 174 adapter->rxd_write_ptr = 0; 175 176 atomic_set(&adapter->txs_write_ptr, 0); 177 adapter->txs_next_clear = 0; 178 } 179 180 /* 181 * atl2_configure - Configure Transmit&Receive Unit after Reset 182 * @adapter: board private structure 183 * 184 * Configure the Tx /Rx unit of the MAC after a reset. 185 */ 186 static int atl2_configure(struct atl2_adapter *adapter) 187 { 188 struct atl2_hw *hw = &adapter->hw; 189 u32 value; 190 191 /* clear interrupt status */ 192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 193 194 /* set MAC Address */ 195 value = (((u32)hw->mac_addr[2]) << 24) | 196 (((u32)hw->mac_addr[3]) << 16) | 197 (((u32)hw->mac_addr[4]) << 8) | 198 (((u32)hw->mac_addr[5])); 199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 200 value = (((u32)hw->mac_addr[0]) << 8) | 201 (((u32)hw->mac_addr[1])); 202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 203 204 /* HI base address */ 205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 207 208 /* LO base address */ 209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 215 216 /* element count */ 217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 220 221 /* config Internal SRAM */ 222 /* 223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 225 */ 226 227 /* config IPG/IFG */ 228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 229 MAC_IPG_IFG_IPGT_SHIFT) | 230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 231 MAC_IPG_IFG_MIFG_SHIFT) | 232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 233 MAC_IPG_IFG_IPGR1_SHIFT)| 234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 235 MAC_IPG_IFG_IPGR2_SHIFT); 236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 237 238 /* config Half-Duplex Control */ 239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 247 248 /* set Interrupt Moderator Timer */ 249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 251 252 /* set Interrupt Clear Timer */ 253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 254 255 /* set MTU */ 256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); 258 259 /* 1590 */ 260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 261 262 /* flow control */ 263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 265 266 /* Init mailbox */ 267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 269 270 /* enable DMA read/write */ 271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 273 274 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 275 if ((value & ISR_PHY_LINKDOWN) != 0) 276 value = 1; /* config failed */ 277 else 278 value = 0; 279 280 /* clear all interrupt status */ 281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 283 return value; 284 } 285 286 /* 287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 288 * @adapter: board private structure 289 * 290 * Return 0 on success, negative on failure 291 */ 292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 293 { 294 struct pci_dev *pdev = adapter->pdev; 295 int size; 296 u8 offset = 0; 297 298 /* real ring DMA buffer */ 299 adapter->ring_size = size = 300 adapter->txd_ring_size * 1 + 7 + /* dword align */ 301 adapter->txs_ring_size * 4 + 7 + /* dword align */ 302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 303 304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 305 &adapter->ring_dma); 306 if (!adapter->ring_vir_addr) 307 return -ENOMEM; 308 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 309 310 /* Init TXD Ring */ 311 adapter->txd_dma = adapter->ring_dma ; 312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 313 adapter->txd_dma += offset; 314 adapter->txd_ring = adapter->ring_vir_addr + offset; 315 316 /* Init TXS Ring */ 317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 319 adapter->txs_dma += offset; 320 adapter->txs_ring = (struct tx_pkt_status *) 321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 322 323 /* Init RXD Ring */ 324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 325 offset = (adapter->rxd_dma & 127) ? 326 (128 - (adapter->rxd_dma & 127)) : 0; 327 if (offset > 7) 328 offset -= 8; 329 else 330 offset += (128 - 8); 331 332 adapter->rxd_dma += offset; 333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 334 (adapter->txs_ring_size * 4 + offset)); 335 336 /* 337 * Read / Write Ptr Initialize: 338 * init_ring_ptrs(adapter); 339 */ 340 return 0; 341 } 342 343 /* 344 * atl2_irq_enable - Enable default interrupt generation settings 345 * @adapter: board private structure 346 */ 347 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 348 { 349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 350 ATL2_WRITE_FLUSH(&adapter->hw); 351 } 352 353 /* 354 * atl2_irq_disable - Mask off interrupt generation on the NIC 355 * @adapter: board private structure 356 */ 357 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 358 { 359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 360 ATL2_WRITE_FLUSH(&adapter->hw); 361 synchronize_irq(adapter->pdev->irq); 362 } 363 364 static void __atl2_vlan_mode(u32 features, u32 *ctrl) 365 { 366 if (features & NETIF_F_HW_VLAN_RX) { 367 /* enable VLAN tag insert/strip */ 368 *ctrl |= MAC_CTRL_RMV_VLAN; 369 } else { 370 /* disable VLAN tag insert/strip */ 371 *ctrl &= ~MAC_CTRL_RMV_VLAN; 372 } 373 } 374 375 static void atl2_vlan_mode(struct net_device *netdev, u32 features) 376 { 377 struct atl2_adapter *adapter = netdev_priv(netdev); 378 u32 ctrl; 379 380 atl2_irq_disable(adapter); 381 382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 383 __atl2_vlan_mode(features, &ctrl); 384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 385 386 atl2_irq_enable(adapter); 387 } 388 389 static void atl2_restore_vlan(struct atl2_adapter *adapter) 390 { 391 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 392 } 393 394 static u32 atl2_fix_features(struct net_device *netdev, u32 features) 395 { 396 /* 397 * Since there is no support for separate rx/tx vlan accel 398 * enable/disable make sure tx flag is always in same state as rx. 399 */ 400 if (features & NETIF_F_HW_VLAN_RX) 401 features |= NETIF_F_HW_VLAN_TX; 402 else 403 features &= ~NETIF_F_HW_VLAN_TX; 404 405 return features; 406 } 407 408 static int atl2_set_features(struct net_device *netdev, u32 features) 409 { 410 u32 changed = netdev->features ^ features; 411 412 if (changed & NETIF_F_HW_VLAN_RX) 413 atl2_vlan_mode(netdev, features); 414 415 return 0; 416 } 417 418 static void atl2_intr_rx(struct atl2_adapter *adapter) 419 { 420 struct net_device *netdev = adapter->netdev; 421 struct rx_desc *rxd; 422 struct sk_buff *skb; 423 424 do { 425 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 426 if (!rxd->status.update) 427 break; /* end of tx */ 428 429 /* clear this flag at once */ 430 rxd->status.update = 0; 431 432 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 433 int rx_size = (int)(rxd->status.pkt_size - 4); 434 /* alloc new buffer */ 435 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 436 if (NULL == skb) { 437 printk(KERN_WARNING 438 "%s: Mem squeeze, deferring packet.\n", 439 netdev->name); 440 /* 441 * Check that some rx space is free. If not, 442 * free one and mark stats->rx_dropped++. 443 */ 444 netdev->stats.rx_dropped++; 445 break; 446 } 447 memcpy(skb->data, rxd->packet, rx_size); 448 skb_put(skb, rx_size); 449 skb->protocol = eth_type_trans(skb, netdev); 450 if (rxd->status.vlan) { 451 u16 vlan_tag = (rxd->status.vtag>>4) | 452 ((rxd->status.vtag&7) << 13) | 453 ((rxd->status.vtag&8) << 9); 454 455 __vlan_hwaccel_put_tag(skb, vlan_tag); 456 } 457 netif_rx(skb); 458 netdev->stats.rx_bytes += rx_size; 459 netdev->stats.rx_packets++; 460 } else { 461 netdev->stats.rx_errors++; 462 463 if (rxd->status.ok && rxd->status.pkt_size <= 60) 464 netdev->stats.rx_length_errors++; 465 if (rxd->status.mcast) 466 netdev->stats.multicast++; 467 if (rxd->status.crc) 468 netdev->stats.rx_crc_errors++; 469 if (rxd->status.align) 470 netdev->stats.rx_frame_errors++; 471 } 472 473 /* advance write ptr */ 474 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 475 adapter->rxd_write_ptr = 0; 476 } while (1); 477 478 /* update mailbox? */ 479 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 480 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 481 } 482 483 static void atl2_intr_tx(struct atl2_adapter *adapter) 484 { 485 struct net_device *netdev = adapter->netdev; 486 u32 txd_read_ptr; 487 u32 txs_write_ptr; 488 struct tx_pkt_status *txs; 489 struct tx_pkt_header *txph; 490 int free_hole = 0; 491 492 do { 493 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 494 txs = adapter->txs_ring + txs_write_ptr; 495 if (!txs->update) 496 break; /* tx stop here */ 497 498 free_hole = 1; 499 txs->update = 0; 500 501 if (++txs_write_ptr == adapter->txs_ring_size) 502 txs_write_ptr = 0; 503 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 504 505 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 506 txph = (struct tx_pkt_header *) 507 (((u8 *)adapter->txd_ring) + txd_read_ptr); 508 509 if (txph->pkt_size != txs->pkt_size) { 510 struct tx_pkt_status *old_txs = txs; 511 printk(KERN_WARNING 512 "%s: txs packet size not consistent with txd" 513 " txd_:0x%08x, txs_:0x%08x!\n", 514 adapter->netdev->name, 515 *(u32 *)txph, *(u32 *)txs); 516 printk(KERN_WARNING 517 "txd read ptr: 0x%x\n", 518 txd_read_ptr); 519 txs = adapter->txs_ring + txs_write_ptr; 520 printk(KERN_WARNING 521 "txs-behind:0x%08x\n", 522 *(u32 *)txs); 523 if (txs_write_ptr < 2) { 524 txs = adapter->txs_ring + 525 (adapter->txs_ring_size + 526 txs_write_ptr - 2); 527 } else { 528 txs = adapter->txs_ring + (txs_write_ptr - 2); 529 } 530 printk(KERN_WARNING 531 "txs-before:0x%08x\n", 532 *(u32 *)txs); 533 txs = old_txs; 534 } 535 536 /* 4for TPH */ 537 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 538 if (txd_read_ptr >= adapter->txd_ring_size) 539 txd_read_ptr -= adapter->txd_ring_size; 540 541 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 542 543 /* tx statistics: */ 544 if (txs->ok) { 545 netdev->stats.tx_bytes += txs->pkt_size; 546 netdev->stats.tx_packets++; 547 } 548 else 549 netdev->stats.tx_errors++; 550 551 if (txs->defer) 552 netdev->stats.collisions++; 553 if (txs->abort_col) 554 netdev->stats.tx_aborted_errors++; 555 if (txs->late_col) 556 netdev->stats.tx_window_errors++; 557 if (txs->underun) 558 netdev->stats.tx_fifo_errors++; 559 } while (1); 560 561 if (free_hole) { 562 if (netif_queue_stopped(adapter->netdev) && 563 netif_carrier_ok(adapter->netdev)) 564 netif_wake_queue(adapter->netdev); 565 } 566 } 567 568 static void atl2_check_for_link(struct atl2_adapter *adapter) 569 { 570 struct net_device *netdev = adapter->netdev; 571 u16 phy_data = 0; 572 573 spin_lock(&adapter->stats_lock); 574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 575 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 576 spin_unlock(&adapter->stats_lock); 577 578 /* notify upper layer link down ASAP */ 579 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 580 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 581 printk(KERN_INFO "%s: %s NIC Link is Down\n", 582 atl2_driver_name, netdev->name); 583 adapter->link_speed = SPEED_0; 584 netif_carrier_off(netdev); 585 netif_stop_queue(netdev); 586 } 587 } 588 schedule_work(&adapter->link_chg_task); 589 } 590 591 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 592 { 593 u16 phy_data; 594 spin_lock(&adapter->stats_lock); 595 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 596 spin_unlock(&adapter->stats_lock); 597 } 598 599 /* 600 * atl2_intr - Interrupt Handler 601 * @irq: interrupt number 602 * @data: pointer to a network interface device structure 603 * @pt_regs: CPU registers structure 604 */ 605 static irqreturn_t atl2_intr(int irq, void *data) 606 { 607 struct atl2_adapter *adapter = netdev_priv(data); 608 struct atl2_hw *hw = &adapter->hw; 609 u32 status; 610 611 status = ATL2_READ_REG(hw, REG_ISR); 612 if (0 == status) 613 return IRQ_NONE; 614 615 /* link event */ 616 if (status & ISR_PHY) 617 atl2_clear_phy_int(adapter); 618 619 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 620 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 621 622 /* check if PCIE PHY Link down */ 623 if (status & ISR_PHY_LINKDOWN) { 624 if (netif_running(adapter->netdev)) { /* reset MAC */ 625 ATL2_WRITE_REG(hw, REG_ISR, 0); 626 ATL2_WRITE_REG(hw, REG_IMR, 0); 627 ATL2_WRITE_FLUSH(hw); 628 schedule_work(&adapter->reset_task); 629 return IRQ_HANDLED; 630 } 631 } 632 633 /* check if DMA read/write error? */ 634 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 635 ATL2_WRITE_REG(hw, REG_ISR, 0); 636 ATL2_WRITE_REG(hw, REG_IMR, 0); 637 ATL2_WRITE_FLUSH(hw); 638 schedule_work(&adapter->reset_task); 639 return IRQ_HANDLED; 640 } 641 642 /* link event */ 643 if (status & (ISR_PHY | ISR_MANUAL)) { 644 adapter->netdev->stats.tx_carrier_errors++; 645 atl2_check_for_link(adapter); 646 } 647 648 /* transmit event */ 649 if (status & ISR_TX_EVENT) 650 atl2_intr_tx(adapter); 651 652 /* rx exception */ 653 if (status & ISR_RX_EVENT) 654 atl2_intr_rx(adapter); 655 656 /* re-enable Interrupt */ 657 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 658 return IRQ_HANDLED; 659 } 660 661 static int atl2_request_irq(struct atl2_adapter *adapter) 662 { 663 struct net_device *netdev = adapter->netdev; 664 int flags, err = 0; 665 666 flags = IRQF_SHARED; 667 adapter->have_msi = true; 668 err = pci_enable_msi(adapter->pdev); 669 if (err) 670 adapter->have_msi = false; 671 672 if (adapter->have_msi) 673 flags &= ~IRQF_SHARED; 674 675 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 676 netdev); 677 } 678 679 /* 680 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 681 * @adapter: board private structure 682 * 683 * Free all transmit software resources 684 */ 685 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 686 { 687 struct pci_dev *pdev = adapter->pdev; 688 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 689 adapter->ring_dma); 690 } 691 692 /* 693 * atl2_open - Called when a network interface is made active 694 * @netdev: network interface device structure 695 * 696 * Returns 0 on success, negative value on failure 697 * 698 * The open entry point is called when a network interface is made 699 * active by the system (IFF_UP). At this point all resources needed 700 * for transmit and receive operations are allocated, the interrupt 701 * handler is registered with the OS, the watchdog timer is started, 702 * and the stack is notified that the interface is ready. 703 */ 704 static int atl2_open(struct net_device *netdev) 705 { 706 struct atl2_adapter *adapter = netdev_priv(netdev); 707 int err; 708 u32 val; 709 710 /* disallow open during test */ 711 if (test_bit(__ATL2_TESTING, &adapter->flags)) 712 return -EBUSY; 713 714 /* allocate transmit descriptors */ 715 err = atl2_setup_ring_resources(adapter); 716 if (err) 717 return err; 718 719 err = atl2_init_hw(&adapter->hw); 720 if (err) { 721 err = -EIO; 722 goto err_init_hw; 723 } 724 725 /* hardware has been reset, we need to reload some things */ 726 atl2_set_multi(netdev); 727 init_ring_ptrs(adapter); 728 729 atl2_restore_vlan(adapter); 730 731 if (atl2_configure(adapter)) { 732 err = -EIO; 733 goto err_config; 734 } 735 736 err = atl2_request_irq(adapter); 737 if (err) 738 goto err_req_irq; 739 740 clear_bit(__ATL2_DOWN, &adapter->flags); 741 742 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 743 744 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 745 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 746 val | MASTER_CTRL_MANUAL_INT); 747 748 atl2_irq_enable(adapter); 749 750 return 0; 751 752 err_init_hw: 753 err_req_irq: 754 err_config: 755 atl2_free_ring_resources(adapter); 756 atl2_reset_hw(&adapter->hw); 757 758 return err; 759 } 760 761 static void atl2_down(struct atl2_adapter *adapter) 762 { 763 struct net_device *netdev = adapter->netdev; 764 765 /* signal that we're down so the interrupt handler does not 766 * reschedule our watchdog timer */ 767 set_bit(__ATL2_DOWN, &adapter->flags); 768 769 netif_tx_disable(netdev); 770 771 /* reset MAC to disable all RX/TX */ 772 atl2_reset_hw(&adapter->hw); 773 msleep(1); 774 775 atl2_irq_disable(adapter); 776 777 del_timer_sync(&adapter->watchdog_timer); 778 del_timer_sync(&adapter->phy_config_timer); 779 clear_bit(0, &adapter->cfg_phy); 780 781 netif_carrier_off(netdev); 782 adapter->link_speed = SPEED_0; 783 adapter->link_duplex = -1; 784 } 785 786 static void atl2_free_irq(struct atl2_adapter *adapter) 787 { 788 struct net_device *netdev = adapter->netdev; 789 790 free_irq(adapter->pdev->irq, netdev); 791 792 #ifdef CONFIG_PCI_MSI 793 if (adapter->have_msi) 794 pci_disable_msi(adapter->pdev); 795 #endif 796 } 797 798 /* 799 * atl2_close - Disables a network interface 800 * @netdev: network interface device structure 801 * 802 * Returns 0, this is not allowed to fail 803 * 804 * The close entry point is called when an interface is de-activated 805 * by the OS. The hardware is still under the drivers control, but 806 * needs to be disabled. A global MAC reset is issued to stop the 807 * hardware, and all transmit and receive resources are freed. 808 */ 809 static int atl2_close(struct net_device *netdev) 810 { 811 struct atl2_adapter *adapter = netdev_priv(netdev); 812 813 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 814 815 atl2_down(adapter); 816 atl2_free_irq(adapter); 817 atl2_free_ring_resources(adapter); 818 819 return 0; 820 } 821 822 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 823 { 824 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 825 826 return (adapter->txs_next_clear >= txs_write_ptr) ? 827 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 828 txs_write_ptr - 1) : 829 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 830 } 831 832 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 833 { 834 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 835 836 return (adapter->txd_write_ptr >= txd_read_ptr) ? 837 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 838 txd_read_ptr - 1) : 839 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 840 } 841 842 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 843 struct net_device *netdev) 844 { 845 struct atl2_adapter *adapter = netdev_priv(netdev); 846 struct tx_pkt_header *txph; 847 u32 offset, copy_len; 848 int txs_unused; 849 int txbuf_unused; 850 851 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 852 dev_kfree_skb_any(skb); 853 return NETDEV_TX_OK; 854 } 855 856 if (unlikely(skb->len <= 0)) { 857 dev_kfree_skb_any(skb); 858 return NETDEV_TX_OK; 859 } 860 861 txs_unused = TxsFreeUnit(adapter); 862 txbuf_unused = TxdFreeBytes(adapter); 863 864 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 865 txs_unused < 1) { 866 /* not enough resources */ 867 netif_stop_queue(netdev); 868 return NETDEV_TX_BUSY; 869 } 870 871 offset = adapter->txd_write_ptr; 872 873 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 874 875 *(u32 *)txph = 0; 876 txph->pkt_size = skb->len; 877 878 offset += 4; 879 if (offset >= adapter->txd_ring_size) 880 offset -= adapter->txd_ring_size; 881 copy_len = adapter->txd_ring_size - offset; 882 if (copy_len >= skb->len) { 883 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 884 offset += ((u32)(skb->len + 3) & ~3); 885 } else { 886 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 887 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 888 skb->len-copy_len); 889 offset = ((u32)(skb->len-copy_len + 3) & ~3); 890 } 891 #ifdef NETIF_F_HW_VLAN_TX 892 if (vlan_tx_tag_present(skb)) { 893 u16 vlan_tag = vlan_tx_tag_get(skb); 894 vlan_tag = (vlan_tag << 4) | 895 (vlan_tag >> 13) | 896 ((vlan_tag >> 9) & 0x8); 897 txph->ins_vlan = 1; 898 txph->vlan = vlan_tag; 899 } 900 #endif 901 if (offset >= adapter->txd_ring_size) 902 offset -= adapter->txd_ring_size; 903 adapter->txd_write_ptr = offset; 904 905 /* clear txs before send */ 906 adapter->txs_ring[adapter->txs_next_clear].update = 0; 907 if (++adapter->txs_next_clear == adapter->txs_ring_size) 908 adapter->txs_next_clear = 0; 909 910 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 911 (adapter->txd_write_ptr >> 2)); 912 913 mmiowb(); 914 dev_kfree_skb_any(skb); 915 return NETDEV_TX_OK; 916 } 917 918 /* 919 * atl2_change_mtu - Change the Maximum Transfer Unit 920 * @netdev: network interface device structure 921 * @new_mtu: new value for maximum frame size 922 * 923 * Returns 0 on success, negative on failure 924 */ 925 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 926 { 927 struct atl2_adapter *adapter = netdev_priv(netdev); 928 struct atl2_hw *hw = &adapter->hw; 929 930 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) 931 return -EINVAL; 932 933 /* set MTU */ 934 if (hw->max_frame_size != new_mtu) { 935 netdev->mtu = new_mtu; 936 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + 937 VLAN_SIZE + ETHERNET_FCS_SIZE); 938 } 939 940 return 0; 941 } 942 943 /* 944 * atl2_set_mac - Change the Ethernet Address of the NIC 945 * @netdev: network interface device structure 946 * @p: pointer to an address structure 947 * 948 * Returns 0 on success, negative on failure 949 */ 950 static int atl2_set_mac(struct net_device *netdev, void *p) 951 { 952 struct atl2_adapter *adapter = netdev_priv(netdev); 953 struct sockaddr *addr = p; 954 955 if (!is_valid_ether_addr(addr->sa_data)) 956 return -EADDRNOTAVAIL; 957 958 if (netif_running(netdev)) 959 return -EBUSY; 960 961 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 962 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 963 964 atl2_set_mac_addr(&adapter->hw); 965 966 return 0; 967 } 968 969 /* 970 * atl2_mii_ioctl - 971 * @netdev: 972 * @ifreq: 973 * @cmd: 974 */ 975 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 976 { 977 struct atl2_adapter *adapter = netdev_priv(netdev); 978 struct mii_ioctl_data *data = if_mii(ifr); 979 unsigned long flags; 980 981 switch (cmd) { 982 case SIOCGMIIPHY: 983 data->phy_id = 0; 984 break; 985 case SIOCGMIIREG: 986 spin_lock_irqsave(&adapter->stats_lock, flags); 987 if (atl2_read_phy_reg(&adapter->hw, 988 data->reg_num & 0x1F, &data->val_out)) { 989 spin_unlock_irqrestore(&adapter->stats_lock, flags); 990 return -EIO; 991 } 992 spin_unlock_irqrestore(&adapter->stats_lock, flags); 993 break; 994 case SIOCSMIIREG: 995 if (data->reg_num & ~(0x1F)) 996 return -EFAULT; 997 spin_lock_irqsave(&adapter->stats_lock, flags); 998 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 999 data->val_in)) { 1000 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1001 return -EIO; 1002 } 1003 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1004 break; 1005 default: 1006 return -EOPNOTSUPP; 1007 } 1008 return 0; 1009 } 1010 1011 /* 1012 * atl2_ioctl - 1013 * @netdev: 1014 * @ifreq: 1015 * @cmd: 1016 */ 1017 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1018 { 1019 switch (cmd) { 1020 case SIOCGMIIPHY: 1021 case SIOCGMIIREG: 1022 case SIOCSMIIREG: 1023 return atl2_mii_ioctl(netdev, ifr, cmd); 1024 #ifdef ETHTOOL_OPS_COMPAT 1025 case SIOCETHTOOL: 1026 return ethtool_ioctl(ifr); 1027 #endif 1028 default: 1029 return -EOPNOTSUPP; 1030 } 1031 } 1032 1033 /* 1034 * atl2_tx_timeout - Respond to a Tx Hang 1035 * @netdev: network interface device structure 1036 */ 1037 static void atl2_tx_timeout(struct net_device *netdev) 1038 { 1039 struct atl2_adapter *adapter = netdev_priv(netdev); 1040 1041 /* Do the reset outside of interrupt context */ 1042 schedule_work(&adapter->reset_task); 1043 } 1044 1045 /* 1046 * atl2_watchdog - Timer Call-back 1047 * @data: pointer to netdev cast into an unsigned long 1048 */ 1049 static void atl2_watchdog(unsigned long data) 1050 { 1051 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1052 1053 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1054 u32 drop_rxd, drop_rxs; 1055 unsigned long flags; 1056 1057 spin_lock_irqsave(&adapter->stats_lock, flags); 1058 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1059 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1060 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1061 1062 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1063 1064 /* Reset the timer */ 1065 mod_timer(&adapter->watchdog_timer, 1066 round_jiffies(jiffies + 4 * HZ)); 1067 } 1068 } 1069 1070 /* 1071 * atl2_phy_config - Timer Call-back 1072 * @data: pointer to netdev cast into an unsigned long 1073 */ 1074 static void atl2_phy_config(unsigned long data) 1075 { 1076 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1077 struct atl2_hw *hw = &adapter->hw; 1078 unsigned long flags; 1079 1080 spin_lock_irqsave(&adapter->stats_lock, flags); 1081 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1082 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1083 MII_CR_RESTART_AUTO_NEG); 1084 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1085 clear_bit(0, &adapter->cfg_phy); 1086 } 1087 1088 static int atl2_up(struct atl2_adapter *adapter) 1089 { 1090 struct net_device *netdev = adapter->netdev; 1091 int err = 0; 1092 u32 val; 1093 1094 /* hardware has been reset, we need to reload some things */ 1095 1096 err = atl2_init_hw(&adapter->hw); 1097 if (err) { 1098 err = -EIO; 1099 return err; 1100 } 1101 1102 atl2_set_multi(netdev); 1103 init_ring_ptrs(adapter); 1104 1105 atl2_restore_vlan(adapter); 1106 1107 if (atl2_configure(adapter)) { 1108 err = -EIO; 1109 goto err_up; 1110 } 1111 1112 clear_bit(__ATL2_DOWN, &adapter->flags); 1113 1114 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1115 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1116 MASTER_CTRL_MANUAL_INT); 1117 1118 atl2_irq_enable(adapter); 1119 1120 err_up: 1121 return err; 1122 } 1123 1124 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1125 { 1126 WARN_ON(in_interrupt()); 1127 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1128 msleep(1); 1129 atl2_down(adapter); 1130 atl2_up(adapter); 1131 clear_bit(__ATL2_RESETTING, &adapter->flags); 1132 } 1133 1134 static void atl2_reset_task(struct work_struct *work) 1135 { 1136 struct atl2_adapter *adapter; 1137 adapter = container_of(work, struct atl2_adapter, reset_task); 1138 1139 atl2_reinit_locked(adapter); 1140 } 1141 1142 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1143 { 1144 u32 value; 1145 struct atl2_hw *hw = &adapter->hw; 1146 struct net_device *netdev = adapter->netdev; 1147 1148 /* Config MAC CTRL Register */ 1149 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1150 1151 /* duplex */ 1152 if (FULL_DUPLEX == adapter->link_duplex) 1153 value |= MAC_CTRL_DUPLX; 1154 1155 /* flow control */ 1156 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1157 1158 /* PAD & CRC */ 1159 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1160 1161 /* preamble length */ 1162 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1163 MAC_CTRL_PRMLEN_SHIFT); 1164 1165 /* vlan */ 1166 __atl2_vlan_mode(netdev->features, &value); 1167 1168 /* filter mode */ 1169 value |= MAC_CTRL_BC_EN; 1170 if (netdev->flags & IFF_PROMISC) 1171 value |= MAC_CTRL_PROMIS_EN; 1172 else if (netdev->flags & IFF_ALLMULTI) 1173 value |= MAC_CTRL_MC_ALL_EN; 1174 1175 /* half retry buffer */ 1176 value |= (((u32)(adapter->hw.retry_buf & 1177 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1178 1179 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1180 } 1181 1182 static int atl2_check_link(struct atl2_adapter *adapter) 1183 { 1184 struct atl2_hw *hw = &adapter->hw; 1185 struct net_device *netdev = adapter->netdev; 1186 int ret_val; 1187 u16 speed, duplex, phy_data; 1188 int reconfig = 0; 1189 1190 /* MII_BMSR must read twise */ 1191 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1192 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1193 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1194 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1195 u32 value; 1196 /* disable rx */ 1197 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1198 value &= ~MAC_CTRL_RX_EN; 1199 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1200 adapter->link_speed = SPEED_0; 1201 netif_carrier_off(netdev); 1202 netif_stop_queue(netdev); 1203 } 1204 return 0; 1205 } 1206 1207 /* Link Up */ 1208 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1209 if (ret_val) 1210 return ret_val; 1211 switch (hw->MediaType) { 1212 case MEDIA_TYPE_100M_FULL: 1213 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1214 reconfig = 1; 1215 break; 1216 case MEDIA_TYPE_100M_HALF: 1217 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1218 reconfig = 1; 1219 break; 1220 case MEDIA_TYPE_10M_FULL: 1221 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1222 reconfig = 1; 1223 break; 1224 case MEDIA_TYPE_10M_HALF: 1225 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1226 reconfig = 1; 1227 break; 1228 } 1229 /* link result is our setting */ 1230 if (reconfig == 0) { 1231 if (adapter->link_speed != speed || 1232 adapter->link_duplex != duplex) { 1233 adapter->link_speed = speed; 1234 adapter->link_duplex = duplex; 1235 atl2_setup_mac_ctrl(adapter); 1236 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1237 atl2_driver_name, netdev->name, 1238 adapter->link_speed, 1239 adapter->link_duplex == FULL_DUPLEX ? 1240 "Full Duplex" : "Half Duplex"); 1241 } 1242 1243 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1244 netif_carrier_on(netdev); 1245 netif_wake_queue(netdev); 1246 } 1247 return 0; 1248 } 1249 1250 /* change original link status */ 1251 if (netif_carrier_ok(netdev)) { 1252 u32 value; 1253 /* disable rx */ 1254 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1255 value &= ~MAC_CTRL_RX_EN; 1256 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1257 1258 adapter->link_speed = SPEED_0; 1259 netif_carrier_off(netdev); 1260 netif_stop_queue(netdev); 1261 } 1262 1263 /* auto-neg, insert timer to re-config phy 1264 * (if interval smaller than 5 seconds, something strange) */ 1265 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1266 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1267 mod_timer(&adapter->phy_config_timer, 1268 round_jiffies(jiffies + 5 * HZ)); 1269 } 1270 1271 return 0; 1272 } 1273 1274 /* 1275 * atl2_link_chg_task - deal with link change event Out of interrupt context 1276 * @netdev: network interface device structure 1277 */ 1278 static void atl2_link_chg_task(struct work_struct *work) 1279 { 1280 struct atl2_adapter *adapter; 1281 unsigned long flags; 1282 1283 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1284 1285 spin_lock_irqsave(&adapter->stats_lock, flags); 1286 atl2_check_link(adapter); 1287 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1288 } 1289 1290 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1291 { 1292 u16 cmd; 1293 1294 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1295 1296 if (cmd & PCI_COMMAND_INTX_DISABLE) 1297 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1298 if (cmd & PCI_COMMAND_IO) 1299 cmd &= ~PCI_COMMAND_IO; 1300 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1301 cmd |= PCI_COMMAND_MEMORY; 1302 if (0 == (cmd & PCI_COMMAND_MASTER)) 1303 cmd |= PCI_COMMAND_MASTER; 1304 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1305 1306 /* 1307 * some motherboards BIOS(PXE/EFI) driver may set PME 1308 * while they transfer control to OS (Windows/Linux) 1309 * so we should clear this bit before NIC work normally 1310 */ 1311 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1312 } 1313 1314 #ifdef CONFIG_NET_POLL_CONTROLLER 1315 static void atl2_poll_controller(struct net_device *netdev) 1316 { 1317 disable_irq(netdev->irq); 1318 atl2_intr(netdev->irq, netdev); 1319 enable_irq(netdev->irq); 1320 } 1321 #endif 1322 1323 1324 static const struct net_device_ops atl2_netdev_ops = { 1325 .ndo_open = atl2_open, 1326 .ndo_stop = atl2_close, 1327 .ndo_start_xmit = atl2_xmit_frame, 1328 .ndo_set_rx_mode = atl2_set_multi, 1329 .ndo_validate_addr = eth_validate_addr, 1330 .ndo_set_mac_address = atl2_set_mac, 1331 .ndo_change_mtu = atl2_change_mtu, 1332 .ndo_fix_features = atl2_fix_features, 1333 .ndo_set_features = atl2_set_features, 1334 .ndo_do_ioctl = atl2_ioctl, 1335 .ndo_tx_timeout = atl2_tx_timeout, 1336 #ifdef CONFIG_NET_POLL_CONTROLLER 1337 .ndo_poll_controller = atl2_poll_controller, 1338 #endif 1339 }; 1340 1341 /* 1342 * atl2_probe - Device Initialization Routine 1343 * @pdev: PCI device information struct 1344 * @ent: entry in atl2_pci_tbl 1345 * 1346 * Returns 0 on success, negative on failure 1347 * 1348 * atl2_probe initializes an adapter identified by a pci_dev structure. 1349 * The OS initialization, configuring of the adapter private structure, 1350 * and a hardware reset occur. 1351 */ 1352 static int __devinit atl2_probe(struct pci_dev *pdev, 1353 const struct pci_device_id *ent) 1354 { 1355 struct net_device *netdev; 1356 struct atl2_adapter *adapter; 1357 static int cards_found; 1358 unsigned long mmio_start; 1359 int mmio_len; 1360 int err; 1361 1362 cards_found = 0; 1363 1364 err = pci_enable_device(pdev); 1365 if (err) 1366 return err; 1367 1368 /* 1369 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1370 * until the kernel has the proper infrastructure to support 64-bit DMA 1371 * on these devices. 1372 */ 1373 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1374 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1375 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1376 goto err_dma; 1377 } 1378 1379 /* Mark all PCI regions associated with PCI device 1380 * pdev as being reserved by owner atl2_driver_name */ 1381 err = pci_request_regions(pdev, atl2_driver_name); 1382 if (err) 1383 goto err_pci_reg; 1384 1385 /* Enables bus-mastering on the device and calls 1386 * pcibios_set_master to do the needed arch specific settings */ 1387 pci_set_master(pdev); 1388 1389 err = -ENOMEM; 1390 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1391 if (!netdev) 1392 goto err_alloc_etherdev; 1393 1394 SET_NETDEV_DEV(netdev, &pdev->dev); 1395 1396 pci_set_drvdata(pdev, netdev); 1397 adapter = netdev_priv(netdev); 1398 adapter->netdev = netdev; 1399 adapter->pdev = pdev; 1400 adapter->hw.back = adapter; 1401 1402 mmio_start = pci_resource_start(pdev, 0x0); 1403 mmio_len = pci_resource_len(pdev, 0x0); 1404 1405 adapter->hw.mem_rang = (u32)mmio_len; 1406 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1407 if (!adapter->hw.hw_addr) { 1408 err = -EIO; 1409 goto err_ioremap; 1410 } 1411 1412 atl2_setup_pcicmd(pdev); 1413 1414 netdev->netdev_ops = &atl2_netdev_ops; 1415 atl2_set_ethtool_ops(netdev); 1416 netdev->watchdog_timeo = 5 * HZ; 1417 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1418 1419 netdev->mem_start = mmio_start; 1420 netdev->mem_end = mmio_start + mmio_len; 1421 adapter->bd_number = cards_found; 1422 adapter->pci_using_64 = false; 1423 1424 /* setup the private structure */ 1425 err = atl2_sw_init(adapter); 1426 if (err) 1427 goto err_sw_init; 1428 1429 err = -EIO; 1430 1431 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX; 1432 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 1433 1434 /* Init PHY as early as possible due to power saving issue */ 1435 atl2_phy_init(&adapter->hw); 1436 1437 /* reset the controller to 1438 * put the device in a known good starting state */ 1439 1440 if (atl2_reset_hw(&adapter->hw)) { 1441 err = -EIO; 1442 goto err_reset; 1443 } 1444 1445 /* copy the MAC address out of the EEPROM */ 1446 atl2_read_mac_addr(&adapter->hw); 1447 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1448 /* FIXME: do we still need this? */ 1449 #ifdef ETHTOOL_GPERMADDR 1450 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); 1451 1452 if (!is_valid_ether_addr(netdev->perm_addr)) { 1453 #else 1454 if (!is_valid_ether_addr(netdev->dev_addr)) { 1455 #endif 1456 err = -EIO; 1457 goto err_eeprom; 1458 } 1459 1460 atl2_check_options(adapter); 1461 1462 init_timer(&adapter->watchdog_timer); 1463 adapter->watchdog_timer.function = atl2_watchdog; 1464 adapter->watchdog_timer.data = (unsigned long) adapter; 1465 1466 init_timer(&adapter->phy_config_timer); 1467 adapter->phy_config_timer.function = atl2_phy_config; 1468 adapter->phy_config_timer.data = (unsigned long) adapter; 1469 1470 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1471 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1472 1473 strcpy(netdev->name, "eth%d"); /* ?? */ 1474 err = register_netdev(netdev); 1475 if (err) 1476 goto err_register; 1477 1478 /* assume we have no link for now */ 1479 netif_carrier_off(netdev); 1480 netif_stop_queue(netdev); 1481 1482 cards_found++; 1483 1484 return 0; 1485 1486 err_reset: 1487 err_register: 1488 err_sw_init: 1489 err_eeprom: 1490 iounmap(adapter->hw.hw_addr); 1491 err_ioremap: 1492 free_netdev(netdev); 1493 err_alloc_etherdev: 1494 pci_release_regions(pdev); 1495 err_pci_reg: 1496 err_dma: 1497 pci_disable_device(pdev); 1498 return err; 1499 } 1500 1501 /* 1502 * atl2_remove - Device Removal Routine 1503 * @pdev: PCI device information struct 1504 * 1505 * atl2_remove is called by the PCI subsystem to alert the driver 1506 * that it should release a PCI device. The could be caused by a 1507 * Hot-Plug event, or because the driver is going to be removed from 1508 * memory. 1509 */ 1510 /* FIXME: write the original MAC address back in case it was changed from a 1511 * BIOS-set value, as in atl1 -- CHS */ 1512 static void __devexit atl2_remove(struct pci_dev *pdev) 1513 { 1514 struct net_device *netdev = pci_get_drvdata(pdev); 1515 struct atl2_adapter *adapter = netdev_priv(netdev); 1516 1517 /* flush_scheduled work may reschedule our watchdog task, so 1518 * explicitly disable watchdog tasks from being rescheduled */ 1519 set_bit(__ATL2_DOWN, &adapter->flags); 1520 1521 del_timer_sync(&adapter->watchdog_timer); 1522 del_timer_sync(&adapter->phy_config_timer); 1523 cancel_work_sync(&adapter->reset_task); 1524 cancel_work_sync(&adapter->link_chg_task); 1525 1526 unregister_netdev(netdev); 1527 1528 atl2_force_ps(&adapter->hw); 1529 1530 iounmap(adapter->hw.hw_addr); 1531 pci_release_regions(pdev); 1532 1533 free_netdev(netdev); 1534 1535 pci_disable_device(pdev); 1536 } 1537 1538 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1539 { 1540 struct net_device *netdev = pci_get_drvdata(pdev); 1541 struct atl2_adapter *adapter = netdev_priv(netdev); 1542 struct atl2_hw *hw = &adapter->hw; 1543 u16 speed, duplex; 1544 u32 ctrl = 0; 1545 u32 wufc = adapter->wol; 1546 1547 #ifdef CONFIG_PM 1548 int retval = 0; 1549 #endif 1550 1551 netif_device_detach(netdev); 1552 1553 if (netif_running(netdev)) { 1554 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1555 atl2_down(adapter); 1556 } 1557 1558 #ifdef CONFIG_PM 1559 retval = pci_save_state(pdev); 1560 if (retval) 1561 return retval; 1562 #endif 1563 1564 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1565 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1566 if (ctrl & BMSR_LSTATUS) 1567 wufc &= ~ATLX_WUFC_LNKC; 1568 1569 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1570 u32 ret_val; 1571 /* get current link speed & duplex */ 1572 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1573 if (ret_val) { 1574 printk(KERN_DEBUG 1575 "%s: get speed&duplex error while suspend\n", 1576 atl2_driver_name); 1577 goto wol_dis; 1578 } 1579 1580 ctrl = 0; 1581 1582 /* turn on magic packet wol */ 1583 if (wufc & ATLX_WUFC_MAG) 1584 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1585 1586 /* ignore Link Chg event when Link is up */ 1587 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1588 1589 /* Config MAC CTRL Register */ 1590 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1591 if (FULL_DUPLEX == adapter->link_duplex) 1592 ctrl |= MAC_CTRL_DUPLX; 1593 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1594 ctrl |= (((u32)adapter->hw.preamble_len & 1595 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1596 ctrl |= (((u32)(adapter->hw.retry_buf & 1597 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1598 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1599 if (wufc & ATLX_WUFC_MAG) { 1600 /* magic packet maybe Broadcast&multicast&Unicast */ 1601 ctrl |= MAC_CTRL_BC_EN; 1602 } 1603 1604 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1605 1606 /* pcie patch */ 1607 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1608 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1609 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1611 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1612 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1613 1614 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1615 goto suspend_exit; 1616 } 1617 1618 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1619 /* link is down, so only LINK CHG WOL event enable */ 1620 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1621 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1622 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1623 1624 /* pcie patch */ 1625 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1626 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1627 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1629 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1630 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1631 1632 hw->phy_configured = false; /* re-init PHY when resume */ 1633 1634 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1635 1636 goto suspend_exit; 1637 } 1638 1639 wol_dis: 1640 /* WOL disabled */ 1641 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1642 1643 /* pcie patch */ 1644 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1645 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1646 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1648 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1649 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1650 1651 atl2_force_ps(hw); 1652 hw->phy_configured = false; /* re-init PHY when resume */ 1653 1654 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1655 1656 suspend_exit: 1657 if (netif_running(netdev)) 1658 atl2_free_irq(adapter); 1659 1660 pci_disable_device(pdev); 1661 1662 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1663 1664 return 0; 1665 } 1666 1667 #ifdef CONFIG_PM 1668 static int atl2_resume(struct pci_dev *pdev) 1669 { 1670 struct net_device *netdev = pci_get_drvdata(pdev); 1671 struct atl2_adapter *adapter = netdev_priv(netdev); 1672 u32 err; 1673 1674 pci_set_power_state(pdev, PCI_D0); 1675 pci_restore_state(pdev); 1676 1677 err = pci_enable_device(pdev); 1678 if (err) { 1679 printk(KERN_ERR 1680 "atl2: Cannot enable PCI device from suspend\n"); 1681 return err; 1682 } 1683 1684 pci_set_master(pdev); 1685 1686 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1687 1688 pci_enable_wake(pdev, PCI_D3hot, 0); 1689 pci_enable_wake(pdev, PCI_D3cold, 0); 1690 1691 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1692 1693 if (netif_running(netdev)) { 1694 err = atl2_request_irq(adapter); 1695 if (err) 1696 return err; 1697 } 1698 1699 atl2_reset_hw(&adapter->hw); 1700 1701 if (netif_running(netdev)) 1702 atl2_up(adapter); 1703 1704 netif_device_attach(netdev); 1705 1706 return 0; 1707 } 1708 #endif 1709 1710 static void atl2_shutdown(struct pci_dev *pdev) 1711 { 1712 atl2_suspend(pdev, PMSG_SUSPEND); 1713 } 1714 1715 static struct pci_driver atl2_driver = { 1716 .name = atl2_driver_name, 1717 .id_table = atl2_pci_tbl, 1718 .probe = atl2_probe, 1719 .remove = __devexit_p(atl2_remove), 1720 /* Power Management Hooks */ 1721 .suspend = atl2_suspend, 1722 #ifdef CONFIG_PM 1723 .resume = atl2_resume, 1724 #endif 1725 .shutdown = atl2_shutdown, 1726 }; 1727 1728 /* 1729 * atl2_init_module - Driver Registration Routine 1730 * 1731 * atl2_init_module is the first routine called when the driver is 1732 * loaded. All it does is register with the PCI subsystem. 1733 */ 1734 static int __init atl2_init_module(void) 1735 { 1736 printk(KERN_INFO "%s - version %s\n", atl2_driver_string, 1737 atl2_driver_version); 1738 printk(KERN_INFO "%s\n", atl2_copyright); 1739 return pci_register_driver(&atl2_driver); 1740 } 1741 module_init(atl2_init_module); 1742 1743 /* 1744 * atl2_exit_module - Driver Exit Cleanup Routine 1745 * 1746 * atl2_exit_module is called just before the driver is removed 1747 * from memory. 1748 */ 1749 static void __exit atl2_exit_module(void) 1750 { 1751 pci_unregister_driver(&atl2_driver); 1752 } 1753 module_exit(atl2_exit_module); 1754 1755 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1756 { 1757 struct atl2_adapter *adapter = hw->back; 1758 pci_read_config_word(adapter->pdev, reg, value); 1759 } 1760 1761 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1762 { 1763 struct atl2_adapter *adapter = hw->back; 1764 pci_write_config_word(adapter->pdev, reg, *value); 1765 } 1766 1767 static int atl2_get_settings(struct net_device *netdev, 1768 struct ethtool_cmd *ecmd) 1769 { 1770 struct atl2_adapter *adapter = netdev_priv(netdev); 1771 struct atl2_hw *hw = &adapter->hw; 1772 1773 ecmd->supported = (SUPPORTED_10baseT_Half | 1774 SUPPORTED_10baseT_Full | 1775 SUPPORTED_100baseT_Half | 1776 SUPPORTED_100baseT_Full | 1777 SUPPORTED_Autoneg | 1778 SUPPORTED_TP); 1779 ecmd->advertising = ADVERTISED_TP; 1780 1781 ecmd->advertising |= ADVERTISED_Autoneg; 1782 ecmd->advertising |= hw->autoneg_advertised; 1783 1784 ecmd->port = PORT_TP; 1785 ecmd->phy_address = 0; 1786 ecmd->transceiver = XCVR_INTERNAL; 1787 1788 if (adapter->link_speed != SPEED_0) { 1789 ethtool_cmd_speed_set(ecmd, adapter->link_speed); 1790 if (adapter->link_duplex == FULL_DUPLEX) 1791 ecmd->duplex = DUPLEX_FULL; 1792 else 1793 ecmd->duplex = DUPLEX_HALF; 1794 } else { 1795 ethtool_cmd_speed_set(ecmd, -1); 1796 ecmd->duplex = -1; 1797 } 1798 1799 ecmd->autoneg = AUTONEG_ENABLE; 1800 return 0; 1801 } 1802 1803 static int atl2_set_settings(struct net_device *netdev, 1804 struct ethtool_cmd *ecmd) 1805 { 1806 struct atl2_adapter *adapter = netdev_priv(netdev); 1807 struct atl2_hw *hw = &adapter->hw; 1808 1809 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1810 msleep(1); 1811 1812 if (ecmd->autoneg == AUTONEG_ENABLE) { 1813 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1814 ADVERTISE_10_FULL | \ 1815 ADVERTISE_100_HALF| \ 1816 ADVERTISE_100_FULL) 1817 1818 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1819 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1820 hw->autoneg_advertised = MY_ADV_MASK; 1821 } else if ((ecmd->advertising & MY_ADV_MASK) == 1822 ADVERTISE_100_FULL) { 1823 hw->MediaType = MEDIA_TYPE_100M_FULL; 1824 hw->autoneg_advertised = ADVERTISE_100_FULL; 1825 } else if ((ecmd->advertising & MY_ADV_MASK) == 1826 ADVERTISE_100_HALF) { 1827 hw->MediaType = MEDIA_TYPE_100M_HALF; 1828 hw->autoneg_advertised = ADVERTISE_100_HALF; 1829 } else if ((ecmd->advertising & MY_ADV_MASK) == 1830 ADVERTISE_10_FULL) { 1831 hw->MediaType = MEDIA_TYPE_10M_FULL; 1832 hw->autoneg_advertised = ADVERTISE_10_FULL; 1833 } else if ((ecmd->advertising & MY_ADV_MASK) == 1834 ADVERTISE_10_HALF) { 1835 hw->MediaType = MEDIA_TYPE_10M_HALF; 1836 hw->autoneg_advertised = ADVERTISE_10_HALF; 1837 } else { 1838 clear_bit(__ATL2_RESETTING, &adapter->flags); 1839 return -EINVAL; 1840 } 1841 ecmd->advertising = hw->autoneg_advertised | 1842 ADVERTISED_TP | ADVERTISED_Autoneg; 1843 } else { 1844 clear_bit(__ATL2_RESETTING, &adapter->flags); 1845 return -EINVAL; 1846 } 1847 1848 /* reset the link */ 1849 if (netif_running(adapter->netdev)) { 1850 atl2_down(adapter); 1851 atl2_up(adapter); 1852 } else 1853 atl2_reset_hw(&adapter->hw); 1854 1855 clear_bit(__ATL2_RESETTING, &adapter->flags); 1856 return 0; 1857 } 1858 1859 static u32 atl2_get_msglevel(struct net_device *netdev) 1860 { 1861 return 0; 1862 } 1863 1864 /* 1865 * It's sane for this to be empty, but we might want to take advantage of this. 1866 */ 1867 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1868 { 1869 } 1870 1871 static int atl2_get_regs_len(struct net_device *netdev) 1872 { 1873 #define ATL2_REGS_LEN 42 1874 return sizeof(u32) * ATL2_REGS_LEN; 1875 } 1876 1877 static void atl2_get_regs(struct net_device *netdev, 1878 struct ethtool_regs *regs, void *p) 1879 { 1880 struct atl2_adapter *adapter = netdev_priv(netdev); 1881 struct atl2_hw *hw = &adapter->hw; 1882 u32 *regs_buff = p; 1883 u16 phy_data; 1884 1885 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1886 1887 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1888 1889 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1890 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1891 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1892 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1893 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1894 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1895 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1896 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1897 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1898 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1899 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1900 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1901 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1902 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1903 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1904 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1905 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1906 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1907 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1908 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1909 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1910 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1911 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1912 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1913 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1914 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1915 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1916 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1917 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1918 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1919 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1920 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1921 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1922 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1923 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1924 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1925 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1926 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1927 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1928 1929 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1930 regs_buff[40] = (u32)phy_data; 1931 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1932 regs_buff[41] = (u32)phy_data; 1933 } 1934 1935 static int atl2_get_eeprom_len(struct net_device *netdev) 1936 { 1937 struct atl2_adapter *adapter = netdev_priv(netdev); 1938 1939 if (!atl2_check_eeprom_exist(&adapter->hw)) 1940 return 512; 1941 else 1942 return 0; 1943 } 1944 1945 static int atl2_get_eeprom(struct net_device *netdev, 1946 struct ethtool_eeprom *eeprom, u8 *bytes) 1947 { 1948 struct atl2_adapter *adapter = netdev_priv(netdev); 1949 struct atl2_hw *hw = &adapter->hw; 1950 u32 *eeprom_buff; 1951 int first_dword, last_dword; 1952 int ret_val = 0; 1953 int i; 1954 1955 if (eeprom->len == 0) 1956 return -EINVAL; 1957 1958 if (atl2_check_eeprom_exist(hw)) 1959 return -EINVAL; 1960 1961 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1962 1963 first_dword = eeprom->offset >> 2; 1964 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1965 1966 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), 1967 GFP_KERNEL); 1968 if (!eeprom_buff) 1969 return -ENOMEM; 1970 1971 for (i = first_dword; i < last_dword; i++) { 1972 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1973 ret_val = -EIO; 1974 goto free; 1975 } 1976 } 1977 1978 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1979 eeprom->len); 1980 free: 1981 kfree(eeprom_buff); 1982 1983 return ret_val; 1984 } 1985 1986 static int atl2_set_eeprom(struct net_device *netdev, 1987 struct ethtool_eeprom *eeprom, u8 *bytes) 1988 { 1989 struct atl2_adapter *adapter = netdev_priv(netdev); 1990 struct atl2_hw *hw = &adapter->hw; 1991 u32 *eeprom_buff; 1992 u32 *ptr; 1993 int max_len, first_dword, last_dword, ret_val = 0; 1994 int i; 1995 1996 if (eeprom->len == 0) 1997 return -EOPNOTSUPP; 1998 1999 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 2000 return -EFAULT; 2001 2002 max_len = 512; 2003 2004 first_dword = eeprom->offset >> 2; 2005 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 2006 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 2007 if (!eeprom_buff) 2008 return -ENOMEM; 2009 2010 ptr = eeprom_buff; 2011 2012 if (eeprom->offset & 3) { 2013 /* need read/modify/write of first changed EEPROM word */ 2014 /* only the second byte of the word is being modified */ 2015 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 2016 ret_val = -EIO; 2017 goto out; 2018 } 2019 ptr++; 2020 } 2021 if (((eeprom->offset + eeprom->len) & 3)) { 2022 /* 2023 * need read/modify/write of last changed EEPROM word 2024 * only the first byte of the word is being modified 2025 */ 2026 if (!atl2_read_eeprom(hw, last_dword * 4, 2027 &(eeprom_buff[last_dword - first_dword]))) { 2028 ret_val = -EIO; 2029 goto out; 2030 } 2031 } 2032 2033 /* Device's eeprom is always little-endian, word addressable */ 2034 memcpy(ptr, bytes, eeprom->len); 2035 2036 for (i = 0; i < last_dword - first_dword + 1; i++) { 2037 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 2038 ret_val = -EIO; 2039 goto out; 2040 } 2041 } 2042 out: 2043 kfree(eeprom_buff); 2044 return ret_val; 2045 } 2046 2047 static void atl2_get_drvinfo(struct net_device *netdev, 2048 struct ethtool_drvinfo *drvinfo) 2049 { 2050 struct atl2_adapter *adapter = netdev_priv(netdev); 2051 2052 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2053 strlcpy(drvinfo->version, atl2_driver_version, 2054 sizeof(drvinfo->version)); 2055 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2056 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2057 sizeof(drvinfo->bus_info)); 2058 drvinfo->n_stats = 0; 2059 drvinfo->testinfo_len = 0; 2060 drvinfo->regdump_len = atl2_get_regs_len(netdev); 2061 drvinfo->eedump_len = atl2_get_eeprom_len(netdev); 2062 } 2063 2064 static void atl2_get_wol(struct net_device *netdev, 2065 struct ethtool_wolinfo *wol) 2066 { 2067 struct atl2_adapter *adapter = netdev_priv(netdev); 2068 2069 wol->supported = WAKE_MAGIC; 2070 wol->wolopts = 0; 2071 2072 if (adapter->wol & ATLX_WUFC_EX) 2073 wol->wolopts |= WAKE_UCAST; 2074 if (adapter->wol & ATLX_WUFC_MC) 2075 wol->wolopts |= WAKE_MCAST; 2076 if (adapter->wol & ATLX_WUFC_BC) 2077 wol->wolopts |= WAKE_BCAST; 2078 if (adapter->wol & ATLX_WUFC_MAG) 2079 wol->wolopts |= WAKE_MAGIC; 2080 if (adapter->wol & ATLX_WUFC_LNKC) 2081 wol->wolopts |= WAKE_PHY; 2082 } 2083 2084 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2085 { 2086 struct atl2_adapter *adapter = netdev_priv(netdev); 2087 2088 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2089 return -EOPNOTSUPP; 2090 2091 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2092 return -EOPNOTSUPP; 2093 2094 /* these settings will always override what we currently have */ 2095 adapter->wol = 0; 2096 2097 if (wol->wolopts & WAKE_MAGIC) 2098 adapter->wol |= ATLX_WUFC_MAG; 2099 if (wol->wolopts & WAKE_PHY) 2100 adapter->wol |= ATLX_WUFC_LNKC; 2101 2102 return 0; 2103 } 2104 2105 static int atl2_nway_reset(struct net_device *netdev) 2106 { 2107 struct atl2_adapter *adapter = netdev_priv(netdev); 2108 if (netif_running(netdev)) 2109 atl2_reinit_locked(adapter); 2110 return 0; 2111 } 2112 2113 static const struct ethtool_ops atl2_ethtool_ops = { 2114 .get_settings = atl2_get_settings, 2115 .set_settings = atl2_set_settings, 2116 .get_drvinfo = atl2_get_drvinfo, 2117 .get_regs_len = atl2_get_regs_len, 2118 .get_regs = atl2_get_regs, 2119 .get_wol = atl2_get_wol, 2120 .set_wol = atl2_set_wol, 2121 .get_msglevel = atl2_get_msglevel, 2122 .set_msglevel = atl2_set_msglevel, 2123 .nway_reset = atl2_nway_reset, 2124 .get_link = ethtool_op_get_link, 2125 .get_eeprom_len = atl2_get_eeprom_len, 2126 .get_eeprom = atl2_get_eeprom, 2127 .set_eeprom = atl2_set_eeprom, 2128 }; 2129 2130 static void atl2_set_ethtool_ops(struct net_device *netdev) 2131 { 2132 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); 2133 } 2134 2135 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2136 (((a) & 0xff00ff00) >> 8)) 2137 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2138 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2139 2140 /* 2141 * Reset the transmit and receive units; mask and clear all interrupts. 2142 * 2143 * hw - Struct containing variables accessed by shared code 2144 * return : 0 or idle status (if error) 2145 */ 2146 static s32 atl2_reset_hw(struct atl2_hw *hw) 2147 { 2148 u32 icr; 2149 u16 pci_cfg_cmd_word; 2150 int i; 2151 2152 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2153 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2154 if ((pci_cfg_cmd_word & 2155 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2156 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2157 pci_cfg_cmd_word |= 2158 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2159 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2160 } 2161 2162 /* Clear Interrupt mask to stop board from generating 2163 * interrupts & Clear any pending interrupt events 2164 */ 2165 /* FIXME */ 2166 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2167 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2168 2169 /* Issue Soft Reset to the MAC. This will reset the chip's 2170 * transmit, receive, DMA. It will not effect 2171 * the current PCI configuration. The global reset bit is self- 2172 * clearing, and should clear within a microsecond. 2173 */ 2174 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2175 wmb(); 2176 msleep(1); /* delay about 1ms */ 2177 2178 /* Wait at least 10ms for All module to be Idle */ 2179 for (i = 0; i < 10; i++) { 2180 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2181 if (!icr) 2182 break; 2183 msleep(1); /* delay 1 ms */ 2184 cpu_relax(); 2185 } 2186 2187 if (icr) 2188 return icr; 2189 2190 return 0; 2191 } 2192 2193 #define CUSTOM_SPI_CS_SETUP 2 2194 #define CUSTOM_SPI_CLK_HI 2 2195 #define CUSTOM_SPI_CLK_LO 2 2196 #define CUSTOM_SPI_CS_HOLD 2 2197 #define CUSTOM_SPI_CS_HI 3 2198 2199 static struct atl2_spi_flash_dev flash_table[] = 2200 { 2201 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2202 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2203 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2204 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2205 }; 2206 2207 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2208 { 2209 int i; 2210 u32 value; 2211 2212 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2213 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2214 2215 value = SPI_FLASH_CTRL_WAIT_READY | 2216 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2217 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2218 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2219 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2220 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2221 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2222 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2223 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2224 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2225 SPI_FLASH_CTRL_CS_HI_SHIFT | 2226 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2227 2228 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2229 2230 value |= SPI_FLASH_CTRL_START; 2231 2232 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2233 2234 for (i = 0; i < 10; i++) { 2235 msleep(1); 2236 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2237 if (!(value & SPI_FLASH_CTRL_START)) 2238 break; 2239 } 2240 2241 if (value & SPI_FLASH_CTRL_START) 2242 return false; 2243 2244 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2245 2246 return true; 2247 } 2248 2249 /* 2250 * get_permanent_address 2251 * return 0 if get valid mac address, 2252 */ 2253 static int get_permanent_address(struct atl2_hw *hw) 2254 { 2255 u32 Addr[2]; 2256 u32 i, Control; 2257 u16 Register; 2258 u8 EthAddr[NODE_ADDRESS_SIZE]; 2259 bool KeyValid; 2260 2261 if (is_valid_ether_addr(hw->perm_mac_addr)) 2262 return 0; 2263 2264 Addr[0] = 0; 2265 Addr[1] = 0; 2266 2267 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2268 Register = 0; 2269 KeyValid = false; 2270 2271 /* Read out all EEPROM content */ 2272 i = 0; 2273 while (1) { 2274 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2275 if (KeyValid) { 2276 if (Register == REG_MAC_STA_ADDR) 2277 Addr[0] = Control; 2278 else if (Register == 2279 (REG_MAC_STA_ADDR + 4)) 2280 Addr[1] = Control; 2281 KeyValid = false; 2282 } else if ((Control & 0xff) == 0x5A) { 2283 KeyValid = true; 2284 Register = (u16) (Control >> 16); 2285 } else { 2286 /* assume data end while encount an invalid KEYWORD */ 2287 break; 2288 } 2289 } else { 2290 break; /* read error */ 2291 } 2292 i += 4; 2293 } 2294 2295 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2296 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2297 2298 if (is_valid_ether_addr(EthAddr)) { 2299 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2300 return 0; 2301 } 2302 return 1; 2303 } 2304 2305 /* see if SPI flash exists? */ 2306 Addr[0] = 0; 2307 Addr[1] = 0; 2308 Register = 0; 2309 KeyValid = false; 2310 i = 0; 2311 while (1) { 2312 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2313 if (KeyValid) { 2314 if (Register == REG_MAC_STA_ADDR) 2315 Addr[0] = Control; 2316 else if (Register == (REG_MAC_STA_ADDR + 4)) 2317 Addr[1] = Control; 2318 KeyValid = false; 2319 } else if ((Control & 0xff) == 0x5A) { 2320 KeyValid = true; 2321 Register = (u16) (Control >> 16); 2322 } else { 2323 break; /* data end */ 2324 } 2325 } else { 2326 break; /* read error */ 2327 } 2328 i += 4; 2329 } 2330 2331 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2332 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2333 if (is_valid_ether_addr(EthAddr)) { 2334 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2335 return 0; 2336 } 2337 /* maybe MAC-address is from BIOS */ 2338 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2339 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2340 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2341 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2342 2343 if (is_valid_ether_addr(EthAddr)) { 2344 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2345 return 0; 2346 } 2347 2348 return 1; 2349 } 2350 2351 /* 2352 * Reads the adapter's MAC address from the EEPROM 2353 * 2354 * hw - Struct containing variables accessed by shared code 2355 */ 2356 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2357 { 2358 u16 i; 2359 2360 if (get_permanent_address(hw)) { 2361 /* for test */ 2362 /* FIXME: shouldn't we use random_ether_addr() here? */ 2363 hw->perm_mac_addr[0] = 0x00; 2364 hw->perm_mac_addr[1] = 0x13; 2365 hw->perm_mac_addr[2] = 0x74; 2366 hw->perm_mac_addr[3] = 0x00; 2367 hw->perm_mac_addr[4] = 0x5c; 2368 hw->perm_mac_addr[5] = 0x38; 2369 } 2370 2371 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 2372 hw->mac_addr[i] = hw->perm_mac_addr[i]; 2373 2374 return 0; 2375 } 2376 2377 /* 2378 * Hashes an address to determine its location in the multicast table 2379 * 2380 * hw - Struct containing variables accessed by shared code 2381 * mc_addr - the multicast address to hash 2382 * 2383 * atl2_hash_mc_addr 2384 * purpose 2385 * set hash value for a multicast address 2386 * hash calcu processing : 2387 * 1. calcu 32bit CRC for multicast address 2388 * 2. reverse crc with MSB to LSB 2389 */ 2390 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2391 { 2392 u32 crc32, value; 2393 int i; 2394 2395 value = 0; 2396 crc32 = ether_crc_le(6, mc_addr); 2397 2398 for (i = 0; i < 32; i++) 2399 value |= (((crc32 >> i) & 1) << (31 - i)); 2400 2401 return value; 2402 } 2403 2404 /* 2405 * Sets the bit in the multicast table corresponding to the hash value. 2406 * 2407 * hw - Struct containing variables accessed by shared code 2408 * hash_value - Multicast address hash value 2409 */ 2410 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2411 { 2412 u32 hash_bit, hash_reg; 2413 u32 mta; 2414 2415 /* The HASH Table is a register array of 2 32-bit registers. 2416 * It is treated like an array of 64 bits. We want to set 2417 * bit BitArray[hash_value]. So we figure out what register 2418 * the bit is in, read it, OR in the new bit, then write 2419 * back the new value. The register is determined by the 2420 * upper 7 bits of the hash value and the bit within that 2421 * register are determined by the lower 5 bits of the value. 2422 */ 2423 hash_reg = (hash_value >> 31) & 0x1; 2424 hash_bit = (hash_value >> 26) & 0x1F; 2425 2426 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2427 2428 mta |= (1 << hash_bit); 2429 2430 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2431 } 2432 2433 /* 2434 * atl2_init_pcie - init PCIE module 2435 */ 2436 static void atl2_init_pcie(struct atl2_hw *hw) 2437 { 2438 u32 value; 2439 value = LTSSM_TEST_MODE_DEF; 2440 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2441 2442 value = PCIE_DLL_TX_CTRL1_DEF; 2443 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2444 } 2445 2446 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2447 { 2448 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2449 hw->flash_vendor = 0; /* ATMEL */ 2450 2451 /* Init OP table */ 2452 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2453 flash_table[hw->flash_vendor].cmdPROGRAM); 2454 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2455 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2456 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2457 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2458 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2459 flash_table[hw->flash_vendor].cmdRDID); 2460 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2461 flash_table[hw->flash_vendor].cmdWREN); 2462 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2463 flash_table[hw->flash_vendor].cmdRDSR); 2464 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2465 flash_table[hw->flash_vendor].cmdWRSR); 2466 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2467 flash_table[hw->flash_vendor].cmdREAD); 2468 } 2469 2470 /******************************************************************** 2471 * Performs basic configuration of the adapter. 2472 * 2473 * hw - Struct containing variables accessed by shared code 2474 * Assumes that the controller has previously been reset and is in a 2475 * post-reset uninitialized state. Initializes multicast table, 2476 * and Calls routines to setup link 2477 * Leaves the transmit and receive units disabled and uninitialized. 2478 ********************************************************************/ 2479 static s32 atl2_init_hw(struct atl2_hw *hw) 2480 { 2481 u32 ret_val = 0; 2482 2483 atl2_init_pcie(hw); 2484 2485 /* Zero out the Multicast HASH table */ 2486 /* clear the old settings from the multicast hash table */ 2487 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2488 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2489 2490 atl2_init_flash_opcode(hw); 2491 2492 ret_val = atl2_phy_init(hw); 2493 2494 return ret_val; 2495 } 2496 2497 /* 2498 * Detects the current speed and duplex settings of the hardware. 2499 * 2500 * hw - Struct containing variables accessed by shared code 2501 * speed - Speed of the connection 2502 * duplex - Duplex setting of the connection 2503 */ 2504 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2505 u16 *duplex) 2506 { 2507 s32 ret_val; 2508 u16 phy_data; 2509 2510 /* Read PHY Specific Status Register (17) */ 2511 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2512 if (ret_val) 2513 return ret_val; 2514 2515 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2516 return ATLX_ERR_PHY_RES; 2517 2518 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2519 case MII_ATLX_PSSR_100MBS: 2520 *speed = SPEED_100; 2521 break; 2522 case MII_ATLX_PSSR_10MBS: 2523 *speed = SPEED_10; 2524 break; 2525 default: 2526 return ATLX_ERR_PHY_SPEED; 2527 break; 2528 } 2529 2530 if (phy_data & MII_ATLX_PSSR_DPLX) 2531 *duplex = FULL_DUPLEX; 2532 else 2533 *duplex = HALF_DUPLEX; 2534 2535 return 0; 2536 } 2537 2538 /* 2539 * Reads the value from a PHY register 2540 * hw - Struct containing variables accessed by shared code 2541 * reg_addr - address of the PHY register to read 2542 */ 2543 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2544 { 2545 u32 val; 2546 int i; 2547 2548 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2549 MDIO_START | 2550 MDIO_SUP_PREAMBLE | 2551 MDIO_RW | 2552 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2553 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2554 2555 wmb(); 2556 2557 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2558 udelay(2); 2559 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2560 if (!(val & (MDIO_START | MDIO_BUSY))) 2561 break; 2562 wmb(); 2563 } 2564 if (!(val & (MDIO_START | MDIO_BUSY))) { 2565 *phy_data = (u16)val; 2566 return 0; 2567 } 2568 2569 return ATLX_ERR_PHY; 2570 } 2571 2572 /* 2573 * Writes a value to a PHY register 2574 * hw - Struct containing variables accessed by shared code 2575 * reg_addr - address of the PHY register to write 2576 * data - data to write to the PHY 2577 */ 2578 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2579 { 2580 int i; 2581 u32 val; 2582 2583 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2584 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2585 MDIO_SUP_PREAMBLE | 2586 MDIO_START | 2587 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2588 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2589 2590 wmb(); 2591 2592 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2593 udelay(2); 2594 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2595 if (!(val & (MDIO_START | MDIO_BUSY))) 2596 break; 2597 2598 wmb(); 2599 } 2600 2601 if (!(val & (MDIO_START | MDIO_BUSY))) 2602 return 0; 2603 2604 return ATLX_ERR_PHY; 2605 } 2606 2607 /* 2608 * Configures PHY autoneg and flow control advertisement settings 2609 * 2610 * hw - Struct containing variables accessed by shared code 2611 */ 2612 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2613 { 2614 s32 ret_val; 2615 s16 mii_autoneg_adv_reg; 2616 2617 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2618 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2619 2620 /* Need to parse autoneg_advertised and set up 2621 * the appropriate PHY registers. First we will parse for 2622 * autoneg_advertised software override. Since we can advertise 2623 * a plethora of combinations, we need to check each bit 2624 * individually. 2625 */ 2626 2627 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2628 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2629 * the 1000Base-T Control Register (Address 9). */ 2630 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2631 2632 /* Need to parse MediaType and setup the 2633 * appropriate PHY registers. */ 2634 switch (hw->MediaType) { 2635 case MEDIA_TYPE_AUTO_SENSOR: 2636 mii_autoneg_adv_reg |= 2637 (MII_AR_10T_HD_CAPS | 2638 MII_AR_10T_FD_CAPS | 2639 MII_AR_100TX_HD_CAPS| 2640 MII_AR_100TX_FD_CAPS); 2641 hw->autoneg_advertised = 2642 ADVERTISE_10_HALF | 2643 ADVERTISE_10_FULL | 2644 ADVERTISE_100_HALF| 2645 ADVERTISE_100_FULL; 2646 break; 2647 case MEDIA_TYPE_100M_FULL: 2648 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2649 hw->autoneg_advertised = ADVERTISE_100_FULL; 2650 break; 2651 case MEDIA_TYPE_100M_HALF: 2652 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2653 hw->autoneg_advertised = ADVERTISE_100_HALF; 2654 break; 2655 case MEDIA_TYPE_10M_FULL: 2656 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2657 hw->autoneg_advertised = ADVERTISE_10_FULL; 2658 break; 2659 default: 2660 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2661 hw->autoneg_advertised = ADVERTISE_10_HALF; 2662 break; 2663 } 2664 2665 /* flow control fixed to enable all */ 2666 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2667 2668 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2669 2670 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2671 2672 if (ret_val) 2673 return ret_val; 2674 2675 return 0; 2676 } 2677 2678 /* 2679 * Resets the PHY and make all config validate 2680 * 2681 * hw - Struct containing variables accessed by shared code 2682 * 2683 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2684 */ 2685 static s32 atl2_phy_commit(struct atl2_hw *hw) 2686 { 2687 s32 ret_val; 2688 u16 phy_data; 2689 2690 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2691 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2692 if (ret_val) { 2693 u32 val; 2694 int i; 2695 /* pcie serdes link may be down ! */ 2696 for (i = 0; i < 25; i++) { 2697 msleep(1); 2698 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2699 if (!(val & (MDIO_START | MDIO_BUSY))) 2700 break; 2701 } 2702 2703 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2704 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2705 return ret_val; 2706 } 2707 } 2708 return 0; 2709 } 2710 2711 static s32 atl2_phy_init(struct atl2_hw *hw) 2712 { 2713 s32 ret_val; 2714 u16 phy_val; 2715 2716 if (hw->phy_configured) 2717 return 0; 2718 2719 /* Enable PHY */ 2720 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2721 ATL2_WRITE_FLUSH(hw); 2722 msleep(1); 2723 2724 /* check if the PHY is in powersaving mode */ 2725 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2726 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2727 2728 /* 024E / 124E 0r 0274 / 1274 ? */ 2729 if (phy_val & 0x1000) { 2730 phy_val &= ~0x1000; 2731 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2732 } 2733 2734 msleep(1); 2735 2736 /*Enable PHY LinkChange Interrupt */ 2737 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2738 if (ret_val) 2739 return ret_val; 2740 2741 /* setup AutoNeg parameters */ 2742 ret_val = atl2_phy_setup_autoneg_adv(hw); 2743 if (ret_val) 2744 return ret_val; 2745 2746 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2747 ret_val = atl2_phy_commit(hw); 2748 if (ret_val) 2749 return ret_val; 2750 2751 hw->phy_configured = true; 2752 2753 return ret_val; 2754 } 2755 2756 static void atl2_set_mac_addr(struct atl2_hw *hw) 2757 { 2758 u32 value; 2759 /* 00-0B-6A-F6-00-DC 2760 * 0: 6AF600DC 1: 000B 2761 * low dword */ 2762 value = (((u32)hw->mac_addr[2]) << 24) | 2763 (((u32)hw->mac_addr[3]) << 16) | 2764 (((u32)hw->mac_addr[4]) << 8) | 2765 (((u32)hw->mac_addr[5])); 2766 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2767 /* hight dword */ 2768 value = (((u32)hw->mac_addr[0]) << 8) | 2769 (((u32)hw->mac_addr[1])); 2770 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2771 } 2772 2773 /* 2774 * check_eeprom_exist 2775 * return 0 if eeprom exist 2776 */ 2777 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2778 { 2779 u32 value; 2780 2781 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2782 if (value & SPI_FLASH_CTRL_EN_VPD) { 2783 value &= ~SPI_FLASH_CTRL_EN_VPD; 2784 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2785 } 2786 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2787 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2788 } 2789 2790 /* FIXME: This doesn't look right. -- CHS */ 2791 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2792 { 2793 return true; 2794 } 2795 2796 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2797 { 2798 int i; 2799 u32 Control; 2800 2801 if (Offset & 0x3) 2802 return false; /* address do not align */ 2803 2804 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2805 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2806 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2807 2808 for (i = 0; i < 10; i++) { 2809 msleep(2); 2810 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2811 if (Control & VPD_CAP_VPD_FLAG) 2812 break; 2813 } 2814 2815 if (Control & VPD_CAP_VPD_FLAG) { 2816 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2817 return true; 2818 } 2819 return false; /* timeout */ 2820 } 2821 2822 static void atl2_force_ps(struct atl2_hw *hw) 2823 { 2824 u16 phy_val; 2825 2826 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2827 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2828 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2829 2830 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2831 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2832 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2833 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2834 } 2835 2836 /* This is the only thing that needs to be changed to adjust the 2837 * maximum number of ports that the driver can manage. 2838 */ 2839 #define ATL2_MAX_NIC 4 2840 2841 #define OPTION_UNSET -1 2842 #define OPTION_DISABLED 0 2843 #define OPTION_ENABLED 1 2844 2845 /* All parameters are treated the same, as an integer array of values. 2846 * This macro just reduces the need to repeat the same declaration code 2847 * over and over (plus this helps to avoid typo bugs). 2848 */ 2849 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2850 #ifndef module_param_array 2851 /* Module Parameters are always initialized to -1, so that the driver 2852 * can tell the difference between no user specified value or the 2853 * user asking for the default value. 2854 * The true default values are loaded in when atl2_check_options is called. 2855 * 2856 * This is a GCC extension to ANSI C. 2857 * See the item "Labeled Elements in Initializers" in the section 2858 * "Extensions to the C Language Family" of the GCC documentation. 2859 */ 2860 2861 #define ATL2_PARAM(X, desc) \ 2862 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2863 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2864 MODULE_PARM_DESC(X, desc); 2865 #else 2866 #define ATL2_PARAM(X, desc) \ 2867 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2868 static unsigned int num_##X; \ 2869 module_param_array_named(X, X, int, &num_##X, 0); \ 2870 MODULE_PARM_DESC(X, desc); 2871 #endif 2872 2873 /* 2874 * Transmit Memory Size 2875 * Valid Range: 64-2048 2876 * Default Value: 128 2877 */ 2878 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2879 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2880 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2881 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2882 2883 /* 2884 * Receive Memory Block Count 2885 * Valid Range: 16-512 2886 * Default Value: 128 2887 */ 2888 #define ATL2_MIN_RXD_COUNT 16 2889 #define ATL2_MAX_RXD_COUNT 512 2890 #define ATL2_DEFAULT_RXD_COUNT 64 2891 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2892 2893 /* 2894 * User Specified MediaType Override 2895 * 2896 * Valid Range: 0-5 2897 * - 0 - auto-negotiate at all supported speeds 2898 * - 1 - only link at 1000Mbps Full Duplex 2899 * - 2 - only link at 100Mbps Full Duplex 2900 * - 3 - only link at 100Mbps Half Duplex 2901 * - 4 - only link at 10Mbps Full Duplex 2902 * - 5 - only link at 10Mbps Half Duplex 2903 * Default Value: 0 2904 */ 2905 ATL2_PARAM(MediaType, "MediaType Select"); 2906 2907 /* 2908 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2909 * Valid Range: 10-65535 2910 * Default Value: 45000(90ms) 2911 */ 2912 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2913 #define INT_MOD_MAX_CNT 65000 2914 #define INT_MOD_MIN_CNT 50 2915 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2916 2917 /* 2918 * FlashVendor 2919 * Valid Range: 0-2 2920 * 0 - Atmel 2921 * 1 - SST 2922 * 2 - ST 2923 */ 2924 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2925 2926 #define AUTONEG_ADV_DEFAULT 0x2F 2927 #define AUTONEG_ADV_MASK 0x2F 2928 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2929 2930 #define FLASH_VENDOR_DEFAULT 0 2931 #define FLASH_VENDOR_MIN 0 2932 #define FLASH_VENDOR_MAX 2 2933 2934 struct atl2_option { 2935 enum { enable_option, range_option, list_option } type; 2936 char *name; 2937 char *err; 2938 int def; 2939 union { 2940 struct { /* range_option info */ 2941 int min; 2942 int max; 2943 } r; 2944 struct { /* list_option info */ 2945 int nr; 2946 struct atl2_opt_list { int i; char *str; } *p; 2947 } l; 2948 } arg; 2949 }; 2950 2951 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt) 2952 { 2953 int i; 2954 struct atl2_opt_list *ent; 2955 2956 if (*value == OPTION_UNSET) { 2957 *value = opt->def; 2958 return 0; 2959 } 2960 2961 switch (opt->type) { 2962 case enable_option: 2963 switch (*value) { 2964 case OPTION_ENABLED: 2965 printk(KERN_INFO "%s Enabled\n", opt->name); 2966 return 0; 2967 break; 2968 case OPTION_DISABLED: 2969 printk(KERN_INFO "%s Disabled\n", opt->name); 2970 return 0; 2971 break; 2972 } 2973 break; 2974 case range_option: 2975 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2976 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2977 return 0; 2978 } 2979 break; 2980 case list_option: 2981 for (i = 0; i < opt->arg.l.nr; i++) { 2982 ent = &opt->arg.l.p[i]; 2983 if (*value == ent->i) { 2984 if (ent->str[0] != '\0') 2985 printk(KERN_INFO "%s\n", ent->str); 2986 return 0; 2987 } 2988 } 2989 break; 2990 default: 2991 BUG(); 2992 } 2993 2994 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2995 opt->name, *value, opt->err); 2996 *value = opt->def; 2997 return -1; 2998 } 2999 3000 /* 3001 * atl2_check_options - Range Checking for Command Line Parameters 3002 * @adapter: board private structure 3003 * 3004 * This routine checks all command line parameters for valid user 3005 * input. If an invalid value is given, or if no user specified 3006 * value exists, a default value is used. The final value is stored 3007 * in a variable in the adapter structure. 3008 */ 3009 static void __devinit atl2_check_options(struct atl2_adapter *adapter) 3010 { 3011 int val; 3012 struct atl2_option opt; 3013 int bd = adapter->bd_number; 3014 if (bd >= ATL2_MAX_NIC) { 3015 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 3016 bd); 3017 printk(KERN_NOTICE "Using defaults for all values\n"); 3018 #ifndef module_param_array 3019 bd = ATL2_MAX_NIC; 3020 #endif 3021 } 3022 3023 /* Bytes of Transmit Memory */ 3024 opt.type = range_option; 3025 opt.name = "Bytes of Transmit Memory"; 3026 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 3027 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 3028 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 3029 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 3030 #ifdef module_param_array 3031 if (num_TxMemSize > bd) { 3032 #endif 3033 val = TxMemSize[bd]; 3034 atl2_validate_option(&val, &opt); 3035 adapter->txd_ring_size = ((u32) val) * 1024; 3036 #ifdef module_param_array 3037 } else 3038 adapter->txd_ring_size = ((u32)opt.def) * 1024; 3039 #endif 3040 /* txs ring size: */ 3041 adapter->txs_ring_size = adapter->txd_ring_size / 128; 3042 if (adapter->txs_ring_size > 160) 3043 adapter->txs_ring_size = 160; 3044 3045 /* Receive Memory Block Count */ 3046 opt.type = range_option; 3047 opt.name = "Number of receive memory block"; 3048 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 3049 opt.def = ATL2_DEFAULT_RXD_COUNT; 3050 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 3051 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 3052 #ifdef module_param_array 3053 if (num_RxMemBlock > bd) { 3054 #endif 3055 val = RxMemBlock[bd]; 3056 atl2_validate_option(&val, &opt); 3057 adapter->rxd_ring_size = (u32)val; 3058 /* FIXME */ 3059 /* ((u16)val)&~1; */ /* even number */ 3060 #ifdef module_param_array 3061 } else 3062 adapter->rxd_ring_size = (u32)opt.def; 3063 #endif 3064 /* init RXD Flow control value */ 3065 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3066 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3067 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3068 (adapter->rxd_ring_size / 12); 3069 3070 /* Interrupt Moderate Timer */ 3071 opt.type = range_option; 3072 opt.name = "Interrupt Moderate Timer"; 3073 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3074 opt.def = INT_MOD_DEFAULT_CNT; 3075 opt.arg.r.min = INT_MOD_MIN_CNT; 3076 opt.arg.r.max = INT_MOD_MAX_CNT; 3077 #ifdef module_param_array 3078 if (num_IntModTimer > bd) { 3079 #endif 3080 val = IntModTimer[bd]; 3081 atl2_validate_option(&val, &opt); 3082 adapter->imt = (u16) val; 3083 #ifdef module_param_array 3084 } else 3085 adapter->imt = (u16)(opt.def); 3086 #endif 3087 /* Flash Vendor */ 3088 opt.type = range_option; 3089 opt.name = "SPI Flash Vendor"; 3090 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3091 opt.def = FLASH_VENDOR_DEFAULT; 3092 opt.arg.r.min = FLASH_VENDOR_MIN; 3093 opt.arg.r.max = FLASH_VENDOR_MAX; 3094 #ifdef module_param_array 3095 if (num_FlashVendor > bd) { 3096 #endif 3097 val = FlashVendor[bd]; 3098 atl2_validate_option(&val, &opt); 3099 adapter->hw.flash_vendor = (u8) val; 3100 #ifdef module_param_array 3101 } else 3102 adapter->hw.flash_vendor = (u8)(opt.def); 3103 #endif 3104 /* MediaType */ 3105 opt.type = range_option; 3106 opt.name = "Speed/Duplex Selection"; 3107 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3108 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3109 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3110 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3111 #ifdef module_param_array 3112 if (num_MediaType > bd) { 3113 #endif 3114 val = MediaType[bd]; 3115 atl2_validate_option(&val, &opt); 3116 adapter->hw.MediaType = (u16) val; 3117 #ifdef module_param_array 3118 } else 3119 adapter->hw.MediaType = (u16)(opt.def); 3120 #endif 3121 } 3122