11fe003fdSJeff Kirsher #ifndef GRETH_H 21fe003fdSJeff Kirsher #define GRETH_H 31fe003fdSJeff Kirsher 41fe003fdSJeff Kirsher #include <linux/phy.h> 51fe003fdSJeff Kirsher 61fe003fdSJeff Kirsher /* Register bits and masks */ 71fe003fdSJeff Kirsher #define GRETH_RESET 0x40 81fe003fdSJeff Kirsher #define GRETH_MII_BUSY 0x8 91fe003fdSJeff Kirsher #define GRETH_MII_NVALID 0x10 101fe003fdSJeff Kirsher 111fe003fdSJeff Kirsher #define GRETH_CTRL_FD 0x10 121fe003fdSJeff Kirsher #define GRETH_CTRL_PR 0x20 131fe003fdSJeff Kirsher #define GRETH_CTRL_SP 0x80 141fe003fdSJeff Kirsher #define GRETH_CTRL_GB 0x100 151fe003fdSJeff Kirsher #define GRETH_CTRL_PSTATIEN 0x400 161fe003fdSJeff Kirsher #define GRETH_CTRL_MCEN 0x800 171fe003fdSJeff Kirsher #define GRETH_CTRL_DISDUPLEX 0x1000 181fe003fdSJeff Kirsher #define GRETH_STATUS_PHYSTAT 0x100 191fe003fdSJeff Kirsher 201fe003fdSJeff Kirsher #define GRETH_BD_EN 0x800 211fe003fdSJeff Kirsher #define GRETH_BD_WR 0x1000 221fe003fdSJeff Kirsher #define GRETH_BD_IE 0x2000 231fe003fdSJeff Kirsher #define GRETH_BD_LEN 0x7FF 241fe003fdSJeff Kirsher 251fe003fdSJeff Kirsher #define GRETH_TXEN 0x1 261fe003fdSJeff Kirsher #define GRETH_INT_TE 0x2 271fe003fdSJeff Kirsher #define GRETH_INT_TX 0x8 281fe003fdSJeff Kirsher #define GRETH_TXI 0x4 291fe003fdSJeff Kirsher #define GRETH_TXBD_STATUS 0x0001C000 301fe003fdSJeff Kirsher #define GRETH_TXBD_MORE 0x20000 311fe003fdSJeff Kirsher #define GRETH_TXBD_IPCS 0x40000 321fe003fdSJeff Kirsher #define GRETH_TXBD_TCPCS 0x80000 331fe003fdSJeff Kirsher #define GRETH_TXBD_UDPCS 0x100000 341fe003fdSJeff Kirsher #define GRETH_TXBD_CSALL (GRETH_TXBD_IPCS | GRETH_TXBD_TCPCS | GRETH_TXBD_UDPCS) 351fe003fdSJeff Kirsher #define GRETH_TXBD_ERR_LC 0x10000 361fe003fdSJeff Kirsher #define GRETH_TXBD_ERR_UE 0x4000 371fe003fdSJeff Kirsher #define GRETH_TXBD_ERR_AL 0x8000 381fe003fdSJeff Kirsher 391fe003fdSJeff Kirsher #define GRETH_INT_RE 0x1 401fe003fdSJeff Kirsher #define GRETH_INT_RX 0x4 411fe003fdSJeff Kirsher #define GRETH_RXEN 0x2 421fe003fdSJeff Kirsher #define GRETH_RXI 0x8 431fe003fdSJeff Kirsher #define GRETH_RXBD_STATUS 0xFFFFC000 441fe003fdSJeff Kirsher #define GRETH_RXBD_ERR_AE 0x4000 451fe003fdSJeff Kirsher #define GRETH_RXBD_ERR_FT 0x8000 461fe003fdSJeff Kirsher #define GRETH_RXBD_ERR_CRC 0x10000 471fe003fdSJeff Kirsher #define GRETH_RXBD_ERR_OE 0x20000 481fe003fdSJeff Kirsher #define GRETH_RXBD_ERR_LE 0x40000 491fe003fdSJeff Kirsher #define GRETH_RXBD_IP 0x80000 501fe003fdSJeff Kirsher #define GRETH_RXBD_IP_CSERR 0x100000 511fe003fdSJeff Kirsher #define GRETH_RXBD_UDP 0x200000 521fe003fdSJeff Kirsher #define GRETH_RXBD_UDP_CSERR 0x400000 531fe003fdSJeff Kirsher #define GRETH_RXBD_TCP 0x800000 541fe003fdSJeff Kirsher #define GRETH_RXBD_TCP_CSERR 0x1000000 551fe003fdSJeff Kirsher #define GRETH_RXBD_IP_FRAG 0x2000000 561fe003fdSJeff Kirsher #define GRETH_RXBD_MCAST 0x4000000 571fe003fdSJeff Kirsher 581fe003fdSJeff Kirsher /* Descriptor parameters */ 591fe003fdSJeff Kirsher #define GRETH_TXBD_NUM 128 601fe003fdSJeff Kirsher #define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) 611fe003fdSJeff Kirsher #define GRETH_TX_BUF_SIZE 2048 621fe003fdSJeff Kirsher #define GRETH_RXBD_NUM 128 631fe003fdSJeff Kirsher #define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) 641fe003fdSJeff Kirsher #define GRETH_RX_BUF_SIZE 2048 651fe003fdSJeff Kirsher 661fe003fdSJeff Kirsher /* Buffers per page */ 671fe003fdSJeff Kirsher #define GRETH_RX_BUF_PPGAE (PAGE_SIZE/GRETH_RX_BUF_SIZE) 681fe003fdSJeff Kirsher #define GRETH_TX_BUF_PPGAE (PAGE_SIZE/GRETH_TX_BUF_SIZE) 691fe003fdSJeff Kirsher 701fe003fdSJeff Kirsher /* How many pages are needed for buffers */ 711fe003fdSJeff Kirsher #define GRETH_RX_BUF_PAGE_NUM (GRETH_RXBD_NUM/GRETH_RX_BUF_PPGAE) 721fe003fdSJeff Kirsher #define GRETH_TX_BUF_PAGE_NUM (GRETH_TXBD_NUM/GRETH_TX_BUF_PPGAE) 731fe003fdSJeff Kirsher 741fe003fdSJeff Kirsher /* Buffer size. 751fe003fdSJeff Kirsher * Gbit MAC uses tagged maximum frame size which is 1518 excluding CRC. 761fe003fdSJeff Kirsher * Set to 1520 to make all buffers word aligned for non-gbit MAC. 771fe003fdSJeff Kirsher */ 781fe003fdSJeff Kirsher #define MAX_FRAME_SIZE 1520 791fe003fdSJeff Kirsher 801fe003fdSJeff Kirsher /* GRETH APB registers */ 811fe003fdSJeff Kirsher struct greth_regs { 821fe003fdSJeff Kirsher u32 control; 831fe003fdSJeff Kirsher u32 status; 841fe003fdSJeff Kirsher u32 esa_msb; 851fe003fdSJeff Kirsher u32 esa_lsb; 861fe003fdSJeff Kirsher u32 mdio; 871fe003fdSJeff Kirsher u32 tx_desc_p; 881fe003fdSJeff Kirsher u32 rx_desc_p; 891fe003fdSJeff Kirsher u32 edclip; 901fe003fdSJeff Kirsher u32 hash_msb; 911fe003fdSJeff Kirsher u32 hash_lsb; 921fe003fdSJeff Kirsher }; 931fe003fdSJeff Kirsher 941fe003fdSJeff Kirsher /* GRETH buffer descriptor */ 951fe003fdSJeff Kirsher struct greth_bd { 961fe003fdSJeff Kirsher u32 stat; 971fe003fdSJeff Kirsher u32 addr; 981fe003fdSJeff Kirsher }; 991fe003fdSJeff Kirsher 1001fe003fdSJeff Kirsher struct greth_private { 1011fe003fdSJeff Kirsher struct sk_buff *rx_skbuff[GRETH_RXBD_NUM]; 1021fe003fdSJeff Kirsher struct sk_buff *tx_skbuff[GRETH_TXBD_NUM]; 1031fe003fdSJeff Kirsher 1041fe003fdSJeff Kirsher unsigned char *tx_bufs[GRETH_TXBD_NUM]; 1051fe003fdSJeff Kirsher unsigned char *rx_bufs[GRETH_RXBD_NUM]; 106*8decf868SDavid S. Miller u16 tx_bufs_length[GRETH_TXBD_NUM]; 1071fe003fdSJeff Kirsher 1081fe003fdSJeff Kirsher u16 tx_next; 1091fe003fdSJeff Kirsher u16 tx_last; 1101fe003fdSJeff Kirsher u16 tx_free; 1111fe003fdSJeff Kirsher u16 rx_cur; 1121fe003fdSJeff Kirsher 1131fe003fdSJeff Kirsher struct greth_regs *regs; /* Address of controller registers. */ 1141fe003fdSJeff Kirsher struct greth_bd *rx_bd_base; /* Address of Rx BDs. */ 1151fe003fdSJeff Kirsher struct greth_bd *tx_bd_base; /* Address of Tx BDs. */ 1161fe003fdSJeff Kirsher dma_addr_t rx_bd_base_phys; 1171fe003fdSJeff Kirsher dma_addr_t tx_bd_base_phys; 1181fe003fdSJeff Kirsher 1191fe003fdSJeff Kirsher int irq; 1201fe003fdSJeff Kirsher 1211fe003fdSJeff Kirsher struct device *dev; /* Pointer to platform_device->dev */ 1221fe003fdSJeff Kirsher struct net_device *netdev; 1231fe003fdSJeff Kirsher struct napi_struct napi; 1241fe003fdSJeff Kirsher spinlock_t devlock; 1251fe003fdSJeff Kirsher 1261fe003fdSJeff Kirsher struct phy_device *phy; 1271fe003fdSJeff Kirsher struct mii_bus *mdio; 1281fe003fdSJeff Kirsher int mdio_irqs[PHY_MAX_ADDR]; 1291fe003fdSJeff Kirsher unsigned int link; 1301fe003fdSJeff Kirsher unsigned int speed; 1311fe003fdSJeff Kirsher unsigned int duplex; 1321fe003fdSJeff Kirsher 1331fe003fdSJeff Kirsher u32 msg_enable; 1341fe003fdSJeff Kirsher 1351fe003fdSJeff Kirsher u8 phyaddr; 1361fe003fdSJeff Kirsher u8 multicast; 1371fe003fdSJeff Kirsher u8 gbit_mac; 1381fe003fdSJeff Kirsher u8 mdio_int_en; 1391fe003fdSJeff Kirsher u8 edcl; 1401fe003fdSJeff Kirsher }; 1411fe003fdSJeff Kirsher 1421fe003fdSJeff Kirsher #endif 143