1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <linux/dsa/8021q.h> 12 #include <net/dsa.h> 13 #include <linux/mutex.h> 14 #include "sja1105_static_config.h" 15 16 #define SJA1105_NUM_PORTS 5 17 #define SJA1105_MAX_NUM_PORTS SJA1105_NUM_PORTS 18 #define SJA1105_NUM_TC 8 19 #define SJA1105ET_FDB_BIN_SIZE 4 20 /* The hardware value is in multiples of 10 ms. 21 * The passed parameter is in multiples of 1 ms. 22 */ 23 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 24 #define SJA1105_NUM_L2_POLICERS 45 25 26 typedef enum { 27 SPI_READ = 0, 28 SPI_WRITE = 1, 29 } sja1105_spi_rw_mode_t; 30 31 #include "sja1105_tas.h" 32 #include "sja1105_ptp.h" 33 34 enum sja1105_stats_area { 35 MAC, 36 HL1, 37 HL2, 38 ETHER, 39 __MAX_SJA1105_STATS_AREA, 40 }; 41 42 /* Keeps the different addresses between E/T and P/Q/R/S */ 43 struct sja1105_regs { 44 u64 device_id; 45 u64 prod_id; 46 u64 status; 47 u64 port_control; 48 u64 rgu; 49 u64 vl_status; 50 u64 config; 51 u64 rmii_pll1; 52 u64 ptppinst; 53 u64 ptppindur; 54 u64 ptp_control; 55 u64 ptpclkval; 56 u64 ptpclkrate; 57 u64 ptpclkcorp; 58 u64 ptpsyncts; 59 u64 ptpschtm; 60 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; 61 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; 62 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; 63 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; 64 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; 65 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; 66 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; 67 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 68 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; 69 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; 70 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; 71 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 72 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; 73 }; 74 75 struct sja1105_info { 76 u64 device_id; 77 /* Needed for distinction between P and R, and between Q and S 78 * (since the parts with/without SGMII share the same 79 * switch core and device_id) 80 */ 81 u64 part_no; 82 /* E/T and P/Q/R/S have partial timestamps of different sizes. 83 * They must be reconstructed on both families anyway to get the full 84 * 64-bit values back. 85 */ 86 int ptp_ts_bits; 87 /* Also SPI commands are of different sizes to retrieve 88 * the egress timestamps. 89 */ 90 int ptpegr_ts_bytes; 91 int num_cbs_shapers; 92 int max_frame_mem; 93 const struct sja1105_dynamic_table_ops *dyn_ops; 94 const struct sja1105_table_ops *static_ops; 95 const struct sja1105_regs *regs; 96 /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag 97 * from double-tagged frames. E/T will pop it only when it's equal to 98 * TPID from the General Parameters Table, while P/Q/R/S will only 99 * pop it when it's equal to TPID2. 100 */ 101 u16 qinq_tpid; 102 bool can_limit_mcast_flood; 103 int (*reset_cmd)(struct dsa_switch *ds); 104 int (*setup_rgmii_delay)(const void *ctx, int port); 105 /* Prototypes from include/net/dsa.h */ 106 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 107 const unsigned char *addr, u16 vid); 108 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 109 const unsigned char *addr, u16 vid); 110 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 111 enum packing_op op); 112 int (*clocking_setup)(struct sja1105_private *priv); 113 const char *name; 114 }; 115 116 enum sja1105_key_type { 117 SJA1105_KEY_BCAST, 118 SJA1105_KEY_TC, 119 SJA1105_KEY_VLAN_UNAWARE_VL, 120 SJA1105_KEY_VLAN_AWARE_VL, 121 }; 122 123 struct sja1105_key { 124 enum sja1105_key_type type; 125 126 union { 127 /* SJA1105_KEY_TC */ 128 struct { 129 int pcp; 130 } tc; 131 132 /* SJA1105_KEY_VLAN_UNAWARE_VL */ 133 /* SJA1105_KEY_VLAN_AWARE_VL */ 134 struct { 135 u64 dmac; 136 u16 vid; 137 u16 pcp; 138 } vl; 139 }; 140 }; 141 142 enum sja1105_rule_type { 143 SJA1105_RULE_BCAST_POLICER, 144 SJA1105_RULE_TC_POLICER, 145 SJA1105_RULE_VL, 146 }; 147 148 enum sja1105_vl_type { 149 SJA1105_VL_NONCRITICAL, 150 SJA1105_VL_RATE_CONSTRAINED, 151 SJA1105_VL_TIME_TRIGGERED, 152 }; 153 154 struct sja1105_rule { 155 struct list_head list; 156 unsigned long cookie; 157 unsigned long port_mask; 158 struct sja1105_key key; 159 enum sja1105_rule_type type; 160 161 /* Action */ 162 union { 163 /* SJA1105_RULE_BCAST_POLICER */ 164 struct { 165 int sharindx; 166 } bcast_pol; 167 168 /* SJA1105_RULE_TC_POLICER */ 169 struct { 170 int sharindx; 171 } tc_pol; 172 173 /* SJA1105_RULE_VL */ 174 struct { 175 enum sja1105_vl_type type; 176 unsigned long destports; 177 int sharindx; 178 int maxlen; 179 int ipv; 180 u64 base_time; 181 u64 cycle_time; 182 int num_entries; 183 struct action_gate_entry *entries; 184 struct flow_stats stats; 185 } vl; 186 }; 187 }; 188 189 struct sja1105_flow_block { 190 struct list_head rules; 191 bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; 192 int num_virtual_links; 193 }; 194 195 struct sja1105_bridge_vlan { 196 struct list_head list; 197 int port; 198 u16 vid; 199 bool pvid; 200 bool untagged; 201 }; 202 203 enum sja1105_vlan_state { 204 SJA1105_VLAN_UNAWARE, 205 SJA1105_VLAN_BEST_EFFORT, 206 SJA1105_VLAN_FILTERING_FULL, 207 }; 208 209 struct sja1105_private { 210 struct sja1105_static_config static_config; 211 bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS]; 212 bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS]; 213 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; 214 bool best_effort_vlan_filtering; 215 unsigned long learn_ena; 216 unsigned long ucast_egress_floods; 217 unsigned long bcast_egress_floods; 218 const struct sja1105_info *info; 219 size_t max_xfer_len; 220 struct gpio_desc *reset_gpio; 221 struct spi_device *spidev; 222 struct dsa_switch *ds; 223 struct list_head dsa_8021q_vlans; 224 struct list_head bridge_vlans; 225 struct sja1105_flow_block flow_block; 226 struct sja1105_port ports[SJA1105_MAX_NUM_PORTS]; 227 /* Serializes transmission of management frames so that 228 * the switch doesn't confuse them with one another. 229 */ 230 struct mutex mgmt_lock; 231 struct dsa_8021q_context *dsa_8021q_ctx; 232 enum sja1105_vlan_state vlan_state; 233 struct devlink_region **regions; 234 struct sja1105_cbs_entry *cbs; 235 struct sja1105_tagger_data tagger_data; 236 struct sja1105_ptp_data ptp_data; 237 struct sja1105_tas_data tas_data; 238 }; 239 240 #include "sja1105_dynamic_config.h" 241 242 struct sja1105_spi_message { 243 u64 access; 244 u64 read_count; 245 u64 address; 246 }; 247 248 /* From sja1105_main.c */ 249 enum sja1105_reset_reason { 250 SJA1105_VLAN_FILTERING = 0, 251 SJA1105_RX_HWTSTAMPING, 252 SJA1105_AGEING_TIME, 253 SJA1105_SCHEDULING, 254 SJA1105_BEST_EFFORT_POLICING, 255 SJA1105_VIRTUAL_LINKS, 256 }; 257 258 int sja1105_static_config_reload(struct sja1105_private *priv, 259 enum sja1105_reset_reason reason); 260 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 261 struct netlink_ext_ack *extack); 262 void sja1105_frame_memory_partitioning(struct sja1105_private *priv); 263 264 /* From sja1105_devlink.c */ 265 int sja1105_devlink_setup(struct dsa_switch *ds); 266 void sja1105_devlink_teardown(struct dsa_switch *ds); 267 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id, 268 struct devlink_param_gset_ctx *ctx); 269 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id, 270 struct devlink_param_gset_ctx *ctx); 271 int sja1105_devlink_info_get(struct dsa_switch *ds, 272 struct devlink_info_req *req, 273 struct netlink_ext_ack *extack); 274 275 /* From sja1105_spi.c */ 276 int sja1105_xfer_buf(const struct sja1105_private *priv, 277 sja1105_spi_rw_mode_t rw, u64 reg_addr, 278 u8 *buf, size_t len); 279 int sja1105_xfer_u32(const struct sja1105_private *priv, 280 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 281 struct ptp_system_timestamp *ptp_sts); 282 int sja1105_xfer_u64(const struct sja1105_private *priv, 283 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 284 struct ptp_system_timestamp *ptp_sts); 285 int static_config_buf_prepare_for_upload(struct sja1105_private *priv, 286 void *config_buf, int buf_len); 287 int sja1105_static_config_upload(struct sja1105_private *priv); 288 int sja1105_inhibit_tx(const struct sja1105_private *priv, 289 unsigned long port_bitmap, bool tx_inhibited); 290 291 extern const struct sja1105_info sja1105e_info; 292 extern const struct sja1105_info sja1105t_info; 293 extern const struct sja1105_info sja1105p_info; 294 extern const struct sja1105_info sja1105q_info; 295 extern const struct sja1105_info sja1105r_info; 296 extern const struct sja1105_info sja1105s_info; 297 298 /* From sja1105_clocking.c */ 299 300 typedef enum { 301 XMII_MAC = 0, 302 XMII_PHY = 1, 303 } sja1105_mii_role_t; 304 305 typedef enum { 306 XMII_MODE_MII = 0, 307 XMII_MODE_RMII = 1, 308 XMII_MODE_RGMII = 2, 309 XMII_MODE_SGMII = 3, 310 } sja1105_phy_interface_t; 311 312 typedef enum { 313 SJA1105_SPEED_10MBPS = 3, 314 SJA1105_SPEED_100MBPS = 2, 315 SJA1105_SPEED_1000MBPS = 1, 316 SJA1105_SPEED_AUTO = 0, 317 } sja1105_speed_t; 318 319 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 320 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 321 int sja1105_clocking_setup(struct sja1105_private *priv); 322 323 /* From sja1105_ethtool.c */ 324 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 325 void sja1105_get_strings(struct dsa_switch *ds, int port, 326 u32 stringset, u8 *data); 327 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 328 329 /* From sja1105_dynamic_config.c */ 330 int sja1105_dynamic_config_read(struct sja1105_private *priv, 331 enum sja1105_blk_idx blk_idx, 332 int index, void *entry); 333 int sja1105_dynamic_config_write(struct sja1105_private *priv, 334 enum sja1105_blk_idx blk_idx, 335 int index, void *entry, bool keep); 336 337 enum sja1105_iotag { 338 SJA1105_C_TAG = 0, /* Inner VLAN header */ 339 SJA1105_S_TAG = 1, /* Outer VLAN header */ 340 }; 341 342 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 343 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 344 const unsigned char *addr, u16 vid); 345 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 346 const unsigned char *addr, u16 vid); 347 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 348 const unsigned char *addr, u16 vid); 349 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 350 const unsigned char *addr, u16 vid); 351 352 /* From sja1105_flower.c */ 353 int sja1105_cls_flower_del(struct dsa_switch *ds, int port, 354 struct flow_cls_offload *cls, bool ingress); 355 int sja1105_cls_flower_add(struct dsa_switch *ds, int port, 356 struct flow_cls_offload *cls, bool ingress); 357 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, 358 struct flow_cls_offload *cls, bool ingress); 359 void sja1105_flower_setup(struct dsa_switch *ds); 360 void sja1105_flower_teardown(struct dsa_switch *ds); 361 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, 362 unsigned long cookie); 363 364 #endif 365