1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 453 mode = chip->info->ops->port_max_speed_mode(port); 454 455 if (chip->info->ops->port_set_pause) { 456 err = chip->info->ops->port_set_pause(chip, port, pause); 457 if (err) 458 goto restore_link; 459 } 460 461 err = mv88e6xxx_port_config_interface(chip, port, mode); 462 restore_link: 463 if (chip->info->ops->port_set_link(chip, port, link)) 464 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 465 466 return err; 467 } 468 469 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 470 { 471 struct mv88e6xxx_chip *chip = ds->priv; 472 473 return port < chip->info->num_internal_phys; 474 } 475 476 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 477 { 478 u16 reg; 479 int err; 480 481 /* The 88e6250 family does not have the PHY detect bit. Instead, 482 * report whether the port is internal. 483 */ 484 if (chip->info->family == MV88E6XXX_FAMILY_6250) 485 return port < chip->info->num_internal_phys; 486 487 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 488 if (err) { 489 dev_err(chip->dev, 490 "p%d: %s: failed to read port status\n", 491 port, __func__); 492 return err; 493 } 494 495 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 496 } 497 498 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 499 struct phylink_link_state *state) 500 { 501 struct mv88e6xxx_chip *chip = ds->priv; 502 int lane; 503 int err; 504 505 mv88e6xxx_reg_lock(chip); 506 lane = mv88e6xxx_serdes_get_lane(chip, port); 507 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 508 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 509 state); 510 else 511 err = -EOPNOTSUPP; 512 mv88e6xxx_reg_unlock(chip); 513 514 return err; 515 } 516 517 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 518 unsigned int mode, 519 phy_interface_t interface, 520 const unsigned long *advertise) 521 { 522 const struct mv88e6xxx_ops *ops = chip->info->ops; 523 int lane; 524 525 if (ops->serdes_pcs_config) { 526 lane = mv88e6xxx_serdes_get_lane(chip, port); 527 if (lane >= 0) 528 return ops->serdes_pcs_config(chip, port, lane, mode, 529 interface, advertise); 530 } 531 532 return 0; 533 } 534 535 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 536 { 537 struct mv88e6xxx_chip *chip = ds->priv; 538 const struct mv88e6xxx_ops *ops; 539 int err = 0; 540 int lane; 541 542 ops = chip->info->ops; 543 544 if (ops->serdes_pcs_an_restart) { 545 mv88e6xxx_reg_lock(chip); 546 lane = mv88e6xxx_serdes_get_lane(chip, port); 547 if (lane >= 0) 548 err = ops->serdes_pcs_an_restart(chip, port, lane); 549 mv88e6xxx_reg_unlock(chip); 550 551 if (err) 552 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 553 } 554 } 555 556 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 557 unsigned int mode, 558 int speed, int duplex) 559 { 560 const struct mv88e6xxx_ops *ops = chip->info->ops; 561 int lane; 562 563 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 564 lane = mv88e6xxx_serdes_get_lane(chip, port); 565 if (lane >= 0) 566 return ops->serdes_pcs_link_up(chip, port, lane, 567 speed, duplex); 568 } 569 570 return 0; 571 } 572 573 static const u8 mv88e6185_phy_interface_modes[] = { 574 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 575 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 576 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 577 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 578 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 579 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 580 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 581 }; 582 583 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 584 struct phylink_config *config) 585 { 586 u8 cmode = chip->ports[port].cmode; 587 588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 589 590 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 591 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 592 } else { 593 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 594 mv88e6185_phy_interface_modes[cmode]) 595 __set_bit(mv88e6185_phy_interface_modes[cmode], 596 config->supported_interfaces); 597 598 config->mac_capabilities |= MAC_1000FD; 599 } 600 } 601 602 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 603 struct phylink_config *config) 604 { 605 u8 cmode = chip->ports[port].cmode; 606 607 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 608 mv88e6185_phy_interface_modes[cmode]) 609 __set_bit(mv88e6185_phy_interface_modes[cmode], 610 config->supported_interfaces); 611 612 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 613 MAC_1000FD; 614 } 615 616 static const u8 mv88e6xxx_phy_interface_modes[] = { 617 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII, 618 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 619 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 620 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII, 621 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 622 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 623 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 624 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 625 /* higher interface modes are not needed here, since ports supporting 626 * them are writable, and so the supported interfaces are filled in the 627 * corresponding .phylink_set_interfaces() implementation below 628 */ 629 }; 630 631 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 632 { 633 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 634 mv88e6xxx_phy_interface_modes[cmode]) 635 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 636 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 637 phy_interface_set_rgmii(supported); 638 } 639 640 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 641 struct phylink_config *config) 642 { 643 unsigned long *supported = config->supported_interfaces; 644 645 /* Translate the default cmode */ 646 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 647 648 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 649 } 650 651 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 652 { 653 u16 reg, val; 654 int err; 655 656 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 657 if (err) 658 return err; 659 660 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 661 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 662 return 0xf; 663 664 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 665 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 666 if (err) 667 return err; 668 669 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 670 if (err) 671 return err; 672 673 /* Restore PHY_DETECT value */ 674 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 675 if (err) 676 return err; 677 678 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 679 } 680 681 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 682 struct phylink_config *config) 683 { 684 unsigned long *supported = config->supported_interfaces; 685 int err, cmode; 686 687 /* Translate the default cmode */ 688 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 689 690 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 691 MAC_1000FD; 692 693 /* Port 4 supports automedia if the serdes is associated with it. */ 694 if (port == 4) { 695 mv88e6xxx_reg_lock(chip); 696 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 697 if (err < 0) 698 dev_err(chip->dev, "p%d: failed to read scratch\n", 699 port); 700 if (err <= 0) 701 goto unlock; 702 703 cmode = mv88e6352_get_port4_serdes_cmode(chip); 704 if (cmode < 0) 705 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 706 port); 707 else 708 mv88e6xxx_translate_cmode(cmode, supported); 709 unlock: 710 mv88e6xxx_reg_unlock(chip); 711 } 712 } 713 714 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 715 struct phylink_config *config) 716 { 717 unsigned long *supported = config->supported_interfaces; 718 719 /* Translate the default cmode */ 720 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 721 722 /* No ethtool bits for 200Mbps */ 723 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 724 MAC_1000FD; 725 726 /* The C_Mode field is programmable on port 5 */ 727 if (port == 5) { 728 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 729 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 730 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 731 732 config->mac_capabilities |= MAC_2500FD; 733 } 734 } 735 736 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 737 struct phylink_config *config) 738 { 739 unsigned long *supported = config->supported_interfaces; 740 741 /* Translate the default cmode */ 742 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 743 744 /* No ethtool bits for 200Mbps */ 745 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 746 MAC_1000FD; 747 748 /* The C_Mode field is programmable on ports 9 and 10 */ 749 if (port == 9 || port == 10) { 750 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 751 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 753 754 config->mac_capabilities |= MAC_2500FD; 755 } 756 } 757 758 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 759 struct phylink_config *config) 760 { 761 unsigned long *supported = config->supported_interfaces; 762 763 mv88e6390_phylink_get_caps(chip, port, config); 764 765 /* For the 6x90X, ports 2-7 can be in automedia mode. 766 * (Note that 6x90 doesn't support RXAUI nor XAUI). 767 * 768 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 769 * configured for 1000BASE-X, SGMII or 2500BASE-X. 770 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 771 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 772 * 773 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 774 * configured for 1000BASE-X, SGMII or 2500BASE-X. 775 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 776 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 777 * 778 * For now, be permissive (as the old code was) and allow 1000BASE-X 779 * on ports 2..7. 780 */ 781 if (port >= 2 && port <= 7) 782 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 783 784 /* The C_Mode field can also be programmed for 10G speeds */ 785 if (port == 9 || port == 10) { 786 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 787 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 788 789 config->mac_capabilities |= MAC_10000FD; 790 } 791 } 792 793 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 794 struct phylink_config *config) 795 { 796 unsigned long *supported = config->supported_interfaces; 797 bool is_6191x = 798 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 799 800 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 801 802 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 803 MAC_1000FD; 804 805 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 806 if (port == 0 || port == 9 || port == 10) { 807 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 808 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 809 810 /* 6191X supports >1G modes only on port 10 */ 811 if (!is_6191x || port == 10) { 812 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 813 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 814 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 815 /* FIXME: USXGMII is not supported yet */ 816 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 817 818 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 819 MAC_10000FD; 820 } 821 } 822 } 823 824 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 825 struct phylink_config *config) 826 { 827 struct mv88e6xxx_chip *chip = ds->priv; 828 829 chip->info->ops->phylink_get_caps(chip, port, config); 830 831 /* Internal ports need GMII for PHYLIB */ 832 if (mv88e6xxx_phy_is_internal(ds, port)) 833 __set_bit(PHY_INTERFACE_MODE_GMII, 834 config->supported_interfaces); 835 } 836 837 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 838 unsigned int mode, 839 const struct phylink_link_state *state) 840 { 841 struct mv88e6xxx_chip *chip = ds->priv; 842 struct mv88e6xxx_port *p; 843 int err = 0; 844 845 p = &chip->ports[port]; 846 847 mv88e6xxx_reg_lock(chip); 848 849 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 850 /* In inband mode, the link may come up at any time while the 851 * link is not forced down. Force the link down while we 852 * reconfigure the interface mode. 853 */ 854 if (mode == MLO_AN_INBAND && 855 p->interface != state->interface && 856 chip->info->ops->port_set_link) 857 chip->info->ops->port_set_link(chip, port, 858 LINK_FORCED_DOWN); 859 860 err = mv88e6xxx_port_config_interface(chip, port, 861 state->interface); 862 if (err && err != -EOPNOTSUPP) 863 goto err_unlock; 864 865 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 866 state->interface, 867 state->advertising); 868 /* FIXME: we should restart negotiation if something changed - 869 * which is something we get if we convert to using phylinks 870 * PCS operations. 871 */ 872 if (err > 0) 873 err = 0; 874 } 875 876 /* Undo the forced down state above after completing configuration 877 * irrespective of its state on entry, which allows the link to come 878 * up in the in-band case where there is no separate SERDES. Also 879 * ensure that the link can come up if the PPU is in use and we are 880 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 881 */ 882 if (chip->info->ops->port_set_link && 883 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 884 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 885 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 886 887 p->interface = state->interface; 888 889 err_unlock: 890 mv88e6xxx_reg_unlock(chip); 891 892 if (err && err != -EOPNOTSUPP) 893 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 894 } 895 896 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 897 unsigned int mode, 898 phy_interface_t interface) 899 { 900 struct mv88e6xxx_chip *chip = ds->priv; 901 const struct mv88e6xxx_ops *ops; 902 int err = 0; 903 904 ops = chip->info->ops; 905 906 mv88e6xxx_reg_lock(chip); 907 /* Force the link down if we know the port may not be automatically 908 * updated by the switch or if we are using fixed-link mode. 909 */ 910 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 911 mode == MLO_AN_FIXED) && ops->port_sync_link) 912 err = ops->port_sync_link(chip, port, mode, false); 913 914 if (!err && ops->port_set_speed_duplex) 915 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 916 DUPLEX_UNFORCED); 917 mv88e6xxx_reg_unlock(chip); 918 919 if (err) 920 dev_err(chip->dev, 921 "p%d: failed to force MAC link down\n", port); 922 } 923 924 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 925 unsigned int mode, phy_interface_t interface, 926 struct phy_device *phydev, 927 int speed, int duplex, 928 bool tx_pause, bool rx_pause) 929 { 930 struct mv88e6xxx_chip *chip = ds->priv; 931 const struct mv88e6xxx_ops *ops; 932 int err = 0; 933 934 ops = chip->info->ops; 935 936 mv88e6xxx_reg_lock(chip); 937 /* Configure and force the link up if we know that the port may not 938 * automatically updated by the switch or if we are using fixed-link 939 * mode. 940 */ 941 if (!mv88e6xxx_port_ppu_updates(chip, port) || 942 mode == MLO_AN_FIXED) { 943 /* FIXME: for an automedia port, should we force the link 944 * down here - what if the link comes up due to "other" media 945 * while we're bringing the port up, how is the exclusivity 946 * handled in the Marvell hardware? E.g. port 2 on 88E6390 947 * shared between internal PHY and Serdes. 948 */ 949 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 950 duplex); 951 if (err) 952 goto error; 953 954 if (ops->port_set_speed_duplex) { 955 err = ops->port_set_speed_duplex(chip, port, 956 speed, duplex); 957 if (err && err != -EOPNOTSUPP) 958 goto error; 959 } 960 961 if (ops->port_sync_link) 962 err = ops->port_sync_link(chip, port, mode, true); 963 } 964 error: 965 mv88e6xxx_reg_unlock(chip); 966 967 if (err && err != -EOPNOTSUPP) 968 dev_err(ds->dev, 969 "p%d: failed to configure MAC link up\n", port); 970 } 971 972 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 973 { 974 if (!chip->info->ops->stats_snapshot) 975 return -EOPNOTSUPP; 976 977 return chip->info->ops->stats_snapshot(chip, port); 978 } 979 980 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 981 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 982 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 983 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 984 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 985 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 986 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 987 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 988 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 989 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 990 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 991 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 992 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 993 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 994 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 995 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 996 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 997 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 998 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 999 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1000 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1001 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1002 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1003 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1004 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1005 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1006 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1007 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1008 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1009 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1010 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1011 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1012 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1013 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1014 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1015 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1016 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1017 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1018 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1019 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1020 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1021 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1022 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1023 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1024 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1025 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1026 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1027 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1028 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1029 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1030 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1031 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1032 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1033 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1034 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1035 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1036 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1037 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1038 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1039 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1040 }; 1041 1042 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1043 struct mv88e6xxx_hw_stat *s, 1044 int port, u16 bank1_select, 1045 u16 histogram) 1046 { 1047 u32 low; 1048 u32 high = 0; 1049 u16 reg = 0; 1050 int err; 1051 u64 value; 1052 1053 switch (s->type) { 1054 case STATS_TYPE_PORT: 1055 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1056 if (err) 1057 return U64_MAX; 1058 1059 low = reg; 1060 if (s->size == 4) { 1061 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1062 if (err) 1063 return U64_MAX; 1064 low |= ((u32)reg) << 16; 1065 } 1066 break; 1067 case STATS_TYPE_BANK1: 1068 reg = bank1_select; 1069 fallthrough; 1070 case STATS_TYPE_BANK0: 1071 reg |= s->reg | histogram; 1072 mv88e6xxx_g1_stats_read(chip, reg, &low); 1073 if (s->size == 8) 1074 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1075 break; 1076 default: 1077 return U64_MAX; 1078 } 1079 value = (((u64)high) << 32) | low; 1080 return value; 1081 } 1082 1083 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1084 uint8_t *data, int types) 1085 { 1086 struct mv88e6xxx_hw_stat *stat; 1087 int i, j; 1088 1089 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1090 stat = &mv88e6xxx_hw_stats[i]; 1091 if (stat->type & types) { 1092 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1093 ETH_GSTRING_LEN); 1094 j++; 1095 } 1096 } 1097 1098 return j; 1099 } 1100 1101 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1102 uint8_t *data) 1103 { 1104 return mv88e6xxx_stats_get_strings(chip, data, 1105 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1106 } 1107 1108 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1109 uint8_t *data) 1110 { 1111 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1112 } 1113 1114 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1115 uint8_t *data) 1116 { 1117 return mv88e6xxx_stats_get_strings(chip, data, 1118 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1119 } 1120 1121 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1122 "atu_member_violation", 1123 "atu_miss_violation", 1124 "atu_full_violation", 1125 "vtu_member_violation", 1126 "vtu_miss_violation", 1127 }; 1128 1129 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1130 { 1131 unsigned int i; 1132 1133 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1134 strlcpy(data + i * ETH_GSTRING_LEN, 1135 mv88e6xxx_atu_vtu_stats_strings[i], 1136 ETH_GSTRING_LEN); 1137 } 1138 1139 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1140 u32 stringset, uint8_t *data) 1141 { 1142 struct mv88e6xxx_chip *chip = ds->priv; 1143 int count = 0; 1144 1145 if (stringset != ETH_SS_STATS) 1146 return; 1147 1148 mv88e6xxx_reg_lock(chip); 1149 1150 if (chip->info->ops->stats_get_strings) 1151 count = chip->info->ops->stats_get_strings(chip, data); 1152 1153 if (chip->info->ops->serdes_get_strings) { 1154 data += count * ETH_GSTRING_LEN; 1155 count = chip->info->ops->serdes_get_strings(chip, port, data); 1156 } 1157 1158 data += count * ETH_GSTRING_LEN; 1159 mv88e6xxx_atu_vtu_get_strings(data); 1160 1161 mv88e6xxx_reg_unlock(chip); 1162 } 1163 1164 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1165 int types) 1166 { 1167 struct mv88e6xxx_hw_stat *stat; 1168 int i, j; 1169 1170 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1171 stat = &mv88e6xxx_hw_stats[i]; 1172 if (stat->type & types) 1173 j++; 1174 } 1175 return j; 1176 } 1177 1178 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1179 { 1180 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1181 STATS_TYPE_PORT); 1182 } 1183 1184 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1185 { 1186 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1187 } 1188 1189 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1190 { 1191 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1192 STATS_TYPE_BANK1); 1193 } 1194 1195 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1196 { 1197 struct mv88e6xxx_chip *chip = ds->priv; 1198 int serdes_count = 0; 1199 int count = 0; 1200 1201 if (sset != ETH_SS_STATS) 1202 return 0; 1203 1204 mv88e6xxx_reg_lock(chip); 1205 if (chip->info->ops->stats_get_sset_count) 1206 count = chip->info->ops->stats_get_sset_count(chip); 1207 if (count < 0) 1208 goto out; 1209 1210 if (chip->info->ops->serdes_get_sset_count) 1211 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1212 port); 1213 if (serdes_count < 0) { 1214 count = serdes_count; 1215 goto out; 1216 } 1217 count += serdes_count; 1218 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1219 1220 out: 1221 mv88e6xxx_reg_unlock(chip); 1222 1223 return count; 1224 } 1225 1226 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1227 uint64_t *data, int types, 1228 u16 bank1_select, u16 histogram) 1229 { 1230 struct mv88e6xxx_hw_stat *stat; 1231 int i, j; 1232 1233 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1234 stat = &mv88e6xxx_hw_stats[i]; 1235 if (stat->type & types) { 1236 mv88e6xxx_reg_lock(chip); 1237 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1238 bank1_select, 1239 histogram); 1240 mv88e6xxx_reg_unlock(chip); 1241 1242 j++; 1243 } 1244 } 1245 return j; 1246 } 1247 1248 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1249 uint64_t *data) 1250 { 1251 return mv88e6xxx_stats_get_stats(chip, port, data, 1252 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1253 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1254 } 1255 1256 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1257 uint64_t *data) 1258 { 1259 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1261 } 1262 1263 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1264 uint64_t *data) 1265 { 1266 return mv88e6xxx_stats_get_stats(chip, port, data, 1267 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1268 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1269 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1270 } 1271 1272 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1273 uint64_t *data) 1274 { 1275 return mv88e6xxx_stats_get_stats(chip, port, data, 1276 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1277 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1278 0); 1279 } 1280 1281 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1282 uint64_t *data) 1283 { 1284 *data++ = chip->ports[port].atu_member_violation; 1285 *data++ = chip->ports[port].atu_miss_violation; 1286 *data++ = chip->ports[port].atu_full_violation; 1287 *data++ = chip->ports[port].vtu_member_violation; 1288 *data++ = chip->ports[port].vtu_miss_violation; 1289 } 1290 1291 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1292 uint64_t *data) 1293 { 1294 int count = 0; 1295 1296 if (chip->info->ops->stats_get_stats) 1297 count = chip->info->ops->stats_get_stats(chip, port, data); 1298 1299 mv88e6xxx_reg_lock(chip); 1300 if (chip->info->ops->serdes_get_stats) { 1301 data += count; 1302 count = chip->info->ops->serdes_get_stats(chip, port, data); 1303 } 1304 data += count; 1305 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1306 mv88e6xxx_reg_unlock(chip); 1307 } 1308 1309 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1310 uint64_t *data) 1311 { 1312 struct mv88e6xxx_chip *chip = ds->priv; 1313 int ret; 1314 1315 mv88e6xxx_reg_lock(chip); 1316 1317 ret = mv88e6xxx_stats_snapshot(chip, port); 1318 mv88e6xxx_reg_unlock(chip); 1319 1320 if (ret < 0) 1321 return; 1322 1323 mv88e6xxx_get_stats(chip, port, data); 1324 1325 } 1326 1327 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1328 { 1329 struct mv88e6xxx_chip *chip = ds->priv; 1330 int len; 1331 1332 len = 32 * sizeof(u16); 1333 if (chip->info->ops->serdes_get_regs_len) 1334 len += chip->info->ops->serdes_get_regs_len(chip, port); 1335 1336 return len; 1337 } 1338 1339 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1340 struct ethtool_regs *regs, void *_p) 1341 { 1342 struct mv88e6xxx_chip *chip = ds->priv; 1343 int err; 1344 u16 reg; 1345 u16 *p = _p; 1346 int i; 1347 1348 regs->version = chip->info->prod_num; 1349 1350 memset(p, 0xff, 32 * sizeof(u16)); 1351 1352 mv88e6xxx_reg_lock(chip); 1353 1354 for (i = 0; i < 32; i++) { 1355 1356 err = mv88e6xxx_port_read(chip, port, i, ®); 1357 if (!err) 1358 p[i] = reg; 1359 } 1360 1361 if (chip->info->ops->serdes_get_regs) 1362 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1363 1364 mv88e6xxx_reg_unlock(chip); 1365 } 1366 1367 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1368 struct ethtool_eee *e) 1369 { 1370 /* Nothing to do on the port's MAC */ 1371 return 0; 1372 } 1373 1374 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1375 struct ethtool_eee *e) 1376 { 1377 /* Nothing to do on the port's MAC */ 1378 return 0; 1379 } 1380 1381 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1382 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1383 { 1384 struct dsa_switch *ds = chip->ds; 1385 struct dsa_switch_tree *dst = ds->dst; 1386 struct dsa_port *dp, *other_dp; 1387 bool found = false; 1388 u16 pvlan; 1389 1390 /* dev is a physical switch */ 1391 if (dev <= dst->last_switch) { 1392 list_for_each_entry(dp, &dst->ports, list) { 1393 if (dp->ds->index == dev && dp->index == port) { 1394 /* dp might be a DSA link or a user port, so it 1395 * might or might not have a bridge. 1396 * Use the "found" variable for both cases. 1397 */ 1398 found = true; 1399 break; 1400 } 1401 } 1402 /* dev is a virtual bridge */ 1403 } else { 1404 list_for_each_entry(dp, &dst->ports, list) { 1405 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1406 1407 if (!bridge_num) 1408 continue; 1409 1410 if (bridge_num + dst->last_switch != dev) 1411 continue; 1412 1413 found = true; 1414 break; 1415 } 1416 } 1417 1418 /* Prevent frames from unknown switch or virtual bridge */ 1419 if (!found) 1420 return 0; 1421 1422 /* Frames from DSA links and CPU ports can egress any local port */ 1423 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1424 return mv88e6xxx_port_mask(chip); 1425 1426 pvlan = 0; 1427 1428 /* Frames from standalone user ports can only egress on the 1429 * upstream port. 1430 */ 1431 if (!dsa_port_bridge_dev_get(dp)) 1432 return BIT(dsa_switch_upstream_port(ds)); 1433 1434 /* Frames from bridged user ports can egress any local DSA 1435 * links and CPU ports, as well as any local member of their 1436 * bridge group. 1437 */ 1438 dsa_switch_for_each_port(other_dp, ds) 1439 if (other_dp->type == DSA_PORT_TYPE_CPU || 1440 other_dp->type == DSA_PORT_TYPE_DSA || 1441 dsa_port_bridge_same(dp, other_dp)) 1442 pvlan |= BIT(other_dp->index); 1443 1444 return pvlan; 1445 } 1446 1447 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1448 { 1449 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1450 1451 /* prevent frames from going back out of the port they came in on */ 1452 output_ports &= ~BIT(port); 1453 1454 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1455 } 1456 1457 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1458 u8 state) 1459 { 1460 struct mv88e6xxx_chip *chip = ds->priv; 1461 int err; 1462 1463 mv88e6xxx_reg_lock(chip); 1464 err = mv88e6xxx_port_set_state(chip, port, state); 1465 mv88e6xxx_reg_unlock(chip); 1466 1467 if (err) 1468 dev_err(ds->dev, "p%d: failed to update state\n", port); 1469 } 1470 1471 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1472 { 1473 int err; 1474 1475 if (chip->info->ops->ieee_pri_map) { 1476 err = chip->info->ops->ieee_pri_map(chip); 1477 if (err) 1478 return err; 1479 } 1480 1481 if (chip->info->ops->ip_pri_map) { 1482 err = chip->info->ops->ip_pri_map(chip); 1483 if (err) 1484 return err; 1485 } 1486 1487 return 0; 1488 } 1489 1490 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1491 { 1492 struct dsa_switch *ds = chip->ds; 1493 int target, port; 1494 int err; 1495 1496 if (!chip->info->global2_addr) 1497 return 0; 1498 1499 /* Initialize the routing port to the 32 possible target devices */ 1500 for (target = 0; target < 32; target++) { 1501 port = dsa_routing_port(ds, target); 1502 if (port == ds->num_ports) 1503 port = 0x1f; 1504 1505 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1506 if (err) 1507 return err; 1508 } 1509 1510 if (chip->info->ops->set_cascade_port) { 1511 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1512 err = chip->info->ops->set_cascade_port(chip, port); 1513 if (err) 1514 return err; 1515 } 1516 1517 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1518 if (err) 1519 return err; 1520 1521 return 0; 1522 } 1523 1524 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1525 { 1526 /* Clear all trunk masks and mapping */ 1527 if (chip->info->global2_addr) 1528 return mv88e6xxx_g2_trunk_clear(chip); 1529 1530 return 0; 1531 } 1532 1533 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1534 { 1535 if (chip->info->ops->rmu_disable) 1536 return chip->info->ops->rmu_disable(chip); 1537 1538 return 0; 1539 } 1540 1541 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1542 { 1543 if (chip->info->ops->pot_clear) 1544 return chip->info->ops->pot_clear(chip); 1545 1546 return 0; 1547 } 1548 1549 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1550 { 1551 if (chip->info->ops->mgmt_rsvd2cpu) 1552 return chip->info->ops->mgmt_rsvd2cpu(chip); 1553 1554 return 0; 1555 } 1556 1557 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1558 { 1559 int err; 1560 1561 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1562 if (err) 1563 return err; 1564 1565 /* The chips that have a "learn2all" bit in Global1, ATU 1566 * Control are precisely those whose port registers have a 1567 * Message Port bit in Port Control 1 and hence implement 1568 * ->port_setup_message_port. 1569 */ 1570 if (chip->info->ops->port_setup_message_port) { 1571 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1572 if (err) 1573 return err; 1574 } 1575 1576 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1577 } 1578 1579 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1580 { 1581 int port; 1582 int err; 1583 1584 if (!chip->info->ops->irl_init_all) 1585 return 0; 1586 1587 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1588 /* Disable ingress rate limiting by resetting all per port 1589 * ingress rate limit resources to their initial state. 1590 */ 1591 err = chip->info->ops->irl_init_all(chip, port); 1592 if (err) 1593 return err; 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1600 { 1601 if (chip->info->ops->set_switch_mac) { 1602 u8 addr[ETH_ALEN]; 1603 1604 eth_random_addr(addr); 1605 1606 return chip->info->ops->set_switch_mac(chip, addr); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1613 { 1614 struct dsa_switch_tree *dst = chip->ds->dst; 1615 struct dsa_switch *ds; 1616 struct dsa_port *dp; 1617 u16 pvlan = 0; 1618 1619 if (!mv88e6xxx_has_pvt(chip)) 1620 return 0; 1621 1622 /* Skip the local source device, which uses in-chip port VLAN */ 1623 if (dev != chip->ds->index) { 1624 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1625 1626 ds = dsa_switch_find(dst->index, dev); 1627 dp = ds ? dsa_to_port(ds, port) : NULL; 1628 if (dp && dp->lag) { 1629 /* As the PVT is used to limit flooding of 1630 * FORWARD frames, which use the LAG ID as the 1631 * source port, we must translate dev/port to 1632 * the special "LAG device" in the PVT, using 1633 * the LAG ID (one-based) as the port number 1634 * (zero-based). 1635 */ 1636 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1637 port = dsa_port_lag_id_get(dp) - 1; 1638 } 1639 } 1640 1641 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1642 } 1643 1644 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1645 { 1646 int dev, port; 1647 int err; 1648 1649 if (!mv88e6xxx_has_pvt(chip)) 1650 return 0; 1651 1652 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1653 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1654 */ 1655 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1656 if (err) 1657 return err; 1658 1659 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1660 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1661 err = mv88e6xxx_pvt_map(chip, dev, port); 1662 if (err) 1663 return err; 1664 } 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1671 u16 fid) 1672 { 1673 if (dsa_to_port(chip->ds, port)->lag) 1674 /* Hardware is incapable of fast-aging a LAG through a 1675 * regular ATU move operation. Until we have something 1676 * more fancy in place this is a no-op. 1677 */ 1678 return -EOPNOTSUPP; 1679 1680 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1681 } 1682 1683 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1684 { 1685 struct mv88e6xxx_chip *chip = ds->priv; 1686 int err; 1687 1688 mv88e6xxx_reg_lock(chip); 1689 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1690 mv88e6xxx_reg_unlock(chip); 1691 1692 if (err) 1693 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1694 port, err); 1695 } 1696 1697 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1698 { 1699 if (!mv88e6xxx_max_vid(chip)) 1700 return 0; 1701 1702 return mv88e6xxx_g1_vtu_flush(chip); 1703 } 1704 1705 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1706 struct mv88e6xxx_vtu_entry *entry) 1707 { 1708 int err; 1709 1710 if (!chip->info->ops->vtu_getnext) 1711 return -EOPNOTSUPP; 1712 1713 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1714 entry->valid = false; 1715 1716 err = chip->info->ops->vtu_getnext(chip, entry); 1717 1718 if (entry->vid != vid) 1719 entry->valid = false; 1720 1721 return err; 1722 } 1723 1724 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1725 int (*cb)(struct mv88e6xxx_chip *chip, 1726 const struct mv88e6xxx_vtu_entry *entry, 1727 void *priv), 1728 void *priv) 1729 { 1730 struct mv88e6xxx_vtu_entry entry = { 1731 .vid = mv88e6xxx_max_vid(chip), 1732 .valid = false, 1733 }; 1734 int err; 1735 1736 if (!chip->info->ops->vtu_getnext) 1737 return -EOPNOTSUPP; 1738 1739 do { 1740 err = chip->info->ops->vtu_getnext(chip, &entry); 1741 if (err) 1742 return err; 1743 1744 if (!entry.valid) 1745 break; 1746 1747 err = cb(chip, &entry, priv); 1748 if (err) 1749 return err; 1750 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1751 1752 return 0; 1753 } 1754 1755 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1756 struct mv88e6xxx_vtu_entry *entry) 1757 { 1758 if (!chip->info->ops->vtu_loadpurge) 1759 return -EOPNOTSUPP; 1760 1761 return chip->info->ops->vtu_loadpurge(chip, entry); 1762 } 1763 1764 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1765 const struct mv88e6xxx_vtu_entry *entry, 1766 void *_fid_bitmap) 1767 { 1768 unsigned long *fid_bitmap = _fid_bitmap; 1769 1770 set_bit(entry->fid, fid_bitmap); 1771 return 0; 1772 } 1773 1774 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1775 { 1776 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1777 1778 /* Every FID has an associated VID, so walking the VTU 1779 * will discover the full set of FIDs in use. 1780 */ 1781 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1782 } 1783 1784 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1785 { 1786 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1787 int err; 1788 1789 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1790 if (err) 1791 return err; 1792 1793 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1794 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1795 return -ENOSPC; 1796 1797 /* Clear the database */ 1798 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1799 } 1800 1801 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1802 struct mv88e6xxx_stu_entry *entry) 1803 { 1804 if (!chip->info->ops->stu_loadpurge) 1805 return -EOPNOTSUPP; 1806 1807 return chip->info->ops->stu_loadpurge(chip, entry); 1808 } 1809 1810 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1811 { 1812 struct mv88e6xxx_stu_entry stu = { 1813 .valid = true, 1814 .sid = 0 1815 }; 1816 1817 if (!mv88e6xxx_has_stu(chip)) 1818 return 0; 1819 1820 /* Make sure that SID 0 is always valid. This is used by VTU 1821 * entries that do not make use of the STU, e.g. when creating 1822 * a VLAN upper on a port that is also part of a VLAN 1823 * filtering bridge. 1824 */ 1825 return mv88e6xxx_stu_loadpurge(chip, &stu); 1826 } 1827 1828 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1829 { 1830 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1831 struct mv88e6xxx_mst *mst; 1832 1833 __set_bit(0, busy); 1834 1835 list_for_each_entry(mst, &chip->msts, node) 1836 __set_bit(mst->stu.sid, busy); 1837 1838 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1839 1840 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1841 } 1842 1843 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1844 { 1845 struct mv88e6xxx_mst *mst, *tmp; 1846 int err; 1847 1848 if (!sid) 1849 return 0; 1850 1851 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1852 if (mst->stu.sid != sid) 1853 continue; 1854 1855 if (!refcount_dec_and_test(&mst->refcnt)) 1856 return 0; 1857 1858 mst->stu.valid = false; 1859 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1860 if (err) { 1861 refcount_set(&mst->refcnt, 1); 1862 return err; 1863 } 1864 1865 list_del(&mst->node); 1866 kfree(mst); 1867 return 0; 1868 } 1869 1870 return -ENOENT; 1871 } 1872 1873 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1874 u16 msti, u8 *sid) 1875 { 1876 struct mv88e6xxx_mst *mst; 1877 int err, i; 1878 1879 if (!mv88e6xxx_has_stu(chip)) { 1880 err = -EOPNOTSUPP; 1881 goto err; 1882 } 1883 1884 if (!msti) { 1885 *sid = 0; 1886 return 0; 1887 } 1888 1889 list_for_each_entry(mst, &chip->msts, node) { 1890 if (mst->br == br && mst->msti == msti) { 1891 refcount_inc(&mst->refcnt); 1892 *sid = mst->stu.sid; 1893 return 0; 1894 } 1895 } 1896 1897 err = mv88e6xxx_sid_get(chip, sid); 1898 if (err) 1899 goto err; 1900 1901 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1902 if (!mst) { 1903 err = -ENOMEM; 1904 goto err; 1905 } 1906 1907 INIT_LIST_HEAD(&mst->node); 1908 refcount_set(&mst->refcnt, 1); 1909 mst->br = br; 1910 mst->msti = msti; 1911 mst->stu.valid = true; 1912 mst->stu.sid = *sid; 1913 1914 /* The bridge starts out all ports in the disabled state. But 1915 * a STU state of disabled means to go by the port-global 1916 * state. So we set all user port's initial state to blocking, 1917 * to match the bridge's behavior. 1918 */ 1919 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1920 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1921 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1922 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1923 1924 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1925 if (err) 1926 goto err_free; 1927 1928 list_add_tail(&mst->node, &chip->msts); 1929 return 0; 1930 1931 err_free: 1932 kfree(mst); 1933 err: 1934 return err; 1935 } 1936 1937 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1938 const struct switchdev_mst_state *st) 1939 { 1940 struct dsa_port *dp = dsa_to_port(ds, port); 1941 struct mv88e6xxx_chip *chip = ds->priv; 1942 struct mv88e6xxx_mst *mst; 1943 u8 state; 1944 int err; 1945 1946 if (!mv88e6xxx_has_stu(chip)) 1947 return -EOPNOTSUPP; 1948 1949 switch (st->state) { 1950 case BR_STATE_DISABLED: 1951 case BR_STATE_BLOCKING: 1952 case BR_STATE_LISTENING: 1953 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1954 break; 1955 case BR_STATE_LEARNING: 1956 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1957 break; 1958 case BR_STATE_FORWARDING: 1959 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1960 break; 1961 default: 1962 return -EINVAL; 1963 } 1964 1965 list_for_each_entry(mst, &chip->msts, node) { 1966 if (mst->br == dsa_port_bridge_dev_get(dp) && 1967 mst->msti == st->msti) { 1968 if (mst->stu.state[port] == state) 1969 return 0; 1970 1971 mst->stu.state[port] = state; 1972 mv88e6xxx_reg_lock(chip); 1973 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1974 mv88e6xxx_reg_unlock(chip); 1975 return err; 1976 } 1977 } 1978 1979 return -ENOENT; 1980 } 1981 1982 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1983 u16 vid) 1984 { 1985 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1986 struct mv88e6xxx_chip *chip = ds->priv; 1987 struct mv88e6xxx_vtu_entry vlan; 1988 int err; 1989 1990 /* DSA and CPU ports have to be members of multiple vlans */ 1991 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1992 return 0; 1993 1994 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1995 if (err) 1996 return err; 1997 1998 if (!vlan.valid) 1999 return 0; 2000 2001 dsa_switch_for_each_user_port(other_dp, ds) { 2002 struct net_device *other_br; 2003 2004 if (vlan.member[other_dp->index] == 2005 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2006 continue; 2007 2008 if (dsa_port_bridge_same(dp, other_dp)) 2009 break; /* same bridge, check next VLAN */ 2010 2011 other_br = dsa_port_bridge_dev_get(other_dp); 2012 if (!other_br) 2013 continue; 2014 2015 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2016 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2017 return -EOPNOTSUPP; 2018 } 2019 2020 return 0; 2021 } 2022 2023 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2024 { 2025 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2026 struct net_device *br = dsa_port_bridge_dev_get(dp); 2027 struct mv88e6xxx_port *p = &chip->ports[port]; 2028 u16 pvid = MV88E6XXX_VID_STANDALONE; 2029 bool drop_untagged = false; 2030 int err; 2031 2032 if (br) { 2033 if (br_vlan_enabled(br)) { 2034 pvid = p->bridge_pvid.vid; 2035 drop_untagged = !p->bridge_pvid.valid; 2036 } else { 2037 pvid = MV88E6XXX_VID_BRIDGED; 2038 } 2039 } 2040 2041 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2042 if (err) 2043 return err; 2044 2045 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2046 } 2047 2048 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2049 bool vlan_filtering, 2050 struct netlink_ext_ack *extack) 2051 { 2052 struct mv88e6xxx_chip *chip = ds->priv; 2053 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2054 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2055 int err; 2056 2057 if (!mv88e6xxx_max_vid(chip)) 2058 return -EOPNOTSUPP; 2059 2060 mv88e6xxx_reg_lock(chip); 2061 2062 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2063 if (err) 2064 goto unlock; 2065 2066 err = mv88e6xxx_port_commit_pvid(chip, port); 2067 if (err) 2068 goto unlock; 2069 2070 unlock: 2071 mv88e6xxx_reg_unlock(chip); 2072 2073 return err; 2074 } 2075 2076 static int 2077 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2078 const struct switchdev_obj_port_vlan *vlan) 2079 { 2080 struct mv88e6xxx_chip *chip = ds->priv; 2081 int err; 2082 2083 if (!mv88e6xxx_max_vid(chip)) 2084 return -EOPNOTSUPP; 2085 2086 /* If the requested port doesn't belong to the same bridge as the VLAN 2087 * members, do not support it (yet) and fallback to software VLAN. 2088 */ 2089 mv88e6xxx_reg_lock(chip); 2090 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2091 mv88e6xxx_reg_unlock(chip); 2092 2093 return err; 2094 } 2095 2096 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2097 const unsigned char *addr, u16 vid, 2098 u8 state) 2099 { 2100 struct mv88e6xxx_atu_entry entry; 2101 struct mv88e6xxx_vtu_entry vlan; 2102 u16 fid; 2103 int err; 2104 2105 /* Ports have two private address databases: one for when the port is 2106 * standalone and one for when the port is under a bridge and the 2107 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2108 * address database to remain 100% empty, so we never load an ATU entry 2109 * into a standalone port's database. Therefore, translate the null 2110 * VLAN ID into the port's database used for VLAN-unaware bridging. 2111 */ 2112 if (vid == 0) { 2113 fid = MV88E6XXX_FID_BRIDGED; 2114 } else { 2115 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2116 if (err) 2117 return err; 2118 2119 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2120 if (!vlan.valid) 2121 return -EOPNOTSUPP; 2122 2123 fid = vlan.fid; 2124 } 2125 2126 entry.state = 0; 2127 ether_addr_copy(entry.mac, addr); 2128 eth_addr_dec(entry.mac); 2129 2130 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2131 if (err) 2132 return err; 2133 2134 /* Initialize a fresh ATU entry if it isn't found */ 2135 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2136 memset(&entry, 0, sizeof(entry)); 2137 ether_addr_copy(entry.mac, addr); 2138 } 2139 2140 /* Purge the ATU entry only if no port is using it anymore */ 2141 if (!state) { 2142 entry.portvec &= ~BIT(port); 2143 if (!entry.portvec) 2144 entry.state = 0; 2145 } else { 2146 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2147 entry.portvec = BIT(port); 2148 else 2149 entry.portvec |= BIT(port); 2150 2151 entry.state = state; 2152 } 2153 2154 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2155 } 2156 2157 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2158 const struct mv88e6xxx_policy *policy) 2159 { 2160 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2161 enum mv88e6xxx_policy_action action = policy->action; 2162 const u8 *addr = policy->addr; 2163 u16 vid = policy->vid; 2164 u8 state; 2165 int err; 2166 int id; 2167 2168 if (!chip->info->ops->port_set_policy) 2169 return -EOPNOTSUPP; 2170 2171 switch (mapping) { 2172 case MV88E6XXX_POLICY_MAPPING_DA: 2173 case MV88E6XXX_POLICY_MAPPING_SA: 2174 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2175 state = 0; /* Dissociate the port and address */ 2176 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2177 is_multicast_ether_addr(addr)) 2178 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2179 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2180 is_unicast_ether_addr(addr)) 2181 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2182 else 2183 return -EOPNOTSUPP; 2184 2185 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2186 state); 2187 if (err) 2188 return err; 2189 break; 2190 default: 2191 return -EOPNOTSUPP; 2192 } 2193 2194 /* Skip the port's policy clearing if the mapping is still in use */ 2195 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2196 idr_for_each_entry(&chip->policies, policy, id) 2197 if (policy->port == port && 2198 policy->mapping == mapping && 2199 policy->action != action) 2200 return 0; 2201 2202 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2203 } 2204 2205 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2206 struct ethtool_rx_flow_spec *fs) 2207 { 2208 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2209 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2210 enum mv88e6xxx_policy_mapping mapping; 2211 enum mv88e6xxx_policy_action action; 2212 struct mv88e6xxx_policy *policy; 2213 u16 vid = 0; 2214 u8 *addr; 2215 int err; 2216 int id; 2217 2218 if (fs->location != RX_CLS_LOC_ANY) 2219 return -EINVAL; 2220 2221 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2222 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2223 else 2224 return -EOPNOTSUPP; 2225 2226 switch (fs->flow_type & ~FLOW_EXT) { 2227 case ETHER_FLOW: 2228 if (!is_zero_ether_addr(mac_mask->h_dest) && 2229 is_zero_ether_addr(mac_mask->h_source)) { 2230 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2231 addr = mac_entry->h_dest; 2232 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2233 !is_zero_ether_addr(mac_mask->h_source)) { 2234 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2235 addr = mac_entry->h_source; 2236 } else { 2237 /* Cannot support DA and SA mapping in the same rule */ 2238 return -EOPNOTSUPP; 2239 } 2240 break; 2241 default: 2242 return -EOPNOTSUPP; 2243 } 2244 2245 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2246 if (fs->m_ext.vlan_tci != htons(0xffff)) 2247 return -EOPNOTSUPP; 2248 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2249 } 2250 2251 idr_for_each_entry(&chip->policies, policy, id) { 2252 if (policy->port == port && policy->mapping == mapping && 2253 policy->action == action && policy->vid == vid && 2254 ether_addr_equal(policy->addr, addr)) 2255 return -EEXIST; 2256 } 2257 2258 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2259 if (!policy) 2260 return -ENOMEM; 2261 2262 fs->location = 0; 2263 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2264 GFP_KERNEL); 2265 if (err) { 2266 devm_kfree(chip->dev, policy); 2267 return err; 2268 } 2269 2270 memcpy(&policy->fs, fs, sizeof(*fs)); 2271 ether_addr_copy(policy->addr, addr); 2272 policy->mapping = mapping; 2273 policy->action = action; 2274 policy->port = port; 2275 policy->vid = vid; 2276 2277 err = mv88e6xxx_policy_apply(chip, port, policy); 2278 if (err) { 2279 idr_remove(&chip->policies, fs->location); 2280 devm_kfree(chip->dev, policy); 2281 return err; 2282 } 2283 2284 return 0; 2285 } 2286 2287 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2288 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2289 { 2290 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2291 struct mv88e6xxx_chip *chip = ds->priv; 2292 struct mv88e6xxx_policy *policy; 2293 int err; 2294 int id; 2295 2296 mv88e6xxx_reg_lock(chip); 2297 2298 switch (rxnfc->cmd) { 2299 case ETHTOOL_GRXCLSRLCNT: 2300 rxnfc->data = 0; 2301 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2302 rxnfc->rule_cnt = 0; 2303 idr_for_each_entry(&chip->policies, policy, id) 2304 if (policy->port == port) 2305 rxnfc->rule_cnt++; 2306 err = 0; 2307 break; 2308 case ETHTOOL_GRXCLSRULE: 2309 err = -ENOENT; 2310 policy = idr_find(&chip->policies, fs->location); 2311 if (policy) { 2312 memcpy(fs, &policy->fs, sizeof(*fs)); 2313 err = 0; 2314 } 2315 break; 2316 case ETHTOOL_GRXCLSRLALL: 2317 rxnfc->data = 0; 2318 rxnfc->rule_cnt = 0; 2319 idr_for_each_entry(&chip->policies, policy, id) 2320 if (policy->port == port) 2321 rule_locs[rxnfc->rule_cnt++] = id; 2322 err = 0; 2323 break; 2324 default: 2325 err = -EOPNOTSUPP; 2326 break; 2327 } 2328 2329 mv88e6xxx_reg_unlock(chip); 2330 2331 return err; 2332 } 2333 2334 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2335 struct ethtool_rxnfc *rxnfc) 2336 { 2337 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2338 struct mv88e6xxx_chip *chip = ds->priv; 2339 struct mv88e6xxx_policy *policy; 2340 int err; 2341 2342 mv88e6xxx_reg_lock(chip); 2343 2344 switch (rxnfc->cmd) { 2345 case ETHTOOL_SRXCLSRLINS: 2346 err = mv88e6xxx_policy_insert(chip, port, fs); 2347 break; 2348 case ETHTOOL_SRXCLSRLDEL: 2349 err = -ENOENT; 2350 policy = idr_remove(&chip->policies, fs->location); 2351 if (policy) { 2352 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2353 err = mv88e6xxx_policy_apply(chip, port, policy); 2354 devm_kfree(chip->dev, policy); 2355 } 2356 break; 2357 default: 2358 err = -EOPNOTSUPP; 2359 break; 2360 } 2361 2362 mv88e6xxx_reg_unlock(chip); 2363 2364 return err; 2365 } 2366 2367 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2368 u16 vid) 2369 { 2370 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2371 u8 broadcast[ETH_ALEN]; 2372 2373 eth_broadcast_addr(broadcast); 2374 2375 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2376 } 2377 2378 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2379 { 2380 int port; 2381 int err; 2382 2383 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2384 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2385 struct net_device *brport; 2386 2387 if (dsa_is_unused_port(chip->ds, port)) 2388 continue; 2389 2390 brport = dsa_port_to_bridge_port(dp); 2391 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2392 /* Skip bridged user ports where broadcast 2393 * flooding is disabled. 2394 */ 2395 continue; 2396 2397 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2398 if (err) 2399 return err; 2400 } 2401 2402 return 0; 2403 } 2404 2405 struct mv88e6xxx_port_broadcast_sync_ctx { 2406 int port; 2407 bool flood; 2408 }; 2409 2410 static int 2411 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2412 const struct mv88e6xxx_vtu_entry *vlan, 2413 void *_ctx) 2414 { 2415 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2416 u8 broadcast[ETH_ALEN]; 2417 u8 state; 2418 2419 if (ctx->flood) 2420 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2421 else 2422 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2423 2424 eth_broadcast_addr(broadcast); 2425 2426 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2427 vlan->vid, state); 2428 } 2429 2430 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2431 bool flood) 2432 { 2433 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2434 .port = port, 2435 .flood = flood, 2436 }; 2437 struct mv88e6xxx_vtu_entry vid0 = { 2438 .vid = 0, 2439 }; 2440 int err; 2441 2442 /* Update the port's private database... */ 2443 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2444 if (err) 2445 return err; 2446 2447 /* ...and the database for all VLANs. */ 2448 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2449 &ctx); 2450 } 2451 2452 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2453 u16 vid, u8 member, bool warn) 2454 { 2455 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2456 struct mv88e6xxx_vtu_entry vlan; 2457 int i, err; 2458 2459 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2460 if (err) 2461 return err; 2462 2463 if (!vlan.valid) { 2464 memset(&vlan, 0, sizeof(vlan)); 2465 2466 if (vid == MV88E6XXX_VID_STANDALONE) 2467 vlan.policy = true; 2468 2469 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2470 if (err) 2471 return err; 2472 2473 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2474 if (i == port) 2475 vlan.member[i] = member; 2476 else 2477 vlan.member[i] = non_member; 2478 2479 vlan.vid = vid; 2480 vlan.valid = true; 2481 2482 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2483 if (err) 2484 return err; 2485 2486 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2487 if (err) 2488 return err; 2489 } else if (vlan.member[port] != member) { 2490 vlan.member[port] = member; 2491 2492 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2493 if (err) 2494 return err; 2495 } else if (warn) { 2496 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2497 port, vid); 2498 } 2499 2500 return 0; 2501 } 2502 2503 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2504 const struct switchdev_obj_port_vlan *vlan, 2505 struct netlink_ext_ack *extack) 2506 { 2507 struct mv88e6xxx_chip *chip = ds->priv; 2508 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2509 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2510 struct mv88e6xxx_port *p = &chip->ports[port]; 2511 bool warn; 2512 u8 member; 2513 int err; 2514 2515 if (!vlan->vid) 2516 return 0; 2517 2518 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2519 if (err) 2520 return err; 2521 2522 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2523 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2524 else if (untagged) 2525 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2526 else 2527 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2528 2529 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2530 * and then the CPU port. Do not warn for duplicates for the CPU port. 2531 */ 2532 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2533 2534 mv88e6xxx_reg_lock(chip); 2535 2536 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2537 if (err) { 2538 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2539 vlan->vid, untagged ? 'u' : 't'); 2540 goto out; 2541 } 2542 2543 if (pvid) { 2544 p->bridge_pvid.vid = vlan->vid; 2545 p->bridge_pvid.valid = true; 2546 2547 err = mv88e6xxx_port_commit_pvid(chip, port); 2548 if (err) 2549 goto out; 2550 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2551 /* The old pvid was reinstalled as a non-pvid VLAN */ 2552 p->bridge_pvid.valid = false; 2553 2554 err = mv88e6xxx_port_commit_pvid(chip, port); 2555 if (err) 2556 goto out; 2557 } 2558 2559 out: 2560 mv88e6xxx_reg_unlock(chip); 2561 2562 return err; 2563 } 2564 2565 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2566 int port, u16 vid) 2567 { 2568 struct mv88e6xxx_vtu_entry vlan; 2569 int i, err; 2570 2571 if (!vid) 2572 return 0; 2573 2574 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2575 if (err) 2576 return err; 2577 2578 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2579 * tell switchdev that this VLAN is likely handled in software. 2580 */ 2581 if (!vlan.valid || 2582 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2583 return -EOPNOTSUPP; 2584 2585 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2586 2587 /* keep the VLAN unless all ports are excluded */ 2588 vlan.valid = false; 2589 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2590 if (vlan.member[i] != 2591 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2592 vlan.valid = true; 2593 break; 2594 } 2595 } 2596 2597 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2598 if (err) 2599 return err; 2600 2601 if (!vlan.valid) { 2602 err = mv88e6xxx_mst_put(chip, vlan.sid); 2603 if (err) 2604 return err; 2605 } 2606 2607 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2608 } 2609 2610 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2611 const struct switchdev_obj_port_vlan *vlan) 2612 { 2613 struct mv88e6xxx_chip *chip = ds->priv; 2614 struct mv88e6xxx_port *p = &chip->ports[port]; 2615 int err = 0; 2616 u16 pvid; 2617 2618 if (!mv88e6xxx_max_vid(chip)) 2619 return -EOPNOTSUPP; 2620 2621 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2622 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2623 * switchdev workqueue to ensure that all FDB entries are deleted 2624 * before we remove the VLAN. 2625 */ 2626 dsa_flush_workqueue(); 2627 2628 mv88e6xxx_reg_lock(chip); 2629 2630 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2631 if (err) 2632 goto unlock; 2633 2634 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2635 if (err) 2636 goto unlock; 2637 2638 if (vlan->vid == pvid) { 2639 p->bridge_pvid.valid = false; 2640 2641 err = mv88e6xxx_port_commit_pvid(chip, port); 2642 if (err) 2643 goto unlock; 2644 } 2645 2646 unlock: 2647 mv88e6xxx_reg_unlock(chip); 2648 2649 return err; 2650 } 2651 2652 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2653 { 2654 struct mv88e6xxx_chip *chip = ds->priv; 2655 struct mv88e6xxx_vtu_entry vlan; 2656 int err; 2657 2658 mv88e6xxx_reg_lock(chip); 2659 2660 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2661 if (err) 2662 goto unlock; 2663 2664 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2665 2666 unlock: 2667 mv88e6xxx_reg_unlock(chip); 2668 2669 return err; 2670 } 2671 2672 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2673 struct dsa_bridge bridge, 2674 const struct switchdev_vlan_msti *msti) 2675 { 2676 struct mv88e6xxx_chip *chip = ds->priv; 2677 struct mv88e6xxx_vtu_entry vlan; 2678 u8 old_sid, new_sid; 2679 int err; 2680 2681 mv88e6xxx_reg_lock(chip); 2682 2683 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2684 if (err) 2685 goto unlock; 2686 2687 if (!vlan.valid) { 2688 err = -EINVAL; 2689 goto unlock; 2690 } 2691 2692 old_sid = vlan.sid; 2693 2694 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2695 if (err) 2696 goto unlock; 2697 2698 if (new_sid != old_sid) { 2699 vlan.sid = new_sid; 2700 2701 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2702 if (err) { 2703 mv88e6xxx_mst_put(chip, new_sid); 2704 goto unlock; 2705 } 2706 } 2707 2708 err = mv88e6xxx_mst_put(chip, old_sid); 2709 2710 unlock: 2711 mv88e6xxx_reg_unlock(chip); 2712 return err; 2713 } 2714 2715 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2716 const unsigned char *addr, u16 vid, 2717 struct dsa_db db) 2718 { 2719 struct mv88e6xxx_chip *chip = ds->priv; 2720 int err; 2721 2722 mv88e6xxx_reg_lock(chip); 2723 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2724 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2725 mv88e6xxx_reg_unlock(chip); 2726 2727 return err; 2728 } 2729 2730 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2731 const unsigned char *addr, u16 vid, 2732 struct dsa_db db) 2733 { 2734 struct mv88e6xxx_chip *chip = ds->priv; 2735 int err; 2736 2737 mv88e6xxx_reg_lock(chip); 2738 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2739 mv88e6xxx_reg_unlock(chip); 2740 2741 return err; 2742 } 2743 2744 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2745 u16 fid, u16 vid, int port, 2746 dsa_fdb_dump_cb_t *cb, void *data) 2747 { 2748 struct mv88e6xxx_atu_entry addr; 2749 bool is_static; 2750 int err; 2751 2752 addr.state = 0; 2753 eth_broadcast_addr(addr.mac); 2754 2755 do { 2756 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2757 if (err) 2758 return err; 2759 2760 if (!addr.state) 2761 break; 2762 2763 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2764 continue; 2765 2766 if (!is_unicast_ether_addr(addr.mac)) 2767 continue; 2768 2769 is_static = (addr.state == 2770 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2771 err = cb(addr.mac, vid, is_static, data); 2772 if (err) 2773 return err; 2774 } while (!is_broadcast_ether_addr(addr.mac)); 2775 2776 return err; 2777 } 2778 2779 struct mv88e6xxx_port_db_dump_vlan_ctx { 2780 int port; 2781 dsa_fdb_dump_cb_t *cb; 2782 void *data; 2783 }; 2784 2785 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2786 const struct mv88e6xxx_vtu_entry *entry, 2787 void *_data) 2788 { 2789 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2790 2791 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2792 ctx->port, ctx->cb, ctx->data); 2793 } 2794 2795 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2796 dsa_fdb_dump_cb_t *cb, void *data) 2797 { 2798 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2799 .port = port, 2800 .cb = cb, 2801 .data = data, 2802 }; 2803 u16 fid; 2804 int err; 2805 2806 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2807 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2808 if (err) 2809 return err; 2810 2811 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2812 if (err) 2813 return err; 2814 2815 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2816 } 2817 2818 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2819 dsa_fdb_dump_cb_t *cb, void *data) 2820 { 2821 struct mv88e6xxx_chip *chip = ds->priv; 2822 int err; 2823 2824 mv88e6xxx_reg_lock(chip); 2825 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2826 mv88e6xxx_reg_unlock(chip); 2827 2828 return err; 2829 } 2830 2831 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2832 struct dsa_bridge bridge) 2833 { 2834 struct dsa_switch *ds = chip->ds; 2835 struct dsa_switch_tree *dst = ds->dst; 2836 struct dsa_port *dp; 2837 int err; 2838 2839 list_for_each_entry(dp, &dst->ports, list) { 2840 if (dsa_port_offloads_bridge(dp, &bridge)) { 2841 if (dp->ds == ds) { 2842 /* This is a local bridge group member, 2843 * remap its Port VLAN Map. 2844 */ 2845 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2846 if (err) 2847 return err; 2848 } else { 2849 /* This is an external bridge group member, 2850 * remap its cross-chip Port VLAN Table entry. 2851 */ 2852 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2853 dp->index); 2854 if (err) 2855 return err; 2856 } 2857 } 2858 } 2859 2860 return 0; 2861 } 2862 2863 /* Treat the software bridge as a virtual single-port switch behind the 2864 * CPU and map in the PVT. First dst->last_switch elements are taken by 2865 * physical switches, so start from beyond that range. 2866 */ 2867 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2868 unsigned int bridge_num) 2869 { 2870 u8 dev = bridge_num + ds->dst->last_switch; 2871 struct mv88e6xxx_chip *chip = ds->priv; 2872 2873 return mv88e6xxx_pvt_map(chip, dev, 0); 2874 } 2875 2876 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2877 struct dsa_bridge bridge, 2878 bool *tx_fwd_offload, 2879 struct netlink_ext_ack *extack) 2880 { 2881 struct mv88e6xxx_chip *chip = ds->priv; 2882 int err; 2883 2884 mv88e6xxx_reg_lock(chip); 2885 2886 err = mv88e6xxx_bridge_map(chip, bridge); 2887 if (err) 2888 goto unlock; 2889 2890 err = mv88e6xxx_port_set_map_da(chip, port, true); 2891 if (err) 2892 goto unlock; 2893 2894 err = mv88e6xxx_port_commit_pvid(chip, port); 2895 if (err) 2896 goto unlock; 2897 2898 if (mv88e6xxx_has_pvt(chip)) { 2899 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2900 if (err) 2901 goto unlock; 2902 2903 *tx_fwd_offload = true; 2904 } 2905 2906 unlock: 2907 mv88e6xxx_reg_unlock(chip); 2908 2909 return err; 2910 } 2911 2912 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2913 struct dsa_bridge bridge) 2914 { 2915 struct mv88e6xxx_chip *chip = ds->priv; 2916 int err; 2917 2918 mv88e6xxx_reg_lock(chip); 2919 2920 if (bridge.tx_fwd_offload && 2921 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2922 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2923 2924 if (mv88e6xxx_bridge_map(chip, bridge) || 2925 mv88e6xxx_port_vlan_map(chip, port)) 2926 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2927 2928 err = mv88e6xxx_port_set_map_da(chip, port, false); 2929 if (err) 2930 dev_err(ds->dev, 2931 "port %d failed to restore map-DA: %pe\n", 2932 port, ERR_PTR(err)); 2933 2934 err = mv88e6xxx_port_commit_pvid(chip, port); 2935 if (err) 2936 dev_err(ds->dev, 2937 "port %d failed to restore standalone pvid: %pe\n", 2938 port, ERR_PTR(err)); 2939 2940 mv88e6xxx_reg_unlock(chip); 2941 } 2942 2943 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2944 int tree_index, int sw_index, 2945 int port, struct dsa_bridge bridge, 2946 struct netlink_ext_ack *extack) 2947 { 2948 struct mv88e6xxx_chip *chip = ds->priv; 2949 int err; 2950 2951 if (tree_index != ds->dst->index) 2952 return 0; 2953 2954 mv88e6xxx_reg_lock(chip); 2955 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2956 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2957 mv88e6xxx_reg_unlock(chip); 2958 2959 return err; 2960 } 2961 2962 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2963 int tree_index, int sw_index, 2964 int port, struct dsa_bridge bridge) 2965 { 2966 struct mv88e6xxx_chip *chip = ds->priv; 2967 2968 if (tree_index != ds->dst->index) 2969 return; 2970 2971 mv88e6xxx_reg_lock(chip); 2972 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2973 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2974 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2975 mv88e6xxx_reg_unlock(chip); 2976 } 2977 2978 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2979 { 2980 if (chip->info->ops->reset) 2981 return chip->info->ops->reset(chip); 2982 2983 return 0; 2984 } 2985 2986 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2987 { 2988 struct gpio_desc *gpiod = chip->reset; 2989 2990 /* If there is a GPIO connected to the reset pin, toggle it */ 2991 if (gpiod) { 2992 gpiod_set_value_cansleep(gpiod, 1); 2993 usleep_range(10000, 20000); 2994 gpiod_set_value_cansleep(gpiod, 0); 2995 usleep_range(10000, 20000); 2996 2997 mv88e6xxx_g1_wait_eeprom_done(chip); 2998 } 2999 } 3000 3001 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3002 { 3003 int i, err; 3004 3005 /* Set all ports to the Disabled state */ 3006 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3007 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3008 if (err) 3009 return err; 3010 } 3011 3012 /* Wait for transmit queues to drain, 3013 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3014 */ 3015 usleep_range(2000, 4000); 3016 3017 return 0; 3018 } 3019 3020 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3021 { 3022 int err; 3023 3024 err = mv88e6xxx_disable_ports(chip); 3025 if (err) 3026 return err; 3027 3028 mv88e6xxx_hardware_reset(chip); 3029 3030 return mv88e6xxx_software_reset(chip); 3031 } 3032 3033 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3034 enum mv88e6xxx_frame_mode frame, 3035 enum mv88e6xxx_egress_mode egress, u16 etype) 3036 { 3037 int err; 3038 3039 if (!chip->info->ops->port_set_frame_mode) 3040 return -EOPNOTSUPP; 3041 3042 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3043 if (err) 3044 return err; 3045 3046 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3047 if (err) 3048 return err; 3049 3050 if (chip->info->ops->port_set_ether_type) 3051 return chip->info->ops->port_set_ether_type(chip, port, etype); 3052 3053 return 0; 3054 } 3055 3056 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3057 { 3058 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3059 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3060 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3061 } 3062 3063 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3064 { 3065 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3066 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3067 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3068 } 3069 3070 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3071 { 3072 return mv88e6xxx_set_port_mode(chip, port, 3073 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3074 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3075 ETH_P_EDSA); 3076 } 3077 3078 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3079 { 3080 if (dsa_is_dsa_port(chip->ds, port)) 3081 return mv88e6xxx_set_port_mode_dsa(chip, port); 3082 3083 if (dsa_is_user_port(chip->ds, port)) 3084 return mv88e6xxx_set_port_mode_normal(chip, port); 3085 3086 /* Setup CPU port mode depending on its supported tag format */ 3087 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3088 return mv88e6xxx_set_port_mode_dsa(chip, port); 3089 3090 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3091 return mv88e6xxx_set_port_mode_edsa(chip, port); 3092 3093 return -EINVAL; 3094 } 3095 3096 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3097 { 3098 bool message = dsa_is_dsa_port(chip->ds, port); 3099 3100 return mv88e6xxx_port_set_message_port(chip, port, message); 3101 } 3102 3103 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3104 { 3105 int err; 3106 3107 if (chip->info->ops->port_set_ucast_flood) { 3108 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3109 if (err) 3110 return err; 3111 } 3112 if (chip->info->ops->port_set_mcast_flood) { 3113 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3114 if (err) 3115 return err; 3116 } 3117 3118 return 0; 3119 } 3120 3121 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3122 { 3123 struct mv88e6xxx_port *mvp = dev_id; 3124 struct mv88e6xxx_chip *chip = mvp->chip; 3125 irqreturn_t ret = IRQ_NONE; 3126 int port = mvp->port; 3127 int lane; 3128 3129 mv88e6xxx_reg_lock(chip); 3130 lane = mv88e6xxx_serdes_get_lane(chip, port); 3131 if (lane >= 0) 3132 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3133 mv88e6xxx_reg_unlock(chip); 3134 3135 return ret; 3136 } 3137 3138 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3139 int lane) 3140 { 3141 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3142 unsigned int irq; 3143 int err; 3144 3145 /* Nothing to request if this SERDES port has no IRQ */ 3146 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3147 if (!irq) 3148 return 0; 3149 3150 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3151 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3152 3153 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3154 mv88e6xxx_reg_unlock(chip); 3155 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3156 IRQF_ONESHOT, dev_id->serdes_irq_name, 3157 dev_id); 3158 mv88e6xxx_reg_lock(chip); 3159 if (err) 3160 return err; 3161 3162 dev_id->serdes_irq = irq; 3163 3164 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3165 } 3166 3167 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3168 int lane) 3169 { 3170 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3171 unsigned int irq = dev_id->serdes_irq; 3172 int err; 3173 3174 /* Nothing to free if no IRQ has been requested */ 3175 if (!irq) 3176 return 0; 3177 3178 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3179 3180 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3181 mv88e6xxx_reg_unlock(chip); 3182 free_irq(irq, dev_id); 3183 mv88e6xxx_reg_lock(chip); 3184 3185 dev_id->serdes_irq = 0; 3186 3187 return err; 3188 } 3189 3190 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3191 bool on) 3192 { 3193 int lane; 3194 int err; 3195 3196 lane = mv88e6xxx_serdes_get_lane(chip, port); 3197 if (lane < 0) 3198 return 0; 3199 3200 if (on) { 3201 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3202 if (err) 3203 return err; 3204 3205 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3206 } else { 3207 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3208 if (err) 3209 return err; 3210 3211 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3212 } 3213 3214 return err; 3215 } 3216 3217 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3218 enum mv88e6xxx_egress_direction direction, 3219 int port) 3220 { 3221 int err; 3222 3223 if (!chip->info->ops->set_egress_port) 3224 return -EOPNOTSUPP; 3225 3226 err = chip->info->ops->set_egress_port(chip, direction, port); 3227 if (err) 3228 return err; 3229 3230 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3231 chip->ingress_dest_port = port; 3232 else 3233 chip->egress_dest_port = port; 3234 3235 return 0; 3236 } 3237 3238 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3239 { 3240 struct dsa_switch *ds = chip->ds; 3241 int upstream_port; 3242 int err; 3243 3244 upstream_port = dsa_upstream_port(ds, port); 3245 if (chip->info->ops->port_set_upstream_port) { 3246 err = chip->info->ops->port_set_upstream_port(chip, port, 3247 upstream_port); 3248 if (err) 3249 return err; 3250 } 3251 3252 if (port == upstream_port) { 3253 if (chip->info->ops->set_cpu_port) { 3254 err = chip->info->ops->set_cpu_port(chip, 3255 upstream_port); 3256 if (err) 3257 return err; 3258 } 3259 3260 err = mv88e6xxx_set_egress_port(chip, 3261 MV88E6XXX_EGRESS_DIR_INGRESS, 3262 upstream_port); 3263 if (err && err != -EOPNOTSUPP) 3264 return err; 3265 3266 err = mv88e6xxx_set_egress_port(chip, 3267 MV88E6XXX_EGRESS_DIR_EGRESS, 3268 upstream_port); 3269 if (err && err != -EOPNOTSUPP) 3270 return err; 3271 } 3272 3273 return 0; 3274 } 3275 3276 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3277 { 3278 struct device_node *phy_handle = NULL; 3279 struct dsa_switch *ds = chip->ds; 3280 struct dsa_port *dp; 3281 int tx_amp; 3282 int err; 3283 u16 reg; 3284 3285 chip->ports[port].chip = chip; 3286 chip->ports[port].port = port; 3287 3288 /* MAC Forcing register: don't force link, speed, duplex or flow control 3289 * state to any particular values on physical ports, but force the CPU 3290 * port and all DSA ports to their maximum bandwidth and full duplex. 3291 */ 3292 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 3293 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3294 SPEED_MAX, DUPLEX_FULL, 3295 PAUSE_OFF, 3296 PHY_INTERFACE_MODE_NA); 3297 else 3298 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3299 SPEED_UNFORCED, DUPLEX_UNFORCED, 3300 PAUSE_ON, 3301 PHY_INTERFACE_MODE_NA); 3302 if (err) 3303 return err; 3304 3305 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3306 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3307 * tunneling, determine priority by looking at 802.1p and IP 3308 * priority fields (IP prio has precedence), and set STP state 3309 * to Forwarding. 3310 * 3311 * If this is the CPU link, use DSA or EDSA tagging depending 3312 * on which tagging mode was configured. 3313 * 3314 * If this is a link to another switch, use DSA tagging mode. 3315 * 3316 * If this is the upstream port for this switch, enable 3317 * forwarding of unknown unicasts and multicasts. 3318 */ 3319 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 3320 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3321 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3322 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3323 if (err) 3324 return err; 3325 3326 err = mv88e6xxx_setup_port_mode(chip, port); 3327 if (err) 3328 return err; 3329 3330 err = mv88e6xxx_setup_egress_floods(chip, port); 3331 if (err) 3332 return err; 3333 3334 /* Port Control 2: don't force a good FCS, set the MTU size to 3335 * 10222 bytes, disable 802.1q tags checking, don't discard 3336 * tagged or untagged frames on this port, skip destination 3337 * address lookup on user ports, disable ARP mirroring and don't 3338 * send a copy of all transmitted/received frames on this port 3339 * to the CPU. 3340 */ 3341 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3342 if (err) 3343 return err; 3344 3345 err = mv88e6xxx_setup_upstream_port(chip, port); 3346 if (err) 3347 return err; 3348 3349 /* On chips that support it, set all downstream DSA ports' 3350 * VLAN policy to TRAP. In combination with loading 3351 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3352 * provides a better isolation barrier between standalone 3353 * ports, as the ATU is bypassed on any intermediate switches 3354 * between the incoming port and the CPU. 3355 */ 3356 if (dsa_is_downstream_port(ds, port) && 3357 chip->info->ops->port_set_policy) { 3358 err = chip->info->ops->port_set_policy(chip, port, 3359 MV88E6XXX_POLICY_MAPPING_VTU, 3360 MV88E6XXX_POLICY_ACTION_TRAP); 3361 if (err) 3362 return err; 3363 } 3364 3365 /* User ports start out in standalone mode and 802.1Q is 3366 * therefore disabled. On DSA ports, all valid VIDs are always 3367 * loaded in the VTU - therefore, enable 802.1Q in order to take 3368 * advantage of VLAN policy on chips that supports it. 3369 */ 3370 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3371 dsa_is_user_port(ds, port) ? 3372 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3373 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3374 if (err) 3375 return err; 3376 3377 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3378 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3379 * the first free FID. This will be used as the private PVID for 3380 * unbridged ports. Shared (DSA and CPU) ports must also be 3381 * members of this VID, in order to trap all frames assigned to 3382 * it to the CPU. 3383 */ 3384 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3385 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3386 false); 3387 if (err) 3388 return err; 3389 3390 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3391 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3392 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3393 * as the private PVID on ports under a VLAN-unaware bridge. 3394 * Shared (DSA and CPU) ports must also be members of it, to translate 3395 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3396 * relying on their port default FID. 3397 */ 3398 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3399 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3400 false); 3401 if (err) 3402 return err; 3403 3404 if (chip->info->ops->port_set_jumbo_size) { 3405 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3406 if (err) 3407 return err; 3408 } 3409 3410 /* Port Association Vector: disable automatic address learning 3411 * on all user ports since they start out in standalone 3412 * mode. When joining a bridge, learning will be configured to 3413 * match the bridge port settings. Enable learning on all 3414 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3415 * learning process. 3416 * 3417 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3418 * and RefreshLocked. I.e. setup standard automatic learning. 3419 */ 3420 if (dsa_is_user_port(ds, port)) 3421 reg = 0; 3422 else 3423 reg = 1 << port; 3424 3425 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3426 reg); 3427 if (err) 3428 return err; 3429 3430 /* Egress rate control 2: disable egress rate control. */ 3431 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3432 0x0000); 3433 if (err) 3434 return err; 3435 3436 if (chip->info->ops->port_pause_limit) { 3437 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3438 if (err) 3439 return err; 3440 } 3441 3442 if (chip->info->ops->port_disable_learn_limit) { 3443 err = chip->info->ops->port_disable_learn_limit(chip, port); 3444 if (err) 3445 return err; 3446 } 3447 3448 if (chip->info->ops->port_disable_pri_override) { 3449 err = chip->info->ops->port_disable_pri_override(chip, port); 3450 if (err) 3451 return err; 3452 } 3453 3454 if (chip->info->ops->port_tag_remap) { 3455 err = chip->info->ops->port_tag_remap(chip, port); 3456 if (err) 3457 return err; 3458 } 3459 3460 if (chip->info->ops->port_egress_rate_limiting) { 3461 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3462 if (err) 3463 return err; 3464 } 3465 3466 if (chip->info->ops->port_setup_message_port) { 3467 err = chip->info->ops->port_setup_message_port(chip, port); 3468 if (err) 3469 return err; 3470 } 3471 3472 if (chip->info->ops->serdes_set_tx_amplitude) { 3473 dp = dsa_to_port(ds, port); 3474 if (dp) 3475 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3476 3477 if (phy_handle && !of_property_read_u32(phy_handle, 3478 "tx-p2p-microvolt", 3479 &tx_amp)) 3480 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3481 port, tx_amp); 3482 if (phy_handle) { 3483 of_node_put(phy_handle); 3484 if (err) 3485 return err; 3486 } 3487 } 3488 3489 /* Port based VLAN map: give each port the same default address 3490 * database, and allow bidirectional communication between the 3491 * CPU and DSA port(s), and the other ports. 3492 */ 3493 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3494 if (err) 3495 return err; 3496 3497 err = mv88e6xxx_port_vlan_map(chip, port); 3498 if (err) 3499 return err; 3500 3501 /* Default VLAN ID and priority: don't set a default VLAN 3502 * ID, and set the default packet priority to zero. 3503 */ 3504 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3505 } 3506 3507 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3508 { 3509 struct mv88e6xxx_chip *chip = ds->priv; 3510 3511 if (chip->info->ops->port_set_jumbo_size) 3512 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3513 else if (chip->info->ops->set_max_frame_size) 3514 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3515 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3516 } 3517 3518 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3519 { 3520 struct mv88e6xxx_chip *chip = ds->priv; 3521 int ret = 0; 3522 3523 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3524 new_mtu += EDSA_HLEN; 3525 3526 mv88e6xxx_reg_lock(chip); 3527 if (chip->info->ops->port_set_jumbo_size) 3528 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3529 else if (chip->info->ops->set_max_frame_size) 3530 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3531 else 3532 if (new_mtu > 1522) 3533 ret = -EINVAL; 3534 mv88e6xxx_reg_unlock(chip); 3535 3536 return ret; 3537 } 3538 3539 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3540 struct phy_device *phydev) 3541 { 3542 struct mv88e6xxx_chip *chip = ds->priv; 3543 int err; 3544 3545 mv88e6xxx_reg_lock(chip); 3546 err = mv88e6xxx_serdes_power(chip, port, true); 3547 mv88e6xxx_reg_unlock(chip); 3548 3549 return err; 3550 } 3551 3552 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3553 { 3554 struct mv88e6xxx_chip *chip = ds->priv; 3555 3556 mv88e6xxx_reg_lock(chip); 3557 if (mv88e6xxx_serdes_power(chip, port, false)) 3558 dev_err(chip->dev, "failed to power off SERDES\n"); 3559 mv88e6xxx_reg_unlock(chip); 3560 } 3561 3562 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3563 unsigned int ageing_time) 3564 { 3565 struct mv88e6xxx_chip *chip = ds->priv; 3566 int err; 3567 3568 mv88e6xxx_reg_lock(chip); 3569 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3570 mv88e6xxx_reg_unlock(chip); 3571 3572 return err; 3573 } 3574 3575 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3576 { 3577 int err; 3578 3579 /* Initialize the statistics unit */ 3580 if (chip->info->ops->stats_set_histogram) { 3581 err = chip->info->ops->stats_set_histogram(chip); 3582 if (err) 3583 return err; 3584 } 3585 3586 return mv88e6xxx_g1_stats_clear(chip); 3587 } 3588 3589 /* Check if the errata has already been applied. */ 3590 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3591 { 3592 int port; 3593 int err; 3594 u16 val; 3595 3596 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3597 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3598 if (err) { 3599 dev_err(chip->dev, 3600 "Error reading hidden register: %d\n", err); 3601 return false; 3602 } 3603 if (val != 0x01c0) 3604 return false; 3605 } 3606 3607 return true; 3608 } 3609 3610 /* The 6390 copper ports have an errata which require poking magic 3611 * values into undocumented hidden registers and then performing a 3612 * software reset. 3613 */ 3614 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3615 { 3616 int port; 3617 int err; 3618 3619 if (mv88e6390_setup_errata_applied(chip)) 3620 return 0; 3621 3622 /* Set the ports into blocking mode */ 3623 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3624 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3625 if (err) 3626 return err; 3627 } 3628 3629 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3630 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3631 if (err) 3632 return err; 3633 } 3634 3635 return mv88e6xxx_software_reset(chip); 3636 } 3637 3638 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3639 { 3640 mv88e6xxx_teardown_devlink_params(ds); 3641 dsa_devlink_resources_unregister(ds); 3642 mv88e6xxx_teardown_devlink_regions_global(ds); 3643 } 3644 3645 static int mv88e6xxx_setup(struct dsa_switch *ds) 3646 { 3647 struct mv88e6xxx_chip *chip = ds->priv; 3648 u8 cmode; 3649 int err; 3650 int i; 3651 3652 chip->ds = ds; 3653 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3654 3655 /* Since virtual bridges are mapped in the PVT, the number we support 3656 * depends on the physical switch topology. We need to let DSA figure 3657 * that out and therefore we cannot set this at dsa_register_switch() 3658 * time. 3659 */ 3660 if (mv88e6xxx_has_pvt(chip)) 3661 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3662 ds->dst->last_switch - 1; 3663 3664 mv88e6xxx_reg_lock(chip); 3665 3666 if (chip->info->ops->setup_errata) { 3667 err = chip->info->ops->setup_errata(chip); 3668 if (err) 3669 goto unlock; 3670 } 3671 3672 /* Cache the cmode of each port. */ 3673 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3674 if (chip->info->ops->port_get_cmode) { 3675 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3676 if (err) 3677 goto unlock; 3678 3679 chip->ports[i].cmode = cmode; 3680 } 3681 } 3682 3683 err = mv88e6xxx_vtu_setup(chip); 3684 if (err) 3685 goto unlock; 3686 3687 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3688 * VTU, thereby also flushing the STU). 3689 */ 3690 err = mv88e6xxx_stu_setup(chip); 3691 if (err) 3692 goto unlock; 3693 3694 /* Setup Switch Port Registers */ 3695 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3696 if (dsa_is_unused_port(ds, i)) 3697 continue; 3698 3699 /* Prevent the use of an invalid port. */ 3700 if (mv88e6xxx_is_invalid_port(chip, i)) { 3701 dev_err(chip->dev, "port %d is invalid\n", i); 3702 err = -EINVAL; 3703 goto unlock; 3704 } 3705 3706 err = mv88e6xxx_setup_port(chip, i); 3707 if (err) 3708 goto unlock; 3709 } 3710 3711 err = mv88e6xxx_irl_setup(chip); 3712 if (err) 3713 goto unlock; 3714 3715 err = mv88e6xxx_mac_setup(chip); 3716 if (err) 3717 goto unlock; 3718 3719 err = mv88e6xxx_phy_setup(chip); 3720 if (err) 3721 goto unlock; 3722 3723 err = mv88e6xxx_pvt_setup(chip); 3724 if (err) 3725 goto unlock; 3726 3727 err = mv88e6xxx_atu_setup(chip); 3728 if (err) 3729 goto unlock; 3730 3731 err = mv88e6xxx_broadcast_setup(chip, 0); 3732 if (err) 3733 goto unlock; 3734 3735 err = mv88e6xxx_pot_setup(chip); 3736 if (err) 3737 goto unlock; 3738 3739 err = mv88e6xxx_rmu_setup(chip); 3740 if (err) 3741 goto unlock; 3742 3743 err = mv88e6xxx_rsvd2cpu_setup(chip); 3744 if (err) 3745 goto unlock; 3746 3747 err = mv88e6xxx_trunk_setup(chip); 3748 if (err) 3749 goto unlock; 3750 3751 err = mv88e6xxx_devmap_setup(chip); 3752 if (err) 3753 goto unlock; 3754 3755 err = mv88e6xxx_pri_setup(chip); 3756 if (err) 3757 goto unlock; 3758 3759 /* Setup PTP Hardware Clock and timestamping */ 3760 if (chip->info->ptp_support) { 3761 err = mv88e6xxx_ptp_setup(chip); 3762 if (err) 3763 goto unlock; 3764 3765 err = mv88e6xxx_hwtstamp_setup(chip); 3766 if (err) 3767 goto unlock; 3768 } 3769 3770 err = mv88e6xxx_stats_setup(chip); 3771 if (err) 3772 goto unlock; 3773 3774 unlock: 3775 mv88e6xxx_reg_unlock(chip); 3776 3777 if (err) 3778 return err; 3779 3780 /* Have to be called without holding the register lock, since 3781 * they take the devlink lock, and we later take the locks in 3782 * the reverse order when getting/setting parameters or 3783 * resource occupancy. 3784 */ 3785 err = mv88e6xxx_setup_devlink_resources(ds); 3786 if (err) 3787 return err; 3788 3789 err = mv88e6xxx_setup_devlink_params(ds); 3790 if (err) 3791 goto out_resources; 3792 3793 err = mv88e6xxx_setup_devlink_regions_global(ds); 3794 if (err) 3795 goto out_params; 3796 3797 return 0; 3798 3799 out_params: 3800 mv88e6xxx_teardown_devlink_params(ds); 3801 out_resources: 3802 dsa_devlink_resources_unregister(ds); 3803 3804 return err; 3805 } 3806 3807 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3808 { 3809 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3810 } 3811 3812 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3813 { 3814 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3815 } 3816 3817 /* prod_id for switch families which do not have a PHY model number */ 3818 static const u16 family_prod_id_table[] = { 3819 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3820 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3821 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3822 }; 3823 3824 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3825 { 3826 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3827 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3828 u16 prod_id; 3829 u16 val; 3830 int err; 3831 3832 if (!chip->info->ops->phy_read) 3833 return -EOPNOTSUPP; 3834 3835 mv88e6xxx_reg_lock(chip); 3836 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3837 mv88e6xxx_reg_unlock(chip); 3838 3839 /* Some internal PHYs don't have a model number. */ 3840 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3841 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3842 prod_id = family_prod_id_table[chip->info->family]; 3843 if (prod_id) 3844 val |= prod_id >> 4; 3845 } 3846 3847 return err ? err : val; 3848 } 3849 3850 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3851 { 3852 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3853 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3854 int err; 3855 3856 if (!chip->info->ops->phy_write) 3857 return -EOPNOTSUPP; 3858 3859 mv88e6xxx_reg_lock(chip); 3860 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3861 mv88e6xxx_reg_unlock(chip); 3862 3863 return err; 3864 } 3865 3866 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3867 struct device_node *np, 3868 bool external) 3869 { 3870 static int index; 3871 struct mv88e6xxx_mdio_bus *mdio_bus; 3872 struct mii_bus *bus; 3873 int err; 3874 3875 if (external) { 3876 mv88e6xxx_reg_lock(chip); 3877 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3878 mv88e6xxx_reg_unlock(chip); 3879 3880 if (err) 3881 return err; 3882 } 3883 3884 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3885 if (!bus) 3886 return -ENOMEM; 3887 3888 mdio_bus = bus->priv; 3889 mdio_bus->bus = bus; 3890 mdio_bus->chip = chip; 3891 INIT_LIST_HEAD(&mdio_bus->list); 3892 mdio_bus->external = external; 3893 3894 if (np) { 3895 bus->name = np->full_name; 3896 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3897 } else { 3898 bus->name = "mv88e6xxx SMI"; 3899 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3900 } 3901 3902 bus->read = mv88e6xxx_mdio_read; 3903 bus->write = mv88e6xxx_mdio_write; 3904 bus->parent = chip->dev; 3905 3906 if (!external) { 3907 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3908 if (err) 3909 goto out; 3910 } 3911 3912 err = of_mdiobus_register(bus, np); 3913 if (err) { 3914 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3915 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3916 goto out; 3917 } 3918 3919 if (external) 3920 list_add_tail(&mdio_bus->list, &chip->mdios); 3921 else 3922 list_add(&mdio_bus->list, &chip->mdios); 3923 3924 return 0; 3925 3926 out: 3927 mdiobus_free(bus); 3928 return err; 3929 } 3930 3931 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3932 3933 { 3934 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3935 struct mii_bus *bus; 3936 3937 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3938 bus = mdio_bus->bus; 3939 3940 if (!mdio_bus->external) 3941 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3942 3943 mdiobus_unregister(bus); 3944 mdiobus_free(bus); 3945 } 3946 } 3947 3948 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3949 struct device_node *np) 3950 { 3951 struct device_node *child; 3952 int err; 3953 3954 /* Always register one mdio bus for the internal/default mdio 3955 * bus. This maybe represented in the device tree, but is 3956 * optional. 3957 */ 3958 child = of_get_child_by_name(np, "mdio"); 3959 err = mv88e6xxx_mdio_register(chip, child, false); 3960 if (err) 3961 return err; 3962 3963 /* Walk the device tree, and see if there are any other nodes 3964 * which say they are compatible with the external mdio 3965 * bus. 3966 */ 3967 for_each_available_child_of_node(np, child) { 3968 if (of_device_is_compatible( 3969 child, "marvell,mv88e6xxx-mdio-external")) { 3970 err = mv88e6xxx_mdio_register(chip, child, true); 3971 if (err) { 3972 mv88e6xxx_mdios_unregister(chip); 3973 of_node_put(child); 3974 return err; 3975 } 3976 } 3977 } 3978 3979 return 0; 3980 } 3981 3982 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3983 { 3984 struct mv88e6xxx_chip *chip = ds->priv; 3985 3986 return chip->eeprom_len; 3987 } 3988 3989 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3990 struct ethtool_eeprom *eeprom, u8 *data) 3991 { 3992 struct mv88e6xxx_chip *chip = ds->priv; 3993 int err; 3994 3995 if (!chip->info->ops->get_eeprom) 3996 return -EOPNOTSUPP; 3997 3998 mv88e6xxx_reg_lock(chip); 3999 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4000 mv88e6xxx_reg_unlock(chip); 4001 4002 if (err) 4003 return err; 4004 4005 eeprom->magic = 0xc3ec4951; 4006 4007 return 0; 4008 } 4009 4010 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4011 struct ethtool_eeprom *eeprom, u8 *data) 4012 { 4013 struct mv88e6xxx_chip *chip = ds->priv; 4014 int err; 4015 4016 if (!chip->info->ops->set_eeprom) 4017 return -EOPNOTSUPP; 4018 4019 if (eeprom->magic != 0xc3ec4951) 4020 return -EINVAL; 4021 4022 mv88e6xxx_reg_lock(chip); 4023 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4024 mv88e6xxx_reg_unlock(chip); 4025 4026 return err; 4027 } 4028 4029 static const struct mv88e6xxx_ops mv88e6085_ops = { 4030 /* MV88E6XXX_FAMILY_6097 */ 4031 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4032 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4033 .irl_init_all = mv88e6352_g2_irl_init_all, 4034 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4035 .phy_read = mv88e6185_phy_ppu_read, 4036 .phy_write = mv88e6185_phy_ppu_write, 4037 .port_set_link = mv88e6xxx_port_set_link, 4038 .port_sync_link = mv88e6xxx_port_sync_link, 4039 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4040 .port_tag_remap = mv88e6095_port_tag_remap, 4041 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4042 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4043 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4044 .port_set_ether_type = mv88e6351_port_set_ether_type, 4045 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4046 .port_pause_limit = mv88e6097_port_pause_limit, 4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4049 .port_get_cmode = mv88e6185_port_get_cmode, 4050 .port_setup_message_port = mv88e6xxx_setup_message_port, 4051 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4052 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4053 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4054 .stats_get_strings = mv88e6095_stats_get_strings, 4055 .stats_get_stats = mv88e6095_stats_get_stats, 4056 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4057 .set_egress_port = mv88e6095_g1_set_egress_port, 4058 .watchdog_ops = &mv88e6097_watchdog_ops, 4059 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4060 .pot_clear = mv88e6xxx_g2_pot_clear, 4061 .ppu_enable = mv88e6185_g1_ppu_enable, 4062 .ppu_disable = mv88e6185_g1_ppu_disable, 4063 .reset = mv88e6185_g1_reset, 4064 .rmu_disable = mv88e6085_g1_rmu_disable, 4065 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4066 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4067 .phylink_get_caps = mv88e6185_phylink_get_caps, 4068 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4069 }; 4070 4071 static const struct mv88e6xxx_ops mv88e6095_ops = { 4072 /* MV88E6XXX_FAMILY_6095 */ 4073 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4074 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4075 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4076 .phy_read = mv88e6185_phy_ppu_read, 4077 .phy_write = mv88e6185_phy_ppu_write, 4078 .port_set_link = mv88e6xxx_port_set_link, 4079 .port_sync_link = mv88e6185_port_sync_link, 4080 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4081 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4082 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4083 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4084 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4085 .port_get_cmode = mv88e6185_port_get_cmode, 4086 .port_setup_message_port = mv88e6xxx_setup_message_port, 4087 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4088 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4089 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4090 .stats_get_strings = mv88e6095_stats_get_strings, 4091 .stats_get_stats = mv88e6095_stats_get_stats, 4092 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4093 .serdes_power = mv88e6185_serdes_power, 4094 .serdes_get_lane = mv88e6185_serdes_get_lane, 4095 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4096 .ppu_enable = mv88e6185_g1_ppu_enable, 4097 .ppu_disable = mv88e6185_g1_ppu_disable, 4098 .reset = mv88e6185_g1_reset, 4099 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4100 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4101 .phylink_get_caps = mv88e6095_phylink_get_caps, 4102 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4103 }; 4104 4105 static const struct mv88e6xxx_ops mv88e6097_ops = { 4106 /* MV88E6XXX_FAMILY_6097 */ 4107 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4108 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4109 .irl_init_all = mv88e6352_g2_irl_init_all, 4110 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4111 .phy_read = mv88e6xxx_g2_smi_phy_read, 4112 .phy_write = mv88e6xxx_g2_smi_phy_write, 4113 .port_set_link = mv88e6xxx_port_set_link, 4114 .port_sync_link = mv88e6185_port_sync_link, 4115 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4116 .port_tag_remap = mv88e6095_port_tag_remap, 4117 .port_set_policy = mv88e6352_port_set_policy, 4118 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4119 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4120 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4121 .port_set_ether_type = mv88e6351_port_set_ether_type, 4122 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4123 .port_pause_limit = mv88e6097_port_pause_limit, 4124 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4125 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4126 .port_get_cmode = mv88e6185_port_get_cmode, 4127 .port_setup_message_port = mv88e6xxx_setup_message_port, 4128 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4129 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4130 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4131 .stats_get_strings = mv88e6095_stats_get_strings, 4132 .stats_get_stats = mv88e6095_stats_get_stats, 4133 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4134 .set_egress_port = mv88e6095_g1_set_egress_port, 4135 .watchdog_ops = &mv88e6097_watchdog_ops, 4136 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4137 .serdes_power = mv88e6185_serdes_power, 4138 .serdes_get_lane = mv88e6185_serdes_get_lane, 4139 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4140 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4141 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4142 .serdes_irq_status = mv88e6097_serdes_irq_status, 4143 .pot_clear = mv88e6xxx_g2_pot_clear, 4144 .reset = mv88e6352_g1_reset, 4145 .rmu_disable = mv88e6085_g1_rmu_disable, 4146 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4147 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4148 .phylink_get_caps = mv88e6095_phylink_get_caps, 4149 .stu_getnext = mv88e6352_g1_stu_getnext, 4150 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4151 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4152 }; 4153 4154 static const struct mv88e6xxx_ops mv88e6123_ops = { 4155 /* MV88E6XXX_FAMILY_6165 */ 4156 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4157 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4158 .irl_init_all = mv88e6352_g2_irl_init_all, 4159 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4160 .phy_read = mv88e6xxx_g2_smi_phy_read, 4161 .phy_write = mv88e6xxx_g2_smi_phy_write, 4162 .port_set_link = mv88e6xxx_port_set_link, 4163 .port_sync_link = mv88e6xxx_port_sync_link, 4164 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4165 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4166 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4167 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4168 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4169 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4170 .port_get_cmode = mv88e6185_port_get_cmode, 4171 .port_setup_message_port = mv88e6xxx_setup_message_port, 4172 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4173 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4174 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4175 .stats_get_strings = mv88e6095_stats_get_strings, 4176 .stats_get_stats = mv88e6095_stats_get_stats, 4177 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4178 .set_egress_port = mv88e6095_g1_set_egress_port, 4179 .watchdog_ops = &mv88e6097_watchdog_ops, 4180 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4181 .pot_clear = mv88e6xxx_g2_pot_clear, 4182 .reset = mv88e6352_g1_reset, 4183 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4184 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4185 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4186 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4187 .phylink_get_caps = mv88e6185_phylink_get_caps, 4188 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4189 }; 4190 4191 static const struct mv88e6xxx_ops mv88e6131_ops = { 4192 /* MV88E6XXX_FAMILY_6185 */ 4193 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4194 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4195 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4196 .phy_read = mv88e6185_phy_ppu_read, 4197 .phy_write = mv88e6185_phy_ppu_write, 4198 .port_set_link = mv88e6xxx_port_set_link, 4199 .port_sync_link = mv88e6xxx_port_sync_link, 4200 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4201 .port_tag_remap = mv88e6095_port_tag_remap, 4202 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4203 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4204 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4205 .port_set_ether_type = mv88e6351_port_set_ether_type, 4206 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4207 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4208 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4209 .port_pause_limit = mv88e6097_port_pause_limit, 4210 .port_set_pause = mv88e6185_port_set_pause, 4211 .port_get_cmode = mv88e6185_port_get_cmode, 4212 .port_setup_message_port = mv88e6xxx_setup_message_port, 4213 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4214 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4215 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4216 .stats_get_strings = mv88e6095_stats_get_strings, 4217 .stats_get_stats = mv88e6095_stats_get_stats, 4218 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4219 .set_egress_port = mv88e6095_g1_set_egress_port, 4220 .watchdog_ops = &mv88e6097_watchdog_ops, 4221 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4222 .ppu_enable = mv88e6185_g1_ppu_enable, 4223 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4224 .ppu_disable = mv88e6185_g1_ppu_disable, 4225 .reset = mv88e6185_g1_reset, 4226 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4227 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4228 .phylink_get_caps = mv88e6185_phylink_get_caps, 4229 }; 4230 4231 static const struct mv88e6xxx_ops mv88e6141_ops = { 4232 /* MV88E6XXX_FAMILY_6341 */ 4233 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4234 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4235 .irl_init_all = mv88e6352_g2_irl_init_all, 4236 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4237 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4238 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4239 .phy_read = mv88e6xxx_g2_smi_phy_read, 4240 .phy_write = mv88e6xxx_g2_smi_phy_write, 4241 .port_set_link = mv88e6xxx_port_set_link, 4242 .port_sync_link = mv88e6xxx_port_sync_link, 4243 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4244 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4245 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4246 .port_tag_remap = mv88e6095_port_tag_remap, 4247 .port_set_policy = mv88e6352_port_set_policy, 4248 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4249 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4250 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4251 .port_set_ether_type = mv88e6351_port_set_ether_type, 4252 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4253 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4254 .port_pause_limit = mv88e6097_port_pause_limit, 4255 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4256 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4257 .port_get_cmode = mv88e6352_port_get_cmode, 4258 .port_set_cmode = mv88e6341_port_set_cmode, 4259 .port_setup_message_port = mv88e6xxx_setup_message_port, 4260 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4261 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4262 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4263 .stats_get_strings = mv88e6320_stats_get_strings, 4264 .stats_get_stats = mv88e6390_stats_get_stats, 4265 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4266 .set_egress_port = mv88e6390_g1_set_egress_port, 4267 .watchdog_ops = &mv88e6390_watchdog_ops, 4268 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4269 .pot_clear = mv88e6xxx_g2_pot_clear, 4270 .reset = mv88e6352_g1_reset, 4271 .rmu_disable = mv88e6390_g1_rmu_disable, 4272 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4273 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4274 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4275 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4276 .serdes_power = mv88e6390_serdes_power, 4277 .serdes_get_lane = mv88e6341_serdes_get_lane, 4278 /* Check status register pause & lpa register */ 4279 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4280 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4281 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4282 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4283 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4284 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4285 .serdes_irq_status = mv88e6390_serdes_irq_status, 4286 .gpio_ops = &mv88e6352_gpio_ops, 4287 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4288 .serdes_get_strings = mv88e6390_serdes_get_strings, 4289 .serdes_get_stats = mv88e6390_serdes_get_stats, 4290 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4291 .serdes_get_regs = mv88e6390_serdes_get_regs, 4292 .phylink_get_caps = mv88e6341_phylink_get_caps, 4293 }; 4294 4295 static const struct mv88e6xxx_ops mv88e6161_ops = { 4296 /* MV88E6XXX_FAMILY_6165 */ 4297 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4298 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4299 .irl_init_all = mv88e6352_g2_irl_init_all, 4300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4301 .phy_read = mv88e6xxx_g2_smi_phy_read, 4302 .phy_write = mv88e6xxx_g2_smi_phy_write, 4303 .port_set_link = mv88e6xxx_port_set_link, 4304 .port_sync_link = mv88e6xxx_port_sync_link, 4305 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4306 .port_tag_remap = mv88e6095_port_tag_remap, 4307 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4308 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4309 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4310 .port_set_ether_type = mv88e6351_port_set_ether_type, 4311 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4312 .port_pause_limit = mv88e6097_port_pause_limit, 4313 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4314 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4315 .port_get_cmode = mv88e6185_port_get_cmode, 4316 .port_setup_message_port = mv88e6xxx_setup_message_port, 4317 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4318 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4319 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4320 .stats_get_strings = mv88e6095_stats_get_strings, 4321 .stats_get_stats = mv88e6095_stats_get_stats, 4322 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4323 .set_egress_port = mv88e6095_g1_set_egress_port, 4324 .watchdog_ops = &mv88e6097_watchdog_ops, 4325 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4326 .pot_clear = mv88e6xxx_g2_pot_clear, 4327 .reset = mv88e6352_g1_reset, 4328 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4329 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4330 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4331 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4332 .avb_ops = &mv88e6165_avb_ops, 4333 .ptp_ops = &mv88e6165_ptp_ops, 4334 .phylink_get_caps = mv88e6185_phylink_get_caps, 4335 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4336 }; 4337 4338 static const struct mv88e6xxx_ops mv88e6165_ops = { 4339 /* MV88E6XXX_FAMILY_6165 */ 4340 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4341 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4342 .irl_init_all = mv88e6352_g2_irl_init_all, 4343 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4344 .phy_read = mv88e6165_phy_read, 4345 .phy_write = mv88e6165_phy_write, 4346 .port_set_link = mv88e6xxx_port_set_link, 4347 .port_sync_link = mv88e6xxx_port_sync_link, 4348 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4351 .port_get_cmode = mv88e6185_port_get_cmode, 4352 .port_setup_message_port = mv88e6xxx_setup_message_port, 4353 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4354 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4355 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4356 .stats_get_strings = mv88e6095_stats_get_strings, 4357 .stats_get_stats = mv88e6095_stats_get_stats, 4358 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4359 .set_egress_port = mv88e6095_g1_set_egress_port, 4360 .watchdog_ops = &mv88e6097_watchdog_ops, 4361 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4362 .pot_clear = mv88e6xxx_g2_pot_clear, 4363 .reset = mv88e6352_g1_reset, 4364 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4365 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4366 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4367 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4368 .avb_ops = &mv88e6165_avb_ops, 4369 .ptp_ops = &mv88e6165_ptp_ops, 4370 .phylink_get_caps = mv88e6185_phylink_get_caps, 4371 }; 4372 4373 static const struct mv88e6xxx_ops mv88e6171_ops = { 4374 /* MV88E6XXX_FAMILY_6351 */ 4375 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4376 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4377 .irl_init_all = mv88e6352_g2_irl_init_all, 4378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4379 .phy_read = mv88e6xxx_g2_smi_phy_read, 4380 .phy_write = mv88e6xxx_g2_smi_phy_write, 4381 .port_set_link = mv88e6xxx_port_set_link, 4382 .port_sync_link = mv88e6xxx_port_sync_link, 4383 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4384 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4385 .port_tag_remap = mv88e6095_port_tag_remap, 4386 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4387 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4388 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4389 .port_set_ether_type = mv88e6351_port_set_ether_type, 4390 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4391 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4392 .port_pause_limit = mv88e6097_port_pause_limit, 4393 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4394 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4395 .port_get_cmode = mv88e6352_port_get_cmode, 4396 .port_setup_message_port = mv88e6xxx_setup_message_port, 4397 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4398 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4399 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4400 .stats_get_strings = mv88e6095_stats_get_strings, 4401 .stats_get_stats = mv88e6095_stats_get_stats, 4402 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4403 .set_egress_port = mv88e6095_g1_set_egress_port, 4404 .watchdog_ops = &mv88e6097_watchdog_ops, 4405 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4406 .pot_clear = mv88e6xxx_g2_pot_clear, 4407 .reset = mv88e6352_g1_reset, 4408 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4409 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4410 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4411 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4412 .phylink_get_caps = mv88e6185_phylink_get_caps, 4413 }; 4414 4415 static const struct mv88e6xxx_ops mv88e6172_ops = { 4416 /* MV88E6XXX_FAMILY_6352 */ 4417 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4418 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4419 .irl_init_all = mv88e6352_g2_irl_init_all, 4420 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4421 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4423 .phy_read = mv88e6xxx_g2_smi_phy_read, 4424 .phy_write = mv88e6xxx_g2_smi_phy_write, 4425 .port_set_link = mv88e6xxx_port_set_link, 4426 .port_sync_link = mv88e6xxx_port_sync_link, 4427 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4428 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4429 .port_tag_remap = mv88e6095_port_tag_remap, 4430 .port_set_policy = mv88e6352_port_set_policy, 4431 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4432 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4433 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4434 .port_set_ether_type = mv88e6351_port_set_ether_type, 4435 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4436 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4437 .port_pause_limit = mv88e6097_port_pause_limit, 4438 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4439 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4440 .port_get_cmode = mv88e6352_port_get_cmode, 4441 .port_setup_message_port = mv88e6xxx_setup_message_port, 4442 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4443 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4444 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4445 .stats_get_strings = mv88e6095_stats_get_strings, 4446 .stats_get_stats = mv88e6095_stats_get_stats, 4447 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4448 .set_egress_port = mv88e6095_g1_set_egress_port, 4449 .watchdog_ops = &mv88e6097_watchdog_ops, 4450 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4451 .pot_clear = mv88e6xxx_g2_pot_clear, 4452 .reset = mv88e6352_g1_reset, 4453 .rmu_disable = mv88e6352_g1_rmu_disable, 4454 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4455 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4456 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4457 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4458 .serdes_get_lane = mv88e6352_serdes_get_lane, 4459 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4460 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4461 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4462 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4463 .serdes_power = mv88e6352_serdes_power, 4464 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4465 .serdes_get_regs = mv88e6352_serdes_get_regs, 4466 .gpio_ops = &mv88e6352_gpio_ops, 4467 .phylink_get_caps = mv88e6352_phylink_get_caps, 4468 }; 4469 4470 static const struct mv88e6xxx_ops mv88e6175_ops = { 4471 /* MV88E6XXX_FAMILY_6351 */ 4472 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4473 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4474 .irl_init_all = mv88e6352_g2_irl_init_all, 4475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4476 .phy_read = mv88e6xxx_g2_smi_phy_read, 4477 .phy_write = mv88e6xxx_g2_smi_phy_write, 4478 .port_set_link = mv88e6xxx_port_set_link, 4479 .port_sync_link = mv88e6xxx_port_sync_link, 4480 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4481 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4482 .port_tag_remap = mv88e6095_port_tag_remap, 4483 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4484 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4485 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4486 .port_set_ether_type = mv88e6351_port_set_ether_type, 4487 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4489 .port_pause_limit = mv88e6097_port_pause_limit, 4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4492 .port_get_cmode = mv88e6352_port_get_cmode, 4493 .port_setup_message_port = mv88e6xxx_setup_message_port, 4494 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4497 .stats_get_strings = mv88e6095_stats_get_strings, 4498 .stats_get_stats = mv88e6095_stats_get_stats, 4499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4500 .set_egress_port = mv88e6095_g1_set_egress_port, 4501 .watchdog_ops = &mv88e6097_watchdog_ops, 4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4503 .pot_clear = mv88e6xxx_g2_pot_clear, 4504 .reset = mv88e6352_g1_reset, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .phylink_get_caps = mv88e6185_phylink_get_caps, 4510 }; 4511 4512 static const struct mv88e6xxx_ops mv88e6176_ops = { 4513 /* MV88E6XXX_FAMILY_6352 */ 4514 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4515 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4516 .irl_init_all = mv88e6352_g2_irl_init_all, 4517 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4518 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4519 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4520 .phy_read = mv88e6xxx_g2_smi_phy_read, 4521 .phy_write = mv88e6xxx_g2_smi_phy_write, 4522 .port_set_link = mv88e6xxx_port_set_link, 4523 .port_sync_link = mv88e6xxx_port_sync_link, 4524 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4525 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4526 .port_tag_remap = mv88e6095_port_tag_remap, 4527 .port_set_policy = mv88e6352_port_set_policy, 4528 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4529 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4530 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4531 .port_set_ether_type = mv88e6351_port_set_ether_type, 4532 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4533 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4534 .port_pause_limit = mv88e6097_port_pause_limit, 4535 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4536 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4537 .port_get_cmode = mv88e6352_port_get_cmode, 4538 .port_setup_message_port = mv88e6xxx_setup_message_port, 4539 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4540 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4541 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4542 .stats_get_strings = mv88e6095_stats_get_strings, 4543 .stats_get_stats = mv88e6095_stats_get_stats, 4544 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4545 .set_egress_port = mv88e6095_g1_set_egress_port, 4546 .watchdog_ops = &mv88e6097_watchdog_ops, 4547 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4548 .pot_clear = mv88e6xxx_g2_pot_clear, 4549 .reset = mv88e6352_g1_reset, 4550 .rmu_disable = mv88e6352_g1_rmu_disable, 4551 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4552 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4553 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4554 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4555 .serdes_get_lane = mv88e6352_serdes_get_lane, 4556 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4557 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4558 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4559 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4560 .serdes_power = mv88e6352_serdes_power, 4561 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4562 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4563 .serdes_irq_status = mv88e6352_serdes_irq_status, 4564 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4565 .serdes_get_regs = mv88e6352_serdes_get_regs, 4566 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4567 .gpio_ops = &mv88e6352_gpio_ops, 4568 .phylink_get_caps = mv88e6352_phylink_get_caps, 4569 }; 4570 4571 static const struct mv88e6xxx_ops mv88e6185_ops = { 4572 /* MV88E6XXX_FAMILY_6185 */ 4573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4574 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4575 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4576 .phy_read = mv88e6185_phy_ppu_read, 4577 .phy_write = mv88e6185_phy_ppu_write, 4578 .port_set_link = mv88e6xxx_port_set_link, 4579 .port_sync_link = mv88e6185_port_sync_link, 4580 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4581 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4582 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4583 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4584 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4585 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4586 .port_set_pause = mv88e6185_port_set_pause, 4587 .port_get_cmode = mv88e6185_port_get_cmode, 4588 .port_setup_message_port = mv88e6xxx_setup_message_port, 4589 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4590 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4591 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4592 .stats_get_strings = mv88e6095_stats_get_strings, 4593 .stats_get_stats = mv88e6095_stats_get_stats, 4594 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4595 .set_egress_port = mv88e6095_g1_set_egress_port, 4596 .watchdog_ops = &mv88e6097_watchdog_ops, 4597 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4598 .serdes_power = mv88e6185_serdes_power, 4599 .serdes_get_lane = mv88e6185_serdes_get_lane, 4600 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4601 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4602 .ppu_enable = mv88e6185_g1_ppu_enable, 4603 .ppu_disable = mv88e6185_g1_ppu_disable, 4604 .reset = mv88e6185_g1_reset, 4605 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4606 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4607 .phylink_get_caps = mv88e6185_phylink_get_caps, 4608 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4609 }; 4610 4611 static const struct mv88e6xxx_ops mv88e6190_ops = { 4612 /* MV88E6XXX_FAMILY_6390 */ 4613 .setup_errata = mv88e6390_setup_errata, 4614 .irl_init_all = mv88e6390_g2_irl_init_all, 4615 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4616 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4618 .phy_read = mv88e6xxx_g2_smi_phy_read, 4619 .phy_write = mv88e6xxx_g2_smi_phy_write, 4620 .port_set_link = mv88e6xxx_port_set_link, 4621 .port_sync_link = mv88e6xxx_port_sync_link, 4622 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4623 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4624 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4625 .port_tag_remap = mv88e6390_port_tag_remap, 4626 .port_set_policy = mv88e6352_port_set_policy, 4627 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4628 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4629 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4630 .port_set_ether_type = mv88e6351_port_set_ether_type, 4631 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4632 .port_pause_limit = mv88e6390_port_pause_limit, 4633 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4634 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4635 .port_get_cmode = mv88e6352_port_get_cmode, 4636 .port_set_cmode = mv88e6390_port_set_cmode, 4637 .port_setup_message_port = mv88e6xxx_setup_message_port, 4638 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4639 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4640 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4641 .stats_get_strings = mv88e6320_stats_get_strings, 4642 .stats_get_stats = mv88e6390_stats_get_stats, 4643 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4644 .set_egress_port = mv88e6390_g1_set_egress_port, 4645 .watchdog_ops = &mv88e6390_watchdog_ops, 4646 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4647 .pot_clear = mv88e6xxx_g2_pot_clear, 4648 .reset = mv88e6352_g1_reset, 4649 .rmu_disable = mv88e6390_g1_rmu_disable, 4650 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4651 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4652 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4653 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4654 .serdes_power = mv88e6390_serdes_power, 4655 .serdes_get_lane = mv88e6390_serdes_get_lane, 4656 /* Check status register pause & lpa register */ 4657 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4658 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4659 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4660 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4661 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4662 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4663 .serdes_irq_status = mv88e6390_serdes_irq_status, 4664 .serdes_get_strings = mv88e6390_serdes_get_strings, 4665 .serdes_get_stats = mv88e6390_serdes_get_stats, 4666 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4667 .serdes_get_regs = mv88e6390_serdes_get_regs, 4668 .gpio_ops = &mv88e6352_gpio_ops, 4669 .phylink_get_caps = mv88e6390_phylink_get_caps, 4670 }; 4671 4672 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4673 /* MV88E6XXX_FAMILY_6390 */ 4674 .setup_errata = mv88e6390_setup_errata, 4675 .irl_init_all = mv88e6390_g2_irl_init_all, 4676 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4677 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4678 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4679 .phy_read = mv88e6xxx_g2_smi_phy_read, 4680 .phy_write = mv88e6xxx_g2_smi_phy_write, 4681 .port_set_link = mv88e6xxx_port_set_link, 4682 .port_sync_link = mv88e6xxx_port_sync_link, 4683 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4684 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4685 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4686 .port_tag_remap = mv88e6390_port_tag_remap, 4687 .port_set_policy = mv88e6352_port_set_policy, 4688 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4689 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4690 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4691 .port_set_ether_type = mv88e6351_port_set_ether_type, 4692 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4693 .port_pause_limit = mv88e6390_port_pause_limit, 4694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4696 .port_get_cmode = mv88e6352_port_get_cmode, 4697 .port_set_cmode = mv88e6390x_port_set_cmode, 4698 .port_setup_message_port = mv88e6xxx_setup_message_port, 4699 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4700 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4701 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4702 .stats_get_strings = mv88e6320_stats_get_strings, 4703 .stats_get_stats = mv88e6390_stats_get_stats, 4704 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4705 .set_egress_port = mv88e6390_g1_set_egress_port, 4706 .watchdog_ops = &mv88e6390_watchdog_ops, 4707 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4708 .pot_clear = mv88e6xxx_g2_pot_clear, 4709 .reset = mv88e6352_g1_reset, 4710 .rmu_disable = mv88e6390_g1_rmu_disable, 4711 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4712 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4713 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4714 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4715 .serdes_power = mv88e6390_serdes_power, 4716 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4717 /* Check status register pause & lpa register */ 4718 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4719 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4720 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4721 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4722 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4723 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4724 .serdes_irq_status = mv88e6390_serdes_irq_status, 4725 .serdes_get_strings = mv88e6390_serdes_get_strings, 4726 .serdes_get_stats = mv88e6390_serdes_get_stats, 4727 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4728 .serdes_get_regs = mv88e6390_serdes_get_regs, 4729 .gpio_ops = &mv88e6352_gpio_ops, 4730 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4731 }; 4732 4733 static const struct mv88e6xxx_ops mv88e6191_ops = { 4734 /* MV88E6XXX_FAMILY_6390 */ 4735 .setup_errata = mv88e6390_setup_errata, 4736 .irl_init_all = mv88e6390_g2_irl_init_all, 4737 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4738 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4740 .phy_read = mv88e6xxx_g2_smi_phy_read, 4741 .phy_write = mv88e6xxx_g2_smi_phy_write, 4742 .port_set_link = mv88e6xxx_port_set_link, 4743 .port_sync_link = mv88e6xxx_port_sync_link, 4744 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4745 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4746 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4747 .port_tag_remap = mv88e6390_port_tag_remap, 4748 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4749 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4750 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4751 .port_set_ether_type = mv88e6351_port_set_ether_type, 4752 .port_pause_limit = mv88e6390_port_pause_limit, 4753 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4754 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4755 .port_get_cmode = mv88e6352_port_get_cmode, 4756 .port_set_cmode = mv88e6390_port_set_cmode, 4757 .port_setup_message_port = mv88e6xxx_setup_message_port, 4758 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4759 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4760 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4761 .stats_get_strings = mv88e6320_stats_get_strings, 4762 .stats_get_stats = mv88e6390_stats_get_stats, 4763 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4764 .set_egress_port = mv88e6390_g1_set_egress_port, 4765 .watchdog_ops = &mv88e6390_watchdog_ops, 4766 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4767 .pot_clear = mv88e6xxx_g2_pot_clear, 4768 .reset = mv88e6352_g1_reset, 4769 .rmu_disable = mv88e6390_g1_rmu_disable, 4770 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4771 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4772 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4773 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4774 .serdes_power = mv88e6390_serdes_power, 4775 .serdes_get_lane = mv88e6390_serdes_get_lane, 4776 /* Check status register pause & lpa register */ 4777 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4778 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4779 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4780 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4781 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4782 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4783 .serdes_irq_status = mv88e6390_serdes_irq_status, 4784 .serdes_get_strings = mv88e6390_serdes_get_strings, 4785 .serdes_get_stats = mv88e6390_serdes_get_stats, 4786 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4787 .serdes_get_regs = mv88e6390_serdes_get_regs, 4788 .avb_ops = &mv88e6390_avb_ops, 4789 .ptp_ops = &mv88e6352_ptp_ops, 4790 .phylink_get_caps = mv88e6390_phylink_get_caps, 4791 }; 4792 4793 static const struct mv88e6xxx_ops mv88e6240_ops = { 4794 /* MV88E6XXX_FAMILY_6352 */ 4795 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4796 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4797 .irl_init_all = mv88e6352_g2_irl_init_all, 4798 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4799 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4800 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4801 .phy_read = mv88e6xxx_g2_smi_phy_read, 4802 .phy_write = mv88e6xxx_g2_smi_phy_write, 4803 .port_set_link = mv88e6xxx_port_set_link, 4804 .port_sync_link = mv88e6xxx_port_sync_link, 4805 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4806 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4807 .port_tag_remap = mv88e6095_port_tag_remap, 4808 .port_set_policy = mv88e6352_port_set_policy, 4809 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4810 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4811 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4812 .port_set_ether_type = mv88e6351_port_set_ether_type, 4813 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4814 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4815 .port_pause_limit = mv88e6097_port_pause_limit, 4816 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4817 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4818 .port_get_cmode = mv88e6352_port_get_cmode, 4819 .port_setup_message_port = mv88e6xxx_setup_message_port, 4820 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4821 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4822 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4823 .stats_get_strings = mv88e6095_stats_get_strings, 4824 .stats_get_stats = mv88e6095_stats_get_stats, 4825 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4826 .set_egress_port = mv88e6095_g1_set_egress_port, 4827 .watchdog_ops = &mv88e6097_watchdog_ops, 4828 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4829 .pot_clear = mv88e6xxx_g2_pot_clear, 4830 .reset = mv88e6352_g1_reset, 4831 .rmu_disable = mv88e6352_g1_rmu_disable, 4832 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4833 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4834 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4835 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4836 .serdes_get_lane = mv88e6352_serdes_get_lane, 4837 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4838 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4839 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4840 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4841 .serdes_power = mv88e6352_serdes_power, 4842 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4843 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4844 .serdes_irq_status = mv88e6352_serdes_irq_status, 4845 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4846 .serdes_get_regs = mv88e6352_serdes_get_regs, 4847 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4848 .gpio_ops = &mv88e6352_gpio_ops, 4849 .avb_ops = &mv88e6352_avb_ops, 4850 .ptp_ops = &mv88e6352_ptp_ops, 4851 .phylink_get_caps = mv88e6352_phylink_get_caps, 4852 }; 4853 4854 static const struct mv88e6xxx_ops mv88e6250_ops = { 4855 /* MV88E6XXX_FAMILY_6250 */ 4856 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4857 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4858 .irl_init_all = mv88e6352_g2_irl_init_all, 4859 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4860 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4861 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4862 .phy_read = mv88e6xxx_g2_smi_phy_read, 4863 .phy_write = mv88e6xxx_g2_smi_phy_write, 4864 .port_set_link = mv88e6xxx_port_set_link, 4865 .port_sync_link = mv88e6xxx_port_sync_link, 4866 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4867 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4868 .port_tag_remap = mv88e6095_port_tag_remap, 4869 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4870 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4871 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4872 .port_set_ether_type = mv88e6351_port_set_ether_type, 4873 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4874 .port_pause_limit = mv88e6097_port_pause_limit, 4875 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4876 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4877 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4878 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4879 .stats_get_strings = mv88e6250_stats_get_strings, 4880 .stats_get_stats = mv88e6250_stats_get_stats, 4881 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4882 .set_egress_port = mv88e6095_g1_set_egress_port, 4883 .watchdog_ops = &mv88e6250_watchdog_ops, 4884 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4885 .pot_clear = mv88e6xxx_g2_pot_clear, 4886 .reset = mv88e6250_g1_reset, 4887 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4888 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4889 .avb_ops = &mv88e6352_avb_ops, 4890 .ptp_ops = &mv88e6250_ptp_ops, 4891 .phylink_get_caps = mv88e6250_phylink_get_caps, 4892 }; 4893 4894 static const struct mv88e6xxx_ops mv88e6290_ops = { 4895 /* MV88E6XXX_FAMILY_6390 */ 4896 .setup_errata = mv88e6390_setup_errata, 4897 .irl_init_all = mv88e6390_g2_irl_init_all, 4898 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4899 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4901 .phy_read = mv88e6xxx_g2_smi_phy_read, 4902 .phy_write = mv88e6xxx_g2_smi_phy_write, 4903 .port_set_link = mv88e6xxx_port_set_link, 4904 .port_sync_link = mv88e6xxx_port_sync_link, 4905 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4906 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4907 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4908 .port_tag_remap = mv88e6390_port_tag_remap, 4909 .port_set_policy = mv88e6352_port_set_policy, 4910 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4911 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4912 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4913 .port_set_ether_type = mv88e6351_port_set_ether_type, 4914 .port_pause_limit = mv88e6390_port_pause_limit, 4915 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4916 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4917 .port_get_cmode = mv88e6352_port_get_cmode, 4918 .port_set_cmode = mv88e6390_port_set_cmode, 4919 .port_setup_message_port = mv88e6xxx_setup_message_port, 4920 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4921 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4922 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4923 .stats_get_strings = mv88e6320_stats_get_strings, 4924 .stats_get_stats = mv88e6390_stats_get_stats, 4925 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4926 .set_egress_port = mv88e6390_g1_set_egress_port, 4927 .watchdog_ops = &mv88e6390_watchdog_ops, 4928 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4929 .pot_clear = mv88e6xxx_g2_pot_clear, 4930 .reset = mv88e6352_g1_reset, 4931 .rmu_disable = mv88e6390_g1_rmu_disable, 4932 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4933 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4934 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4935 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4936 .serdes_power = mv88e6390_serdes_power, 4937 .serdes_get_lane = mv88e6390_serdes_get_lane, 4938 /* Check status register pause & lpa register */ 4939 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4940 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4941 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4942 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4943 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4944 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4945 .serdes_irq_status = mv88e6390_serdes_irq_status, 4946 .serdes_get_strings = mv88e6390_serdes_get_strings, 4947 .serdes_get_stats = mv88e6390_serdes_get_stats, 4948 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4949 .serdes_get_regs = mv88e6390_serdes_get_regs, 4950 .gpio_ops = &mv88e6352_gpio_ops, 4951 .avb_ops = &mv88e6390_avb_ops, 4952 .ptp_ops = &mv88e6352_ptp_ops, 4953 .phylink_get_caps = mv88e6390_phylink_get_caps, 4954 }; 4955 4956 static const struct mv88e6xxx_ops mv88e6320_ops = { 4957 /* MV88E6XXX_FAMILY_6320 */ 4958 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4959 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4960 .irl_init_all = mv88e6352_g2_irl_init_all, 4961 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4962 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4963 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4964 .phy_read = mv88e6xxx_g2_smi_phy_read, 4965 .phy_write = mv88e6xxx_g2_smi_phy_write, 4966 .port_set_link = mv88e6xxx_port_set_link, 4967 .port_sync_link = mv88e6xxx_port_sync_link, 4968 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4969 .port_tag_remap = mv88e6095_port_tag_remap, 4970 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4971 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4972 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4973 .port_set_ether_type = mv88e6351_port_set_ether_type, 4974 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4975 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4976 .port_pause_limit = mv88e6097_port_pause_limit, 4977 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4978 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4979 .port_get_cmode = mv88e6352_port_get_cmode, 4980 .port_setup_message_port = mv88e6xxx_setup_message_port, 4981 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4982 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4983 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4984 .stats_get_strings = mv88e6320_stats_get_strings, 4985 .stats_get_stats = mv88e6320_stats_get_stats, 4986 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4987 .set_egress_port = mv88e6095_g1_set_egress_port, 4988 .watchdog_ops = &mv88e6390_watchdog_ops, 4989 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4990 .pot_clear = mv88e6xxx_g2_pot_clear, 4991 .reset = mv88e6352_g1_reset, 4992 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4993 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4994 .gpio_ops = &mv88e6352_gpio_ops, 4995 .avb_ops = &mv88e6352_avb_ops, 4996 .ptp_ops = &mv88e6352_ptp_ops, 4997 .phylink_get_caps = mv88e6185_phylink_get_caps, 4998 }; 4999 5000 static const struct mv88e6xxx_ops mv88e6321_ops = { 5001 /* MV88E6XXX_FAMILY_6320 */ 5002 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5003 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5004 .irl_init_all = mv88e6352_g2_irl_init_all, 5005 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5006 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5007 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5008 .phy_read = mv88e6xxx_g2_smi_phy_read, 5009 .phy_write = mv88e6xxx_g2_smi_phy_write, 5010 .port_set_link = mv88e6xxx_port_set_link, 5011 .port_sync_link = mv88e6xxx_port_sync_link, 5012 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5013 .port_tag_remap = mv88e6095_port_tag_remap, 5014 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5015 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5016 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5017 .port_set_ether_type = mv88e6351_port_set_ether_type, 5018 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5019 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5020 .port_pause_limit = mv88e6097_port_pause_limit, 5021 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5022 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5023 .port_get_cmode = mv88e6352_port_get_cmode, 5024 .port_setup_message_port = mv88e6xxx_setup_message_port, 5025 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5026 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5027 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5028 .stats_get_strings = mv88e6320_stats_get_strings, 5029 .stats_get_stats = mv88e6320_stats_get_stats, 5030 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5031 .set_egress_port = mv88e6095_g1_set_egress_port, 5032 .watchdog_ops = &mv88e6390_watchdog_ops, 5033 .reset = mv88e6352_g1_reset, 5034 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5035 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5036 .gpio_ops = &mv88e6352_gpio_ops, 5037 .avb_ops = &mv88e6352_avb_ops, 5038 .ptp_ops = &mv88e6352_ptp_ops, 5039 .phylink_get_caps = mv88e6185_phylink_get_caps, 5040 }; 5041 5042 static const struct mv88e6xxx_ops mv88e6341_ops = { 5043 /* MV88E6XXX_FAMILY_6341 */ 5044 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5045 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5046 .irl_init_all = mv88e6352_g2_irl_init_all, 5047 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5048 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5049 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5050 .phy_read = mv88e6xxx_g2_smi_phy_read, 5051 .phy_write = mv88e6xxx_g2_smi_phy_write, 5052 .port_set_link = mv88e6xxx_port_set_link, 5053 .port_sync_link = mv88e6xxx_port_sync_link, 5054 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5055 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5056 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5057 .port_tag_remap = mv88e6095_port_tag_remap, 5058 .port_set_policy = mv88e6352_port_set_policy, 5059 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5060 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5061 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5062 .port_set_ether_type = mv88e6351_port_set_ether_type, 5063 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5064 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5065 .port_pause_limit = mv88e6097_port_pause_limit, 5066 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5067 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5068 .port_get_cmode = mv88e6352_port_get_cmode, 5069 .port_set_cmode = mv88e6341_port_set_cmode, 5070 .port_setup_message_port = mv88e6xxx_setup_message_port, 5071 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5072 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5073 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5074 .stats_get_strings = mv88e6320_stats_get_strings, 5075 .stats_get_stats = mv88e6390_stats_get_stats, 5076 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5077 .set_egress_port = mv88e6390_g1_set_egress_port, 5078 .watchdog_ops = &mv88e6390_watchdog_ops, 5079 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5080 .pot_clear = mv88e6xxx_g2_pot_clear, 5081 .reset = mv88e6352_g1_reset, 5082 .rmu_disable = mv88e6390_g1_rmu_disable, 5083 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5084 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5085 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5086 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5087 .serdes_power = mv88e6390_serdes_power, 5088 .serdes_get_lane = mv88e6341_serdes_get_lane, 5089 /* Check status register pause & lpa register */ 5090 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5091 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5092 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5093 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5094 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5095 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5096 .serdes_irq_status = mv88e6390_serdes_irq_status, 5097 .gpio_ops = &mv88e6352_gpio_ops, 5098 .avb_ops = &mv88e6390_avb_ops, 5099 .ptp_ops = &mv88e6352_ptp_ops, 5100 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5101 .serdes_get_strings = mv88e6390_serdes_get_strings, 5102 .serdes_get_stats = mv88e6390_serdes_get_stats, 5103 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5104 .serdes_get_regs = mv88e6390_serdes_get_regs, 5105 .phylink_get_caps = mv88e6341_phylink_get_caps, 5106 }; 5107 5108 static const struct mv88e6xxx_ops mv88e6350_ops = { 5109 /* MV88E6XXX_FAMILY_6351 */ 5110 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5111 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5112 .irl_init_all = mv88e6352_g2_irl_init_all, 5113 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5114 .phy_read = mv88e6xxx_g2_smi_phy_read, 5115 .phy_write = mv88e6xxx_g2_smi_phy_write, 5116 .port_set_link = mv88e6xxx_port_set_link, 5117 .port_sync_link = mv88e6xxx_port_sync_link, 5118 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5119 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5120 .port_tag_remap = mv88e6095_port_tag_remap, 5121 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5122 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5123 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5124 .port_set_ether_type = mv88e6351_port_set_ether_type, 5125 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5126 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5127 .port_pause_limit = mv88e6097_port_pause_limit, 5128 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5129 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5130 .port_get_cmode = mv88e6352_port_get_cmode, 5131 .port_setup_message_port = mv88e6xxx_setup_message_port, 5132 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5133 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5134 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5135 .stats_get_strings = mv88e6095_stats_get_strings, 5136 .stats_get_stats = mv88e6095_stats_get_stats, 5137 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5138 .set_egress_port = mv88e6095_g1_set_egress_port, 5139 .watchdog_ops = &mv88e6097_watchdog_ops, 5140 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5141 .pot_clear = mv88e6xxx_g2_pot_clear, 5142 .reset = mv88e6352_g1_reset, 5143 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5144 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5145 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5146 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5147 .phylink_get_caps = mv88e6185_phylink_get_caps, 5148 }; 5149 5150 static const struct mv88e6xxx_ops mv88e6351_ops = { 5151 /* MV88E6XXX_FAMILY_6351 */ 5152 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5153 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5154 .irl_init_all = mv88e6352_g2_irl_init_all, 5155 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5156 .phy_read = mv88e6xxx_g2_smi_phy_read, 5157 .phy_write = mv88e6xxx_g2_smi_phy_write, 5158 .port_set_link = mv88e6xxx_port_set_link, 5159 .port_sync_link = mv88e6xxx_port_sync_link, 5160 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5161 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5162 .port_tag_remap = mv88e6095_port_tag_remap, 5163 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5164 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5165 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5166 .port_set_ether_type = mv88e6351_port_set_ether_type, 5167 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5168 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5169 .port_pause_limit = mv88e6097_port_pause_limit, 5170 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5171 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5172 .port_get_cmode = mv88e6352_port_get_cmode, 5173 .port_setup_message_port = mv88e6xxx_setup_message_port, 5174 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5175 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5176 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5177 .stats_get_strings = mv88e6095_stats_get_strings, 5178 .stats_get_stats = mv88e6095_stats_get_stats, 5179 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5180 .set_egress_port = mv88e6095_g1_set_egress_port, 5181 .watchdog_ops = &mv88e6097_watchdog_ops, 5182 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5183 .pot_clear = mv88e6xxx_g2_pot_clear, 5184 .reset = mv88e6352_g1_reset, 5185 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5186 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5187 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5188 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5189 .avb_ops = &mv88e6352_avb_ops, 5190 .ptp_ops = &mv88e6352_ptp_ops, 5191 .phylink_get_caps = mv88e6185_phylink_get_caps, 5192 }; 5193 5194 static const struct mv88e6xxx_ops mv88e6352_ops = { 5195 /* MV88E6XXX_FAMILY_6352 */ 5196 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5197 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5198 .irl_init_all = mv88e6352_g2_irl_init_all, 5199 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5200 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5201 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5202 .phy_read = mv88e6xxx_g2_smi_phy_read, 5203 .phy_write = mv88e6xxx_g2_smi_phy_write, 5204 .port_set_link = mv88e6xxx_port_set_link, 5205 .port_sync_link = mv88e6xxx_port_sync_link, 5206 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5207 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5208 .port_tag_remap = mv88e6095_port_tag_remap, 5209 .port_set_policy = mv88e6352_port_set_policy, 5210 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5211 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5212 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5213 .port_set_ether_type = mv88e6351_port_set_ether_type, 5214 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5215 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5216 .port_pause_limit = mv88e6097_port_pause_limit, 5217 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5218 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5219 .port_get_cmode = mv88e6352_port_get_cmode, 5220 .port_setup_message_port = mv88e6xxx_setup_message_port, 5221 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5223 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5224 .stats_get_strings = mv88e6095_stats_get_strings, 5225 .stats_get_stats = mv88e6095_stats_get_stats, 5226 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5227 .set_egress_port = mv88e6095_g1_set_egress_port, 5228 .watchdog_ops = &mv88e6097_watchdog_ops, 5229 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5230 .pot_clear = mv88e6xxx_g2_pot_clear, 5231 .reset = mv88e6352_g1_reset, 5232 .rmu_disable = mv88e6352_g1_rmu_disable, 5233 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5234 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5235 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5236 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5237 .stu_getnext = mv88e6352_g1_stu_getnext, 5238 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5239 .serdes_get_lane = mv88e6352_serdes_get_lane, 5240 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5241 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5242 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5243 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5244 .serdes_power = mv88e6352_serdes_power, 5245 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5246 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5247 .serdes_irq_status = mv88e6352_serdes_irq_status, 5248 .gpio_ops = &mv88e6352_gpio_ops, 5249 .avb_ops = &mv88e6352_avb_ops, 5250 .ptp_ops = &mv88e6352_ptp_ops, 5251 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5252 .serdes_get_strings = mv88e6352_serdes_get_strings, 5253 .serdes_get_stats = mv88e6352_serdes_get_stats, 5254 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5255 .serdes_get_regs = mv88e6352_serdes_get_regs, 5256 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5257 .phylink_get_caps = mv88e6352_phylink_get_caps, 5258 }; 5259 5260 static const struct mv88e6xxx_ops mv88e6390_ops = { 5261 /* MV88E6XXX_FAMILY_6390 */ 5262 .setup_errata = mv88e6390_setup_errata, 5263 .irl_init_all = mv88e6390_g2_irl_init_all, 5264 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5265 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5266 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5267 .phy_read = mv88e6xxx_g2_smi_phy_read, 5268 .phy_write = mv88e6xxx_g2_smi_phy_write, 5269 .port_set_link = mv88e6xxx_port_set_link, 5270 .port_sync_link = mv88e6xxx_port_sync_link, 5271 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5272 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5273 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5274 .port_tag_remap = mv88e6390_port_tag_remap, 5275 .port_set_policy = mv88e6352_port_set_policy, 5276 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5277 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5278 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5279 .port_set_ether_type = mv88e6351_port_set_ether_type, 5280 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5281 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5282 .port_pause_limit = mv88e6390_port_pause_limit, 5283 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5284 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5285 .port_get_cmode = mv88e6352_port_get_cmode, 5286 .port_set_cmode = mv88e6390_port_set_cmode, 5287 .port_setup_message_port = mv88e6xxx_setup_message_port, 5288 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5289 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5290 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5291 .stats_get_strings = mv88e6320_stats_get_strings, 5292 .stats_get_stats = mv88e6390_stats_get_stats, 5293 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5294 .set_egress_port = mv88e6390_g1_set_egress_port, 5295 .watchdog_ops = &mv88e6390_watchdog_ops, 5296 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5297 .pot_clear = mv88e6xxx_g2_pot_clear, 5298 .reset = mv88e6352_g1_reset, 5299 .rmu_disable = mv88e6390_g1_rmu_disable, 5300 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5301 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5302 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5303 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5304 .stu_getnext = mv88e6390_g1_stu_getnext, 5305 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5306 .serdes_power = mv88e6390_serdes_power, 5307 .serdes_get_lane = mv88e6390_serdes_get_lane, 5308 /* Check status register pause & lpa register */ 5309 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5310 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5311 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5312 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5313 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5314 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5315 .serdes_irq_status = mv88e6390_serdes_irq_status, 5316 .gpio_ops = &mv88e6352_gpio_ops, 5317 .avb_ops = &mv88e6390_avb_ops, 5318 .ptp_ops = &mv88e6352_ptp_ops, 5319 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5320 .serdes_get_strings = mv88e6390_serdes_get_strings, 5321 .serdes_get_stats = mv88e6390_serdes_get_stats, 5322 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5323 .serdes_get_regs = mv88e6390_serdes_get_regs, 5324 .phylink_get_caps = mv88e6390_phylink_get_caps, 5325 }; 5326 5327 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5328 /* MV88E6XXX_FAMILY_6390 */ 5329 .setup_errata = mv88e6390_setup_errata, 5330 .irl_init_all = mv88e6390_g2_irl_init_all, 5331 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5332 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5333 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5334 .phy_read = mv88e6xxx_g2_smi_phy_read, 5335 .phy_write = mv88e6xxx_g2_smi_phy_write, 5336 .port_set_link = mv88e6xxx_port_set_link, 5337 .port_sync_link = mv88e6xxx_port_sync_link, 5338 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5339 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5340 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5341 .port_tag_remap = mv88e6390_port_tag_remap, 5342 .port_set_policy = mv88e6352_port_set_policy, 5343 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5344 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5345 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5346 .port_set_ether_type = mv88e6351_port_set_ether_type, 5347 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5348 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5349 .port_pause_limit = mv88e6390_port_pause_limit, 5350 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5351 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5352 .port_get_cmode = mv88e6352_port_get_cmode, 5353 .port_set_cmode = mv88e6390x_port_set_cmode, 5354 .port_setup_message_port = mv88e6xxx_setup_message_port, 5355 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5356 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5357 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5358 .stats_get_strings = mv88e6320_stats_get_strings, 5359 .stats_get_stats = mv88e6390_stats_get_stats, 5360 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5361 .set_egress_port = mv88e6390_g1_set_egress_port, 5362 .watchdog_ops = &mv88e6390_watchdog_ops, 5363 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5364 .pot_clear = mv88e6xxx_g2_pot_clear, 5365 .reset = mv88e6352_g1_reset, 5366 .rmu_disable = mv88e6390_g1_rmu_disable, 5367 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5368 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5369 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5370 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5371 .stu_getnext = mv88e6390_g1_stu_getnext, 5372 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5373 .serdes_power = mv88e6390_serdes_power, 5374 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5375 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5376 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5377 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5378 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5379 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5380 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5381 .serdes_irq_status = mv88e6390_serdes_irq_status, 5382 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5383 .serdes_get_strings = mv88e6390_serdes_get_strings, 5384 .serdes_get_stats = mv88e6390_serdes_get_stats, 5385 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5386 .serdes_get_regs = mv88e6390_serdes_get_regs, 5387 .gpio_ops = &mv88e6352_gpio_ops, 5388 .avb_ops = &mv88e6390_avb_ops, 5389 .ptp_ops = &mv88e6352_ptp_ops, 5390 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5391 }; 5392 5393 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5394 /* MV88E6XXX_FAMILY_6393 */ 5395 .setup_errata = mv88e6393x_serdes_setup_errata, 5396 .irl_init_all = mv88e6390_g2_irl_init_all, 5397 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5398 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5399 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5400 .phy_read = mv88e6xxx_g2_smi_phy_read, 5401 .phy_write = mv88e6xxx_g2_smi_phy_write, 5402 .port_set_link = mv88e6xxx_port_set_link, 5403 .port_sync_link = mv88e6xxx_port_sync_link, 5404 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5405 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5406 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5407 .port_tag_remap = mv88e6390_port_tag_remap, 5408 .port_set_policy = mv88e6393x_port_set_policy, 5409 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5410 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5411 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5412 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5413 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5414 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5415 .port_pause_limit = mv88e6390_port_pause_limit, 5416 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5417 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5418 .port_get_cmode = mv88e6352_port_get_cmode, 5419 .port_set_cmode = mv88e6393x_port_set_cmode, 5420 .port_setup_message_port = mv88e6xxx_setup_message_port, 5421 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5422 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5423 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5424 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5425 .stats_get_strings = mv88e6320_stats_get_strings, 5426 .stats_get_stats = mv88e6390_stats_get_stats, 5427 /* .set_cpu_port is missing because this family does not support a global 5428 * CPU port, only per port CPU port which is set via 5429 * .port_set_upstream_port method. 5430 */ 5431 .set_egress_port = mv88e6393x_set_egress_port, 5432 .watchdog_ops = &mv88e6390_watchdog_ops, 5433 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5434 .pot_clear = mv88e6xxx_g2_pot_clear, 5435 .reset = mv88e6352_g1_reset, 5436 .rmu_disable = mv88e6390_g1_rmu_disable, 5437 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5438 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5439 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5440 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5441 .stu_getnext = mv88e6390_g1_stu_getnext, 5442 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5443 .serdes_power = mv88e6393x_serdes_power, 5444 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5445 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5446 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5447 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5448 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5449 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5450 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5451 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5452 /* TODO: serdes stats */ 5453 .gpio_ops = &mv88e6352_gpio_ops, 5454 .avb_ops = &mv88e6390_avb_ops, 5455 .ptp_ops = &mv88e6352_ptp_ops, 5456 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5457 }; 5458 5459 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5460 [MV88E6085] = { 5461 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5462 .family = MV88E6XXX_FAMILY_6097, 5463 .name = "Marvell 88E6085", 5464 .num_databases = 4096, 5465 .num_macs = 8192, 5466 .num_ports = 10, 5467 .num_internal_phys = 5, 5468 .max_vid = 4095, 5469 .port_base_addr = 0x10, 5470 .phy_base_addr = 0x0, 5471 .global1_addr = 0x1b, 5472 .global2_addr = 0x1c, 5473 .age_time_coeff = 15000, 5474 .g1_irqs = 8, 5475 .g2_irqs = 10, 5476 .atu_move_port_mask = 0xf, 5477 .pvt = true, 5478 .multi_chip = true, 5479 .ops = &mv88e6085_ops, 5480 }, 5481 5482 [MV88E6095] = { 5483 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5484 .family = MV88E6XXX_FAMILY_6095, 5485 .name = "Marvell 88E6095/88E6095F", 5486 .num_databases = 256, 5487 .num_macs = 8192, 5488 .num_ports = 11, 5489 .num_internal_phys = 0, 5490 .max_vid = 4095, 5491 .port_base_addr = 0x10, 5492 .phy_base_addr = 0x0, 5493 .global1_addr = 0x1b, 5494 .global2_addr = 0x1c, 5495 .age_time_coeff = 15000, 5496 .g1_irqs = 8, 5497 .atu_move_port_mask = 0xf, 5498 .multi_chip = true, 5499 .ops = &mv88e6095_ops, 5500 }, 5501 5502 [MV88E6097] = { 5503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5504 .family = MV88E6XXX_FAMILY_6097, 5505 .name = "Marvell 88E6097/88E6097F", 5506 .num_databases = 4096, 5507 .num_macs = 8192, 5508 .num_ports = 11, 5509 .num_internal_phys = 8, 5510 .max_vid = 4095, 5511 .max_sid = 63, 5512 .port_base_addr = 0x10, 5513 .phy_base_addr = 0x0, 5514 .global1_addr = 0x1b, 5515 .global2_addr = 0x1c, 5516 .age_time_coeff = 15000, 5517 .g1_irqs = 8, 5518 .g2_irqs = 10, 5519 .atu_move_port_mask = 0xf, 5520 .pvt = true, 5521 .multi_chip = true, 5522 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5523 .ops = &mv88e6097_ops, 5524 }, 5525 5526 [MV88E6123] = { 5527 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5528 .family = MV88E6XXX_FAMILY_6165, 5529 .name = "Marvell 88E6123", 5530 .num_databases = 4096, 5531 .num_macs = 1024, 5532 .num_ports = 3, 5533 .num_internal_phys = 5, 5534 .max_vid = 4095, 5535 .port_base_addr = 0x10, 5536 .phy_base_addr = 0x0, 5537 .global1_addr = 0x1b, 5538 .global2_addr = 0x1c, 5539 .age_time_coeff = 15000, 5540 .g1_irqs = 9, 5541 .g2_irqs = 10, 5542 .atu_move_port_mask = 0xf, 5543 .pvt = true, 5544 .multi_chip = true, 5545 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5546 .ops = &mv88e6123_ops, 5547 }, 5548 5549 [MV88E6131] = { 5550 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5551 .family = MV88E6XXX_FAMILY_6185, 5552 .name = "Marvell 88E6131", 5553 .num_databases = 256, 5554 .num_macs = 8192, 5555 .num_ports = 8, 5556 .num_internal_phys = 0, 5557 .max_vid = 4095, 5558 .port_base_addr = 0x10, 5559 .phy_base_addr = 0x0, 5560 .global1_addr = 0x1b, 5561 .global2_addr = 0x1c, 5562 .age_time_coeff = 15000, 5563 .g1_irqs = 9, 5564 .atu_move_port_mask = 0xf, 5565 .multi_chip = true, 5566 .ops = &mv88e6131_ops, 5567 }, 5568 5569 [MV88E6141] = { 5570 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5571 .family = MV88E6XXX_FAMILY_6341, 5572 .name = "Marvell 88E6141", 5573 .num_databases = 4096, 5574 .num_macs = 2048, 5575 .num_ports = 6, 5576 .num_internal_phys = 5, 5577 .num_gpio = 11, 5578 .max_vid = 4095, 5579 .port_base_addr = 0x10, 5580 .phy_base_addr = 0x10, 5581 .global1_addr = 0x1b, 5582 .global2_addr = 0x1c, 5583 .age_time_coeff = 3750, 5584 .atu_move_port_mask = 0x1f, 5585 .g1_irqs = 9, 5586 .g2_irqs = 10, 5587 .pvt = true, 5588 .multi_chip = true, 5589 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5590 .ops = &mv88e6141_ops, 5591 }, 5592 5593 [MV88E6161] = { 5594 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5595 .family = MV88E6XXX_FAMILY_6165, 5596 .name = "Marvell 88E6161", 5597 .num_databases = 4096, 5598 .num_macs = 1024, 5599 .num_ports = 6, 5600 .num_internal_phys = 5, 5601 .max_vid = 4095, 5602 .port_base_addr = 0x10, 5603 .phy_base_addr = 0x0, 5604 .global1_addr = 0x1b, 5605 .global2_addr = 0x1c, 5606 .age_time_coeff = 15000, 5607 .g1_irqs = 9, 5608 .g2_irqs = 10, 5609 .atu_move_port_mask = 0xf, 5610 .pvt = true, 5611 .multi_chip = true, 5612 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5613 .ptp_support = true, 5614 .ops = &mv88e6161_ops, 5615 }, 5616 5617 [MV88E6165] = { 5618 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5619 .family = MV88E6XXX_FAMILY_6165, 5620 .name = "Marvell 88E6165", 5621 .num_databases = 4096, 5622 .num_macs = 8192, 5623 .num_ports = 6, 5624 .num_internal_phys = 0, 5625 .max_vid = 4095, 5626 .port_base_addr = 0x10, 5627 .phy_base_addr = 0x0, 5628 .global1_addr = 0x1b, 5629 .global2_addr = 0x1c, 5630 .age_time_coeff = 15000, 5631 .g1_irqs = 9, 5632 .g2_irqs = 10, 5633 .atu_move_port_mask = 0xf, 5634 .pvt = true, 5635 .multi_chip = true, 5636 .ptp_support = true, 5637 .ops = &mv88e6165_ops, 5638 }, 5639 5640 [MV88E6171] = { 5641 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5642 .family = MV88E6XXX_FAMILY_6351, 5643 .name = "Marvell 88E6171", 5644 .num_databases = 4096, 5645 .num_macs = 8192, 5646 .num_ports = 7, 5647 .num_internal_phys = 5, 5648 .max_vid = 4095, 5649 .port_base_addr = 0x10, 5650 .phy_base_addr = 0x0, 5651 .global1_addr = 0x1b, 5652 .global2_addr = 0x1c, 5653 .age_time_coeff = 15000, 5654 .g1_irqs = 9, 5655 .g2_irqs = 10, 5656 .atu_move_port_mask = 0xf, 5657 .pvt = true, 5658 .multi_chip = true, 5659 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5660 .ops = &mv88e6171_ops, 5661 }, 5662 5663 [MV88E6172] = { 5664 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5665 .family = MV88E6XXX_FAMILY_6352, 5666 .name = "Marvell 88E6172", 5667 .num_databases = 4096, 5668 .num_macs = 8192, 5669 .num_ports = 7, 5670 .num_internal_phys = 5, 5671 .num_gpio = 15, 5672 .max_vid = 4095, 5673 .port_base_addr = 0x10, 5674 .phy_base_addr = 0x0, 5675 .global1_addr = 0x1b, 5676 .global2_addr = 0x1c, 5677 .age_time_coeff = 15000, 5678 .g1_irqs = 9, 5679 .g2_irqs = 10, 5680 .atu_move_port_mask = 0xf, 5681 .pvt = true, 5682 .multi_chip = true, 5683 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5684 .ops = &mv88e6172_ops, 5685 }, 5686 5687 [MV88E6175] = { 5688 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5689 .family = MV88E6XXX_FAMILY_6351, 5690 .name = "Marvell 88E6175", 5691 .num_databases = 4096, 5692 .num_macs = 8192, 5693 .num_ports = 7, 5694 .num_internal_phys = 5, 5695 .max_vid = 4095, 5696 .port_base_addr = 0x10, 5697 .phy_base_addr = 0x0, 5698 .global1_addr = 0x1b, 5699 .global2_addr = 0x1c, 5700 .age_time_coeff = 15000, 5701 .g1_irqs = 9, 5702 .g2_irqs = 10, 5703 .atu_move_port_mask = 0xf, 5704 .pvt = true, 5705 .multi_chip = true, 5706 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5707 .ops = &mv88e6175_ops, 5708 }, 5709 5710 [MV88E6176] = { 5711 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5712 .family = MV88E6XXX_FAMILY_6352, 5713 .name = "Marvell 88E6176", 5714 .num_databases = 4096, 5715 .num_macs = 8192, 5716 .num_ports = 7, 5717 .num_internal_phys = 5, 5718 .num_gpio = 15, 5719 .max_vid = 4095, 5720 .port_base_addr = 0x10, 5721 .phy_base_addr = 0x0, 5722 .global1_addr = 0x1b, 5723 .global2_addr = 0x1c, 5724 .age_time_coeff = 15000, 5725 .g1_irqs = 9, 5726 .g2_irqs = 10, 5727 .atu_move_port_mask = 0xf, 5728 .pvt = true, 5729 .multi_chip = true, 5730 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5731 .ops = &mv88e6176_ops, 5732 }, 5733 5734 [MV88E6185] = { 5735 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5736 .family = MV88E6XXX_FAMILY_6185, 5737 .name = "Marvell 88E6185", 5738 .num_databases = 256, 5739 .num_macs = 8192, 5740 .num_ports = 10, 5741 .num_internal_phys = 0, 5742 .max_vid = 4095, 5743 .port_base_addr = 0x10, 5744 .phy_base_addr = 0x0, 5745 .global1_addr = 0x1b, 5746 .global2_addr = 0x1c, 5747 .age_time_coeff = 15000, 5748 .g1_irqs = 8, 5749 .atu_move_port_mask = 0xf, 5750 .multi_chip = true, 5751 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5752 .ops = &mv88e6185_ops, 5753 }, 5754 5755 [MV88E6190] = { 5756 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5757 .family = MV88E6XXX_FAMILY_6390, 5758 .name = "Marvell 88E6190", 5759 .num_databases = 4096, 5760 .num_macs = 16384, 5761 .num_ports = 11, /* 10 + Z80 */ 5762 .num_internal_phys = 9, 5763 .num_gpio = 16, 5764 .max_vid = 8191, 5765 .max_sid = 63, 5766 .port_base_addr = 0x0, 5767 .phy_base_addr = 0x0, 5768 .global1_addr = 0x1b, 5769 .global2_addr = 0x1c, 5770 .age_time_coeff = 3750, 5771 .g1_irqs = 9, 5772 .g2_irqs = 14, 5773 .pvt = true, 5774 .multi_chip = true, 5775 .atu_move_port_mask = 0x1f, 5776 .ops = &mv88e6190_ops, 5777 }, 5778 5779 [MV88E6190X] = { 5780 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5781 .family = MV88E6XXX_FAMILY_6390, 5782 .name = "Marvell 88E6190X", 5783 .num_databases = 4096, 5784 .num_macs = 16384, 5785 .num_ports = 11, /* 10 + Z80 */ 5786 .num_internal_phys = 9, 5787 .num_gpio = 16, 5788 .max_vid = 8191, 5789 .max_sid = 63, 5790 .port_base_addr = 0x0, 5791 .phy_base_addr = 0x0, 5792 .global1_addr = 0x1b, 5793 .global2_addr = 0x1c, 5794 .age_time_coeff = 3750, 5795 .g1_irqs = 9, 5796 .g2_irqs = 14, 5797 .atu_move_port_mask = 0x1f, 5798 .pvt = true, 5799 .multi_chip = true, 5800 .ops = &mv88e6190x_ops, 5801 }, 5802 5803 [MV88E6191] = { 5804 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5805 .family = MV88E6XXX_FAMILY_6390, 5806 .name = "Marvell 88E6191", 5807 .num_databases = 4096, 5808 .num_macs = 16384, 5809 .num_ports = 11, /* 10 + Z80 */ 5810 .num_internal_phys = 9, 5811 .max_vid = 8191, 5812 .max_sid = 63, 5813 .port_base_addr = 0x0, 5814 .phy_base_addr = 0x0, 5815 .global1_addr = 0x1b, 5816 .global2_addr = 0x1c, 5817 .age_time_coeff = 3750, 5818 .g1_irqs = 9, 5819 .g2_irqs = 14, 5820 .atu_move_port_mask = 0x1f, 5821 .pvt = true, 5822 .multi_chip = true, 5823 .ptp_support = true, 5824 .ops = &mv88e6191_ops, 5825 }, 5826 5827 [MV88E6191X] = { 5828 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5829 .family = MV88E6XXX_FAMILY_6393, 5830 .name = "Marvell 88E6191X", 5831 .num_databases = 4096, 5832 .num_ports = 11, /* 10 + Z80 */ 5833 .num_internal_phys = 9, 5834 .max_vid = 8191, 5835 .max_sid = 63, 5836 .port_base_addr = 0x0, 5837 .phy_base_addr = 0x0, 5838 .global1_addr = 0x1b, 5839 .global2_addr = 0x1c, 5840 .age_time_coeff = 3750, 5841 .g1_irqs = 10, 5842 .g2_irqs = 14, 5843 .atu_move_port_mask = 0x1f, 5844 .pvt = true, 5845 .multi_chip = true, 5846 .ptp_support = true, 5847 .ops = &mv88e6393x_ops, 5848 }, 5849 5850 [MV88E6193X] = { 5851 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5852 .family = MV88E6XXX_FAMILY_6393, 5853 .name = "Marvell 88E6193X", 5854 .num_databases = 4096, 5855 .num_ports = 11, /* 10 + Z80 */ 5856 .num_internal_phys = 9, 5857 .max_vid = 8191, 5858 .max_sid = 63, 5859 .port_base_addr = 0x0, 5860 .phy_base_addr = 0x0, 5861 .global1_addr = 0x1b, 5862 .global2_addr = 0x1c, 5863 .age_time_coeff = 3750, 5864 .g1_irqs = 10, 5865 .g2_irqs = 14, 5866 .atu_move_port_mask = 0x1f, 5867 .pvt = true, 5868 .multi_chip = true, 5869 .ptp_support = true, 5870 .ops = &mv88e6393x_ops, 5871 }, 5872 5873 [MV88E6220] = { 5874 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5875 .family = MV88E6XXX_FAMILY_6250, 5876 .name = "Marvell 88E6220", 5877 .num_databases = 64, 5878 5879 /* Ports 2-4 are not routed to pins 5880 * => usable ports 0, 1, 5, 6 5881 */ 5882 .num_ports = 7, 5883 .num_internal_phys = 2, 5884 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5885 .max_vid = 4095, 5886 .port_base_addr = 0x08, 5887 .phy_base_addr = 0x00, 5888 .global1_addr = 0x0f, 5889 .global2_addr = 0x07, 5890 .age_time_coeff = 15000, 5891 .g1_irqs = 9, 5892 .g2_irqs = 10, 5893 .atu_move_port_mask = 0xf, 5894 .dual_chip = true, 5895 .ptp_support = true, 5896 .ops = &mv88e6250_ops, 5897 }, 5898 5899 [MV88E6240] = { 5900 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5901 .family = MV88E6XXX_FAMILY_6352, 5902 .name = "Marvell 88E6240", 5903 .num_databases = 4096, 5904 .num_macs = 8192, 5905 .num_ports = 7, 5906 .num_internal_phys = 5, 5907 .num_gpio = 15, 5908 .max_vid = 4095, 5909 .port_base_addr = 0x10, 5910 .phy_base_addr = 0x0, 5911 .global1_addr = 0x1b, 5912 .global2_addr = 0x1c, 5913 .age_time_coeff = 15000, 5914 .g1_irqs = 9, 5915 .g2_irqs = 10, 5916 .atu_move_port_mask = 0xf, 5917 .pvt = true, 5918 .multi_chip = true, 5919 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5920 .ptp_support = true, 5921 .ops = &mv88e6240_ops, 5922 }, 5923 5924 [MV88E6250] = { 5925 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5926 .family = MV88E6XXX_FAMILY_6250, 5927 .name = "Marvell 88E6250", 5928 .num_databases = 64, 5929 .num_ports = 7, 5930 .num_internal_phys = 5, 5931 .max_vid = 4095, 5932 .port_base_addr = 0x08, 5933 .phy_base_addr = 0x00, 5934 .global1_addr = 0x0f, 5935 .global2_addr = 0x07, 5936 .age_time_coeff = 15000, 5937 .g1_irqs = 9, 5938 .g2_irqs = 10, 5939 .atu_move_port_mask = 0xf, 5940 .dual_chip = true, 5941 .ptp_support = true, 5942 .ops = &mv88e6250_ops, 5943 }, 5944 5945 [MV88E6290] = { 5946 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5947 .family = MV88E6XXX_FAMILY_6390, 5948 .name = "Marvell 88E6290", 5949 .num_databases = 4096, 5950 .num_ports = 11, /* 10 + Z80 */ 5951 .num_internal_phys = 9, 5952 .num_gpio = 16, 5953 .max_vid = 8191, 5954 .port_base_addr = 0x0, 5955 .phy_base_addr = 0x0, 5956 .global1_addr = 0x1b, 5957 .global2_addr = 0x1c, 5958 .age_time_coeff = 3750, 5959 .g1_irqs = 9, 5960 .g2_irqs = 14, 5961 .atu_move_port_mask = 0x1f, 5962 .pvt = true, 5963 .multi_chip = true, 5964 .ptp_support = true, 5965 .ops = &mv88e6290_ops, 5966 }, 5967 5968 [MV88E6320] = { 5969 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5970 .family = MV88E6XXX_FAMILY_6320, 5971 .name = "Marvell 88E6320", 5972 .num_databases = 4096, 5973 .num_macs = 8192, 5974 .num_ports = 7, 5975 .num_internal_phys = 5, 5976 .num_gpio = 15, 5977 .max_vid = 4095, 5978 .port_base_addr = 0x10, 5979 .phy_base_addr = 0x0, 5980 .global1_addr = 0x1b, 5981 .global2_addr = 0x1c, 5982 .age_time_coeff = 15000, 5983 .g1_irqs = 8, 5984 .g2_irqs = 10, 5985 .atu_move_port_mask = 0xf, 5986 .pvt = true, 5987 .multi_chip = true, 5988 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5989 .ptp_support = true, 5990 .ops = &mv88e6320_ops, 5991 }, 5992 5993 [MV88E6321] = { 5994 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5995 .family = MV88E6XXX_FAMILY_6320, 5996 .name = "Marvell 88E6321", 5997 .num_databases = 4096, 5998 .num_macs = 8192, 5999 .num_ports = 7, 6000 .num_internal_phys = 5, 6001 .num_gpio = 15, 6002 .max_vid = 4095, 6003 .port_base_addr = 0x10, 6004 .phy_base_addr = 0x0, 6005 .global1_addr = 0x1b, 6006 .global2_addr = 0x1c, 6007 .age_time_coeff = 15000, 6008 .g1_irqs = 8, 6009 .g2_irqs = 10, 6010 .atu_move_port_mask = 0xf, 6011 .multi_chip = true, 6012 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6013 .ptp_support = true, 6014 .ops = &mv88e6321_ops, 6015 }, 6016 6017 [MV88E6341] = { 6018 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6019 .family = MV88E6XXX_FAMILY_6341, 6020 .name = "Marvell 88E6341", 6021 .num_databases = 4096, 6022 .num_macs = 2048, 6023 .num_internal_phys = 5, 6024 .num_ports = 6, 6025 .num_gpio = 11, 6026 .max_vid = 4095, 6027 .port_base_addr = 0x10, 6028 .phy_base_addr = 0x10, 6029 .global1_addr = 0x1b, 6030 .global2_addr = 0x1c, 6031 .age_time_coeff = 3750, 6032 .atu_move_port_mask = 0x1f, 6033 .g1_irqs = 9, 6034 .g2_irqs = 10, 6035 .pvt = true, 6036 .multi_chip = true, 6037 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6038 .ptp_support = true, 6039 .ops = &mv88e6341_ops, 6040 }, 6041 6042 [MV88E6350] = { 6043 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6044 .family = MV88E6XXX_FAMILY_6351, 6045 .name = "Marvell 88E6350", 6046 .num_databases = 4096, 6047 .num_macs = 8192, 6048 .num_ports = 7, 6049 .num_internal_phys = 5, 6050 .max_vid = 4095, 6051 .port_base_addr = 0x10, 6052 .phy_base_addr = 0x0, 6053 .global1_addr = 0x1b, 6054 .global2_addr = 0x1c, 6055 .age_time_coeff = 15000, 6056 .g1_irqs = 9, 6057 .g2_irqs = 10, 6058 .atu_move_port_mask = 0xf, 6059 .pvt = true, 6060 .multi_chip = true, 6061 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6062 .ops = &mv88e6350_ops, 6063 }, 6064 6065 [MV88E6351] = { 6066 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6067 .family = MV88E6XXX_FAMILY_6351, 6068 .name = "Marvell 88E6351", 6069 .num_databases = 4096, 6070 .num_macs = 8192, 6071 .num_ports = 7, 6072 .num_internal_phys = 5, 6073 .max_vid = 4095, 6074 .port_base_addr = 0x10, 6075 .phy_base_addr = 0x0, 6076 .global1_addr = 0x1b, 6077 .global2_addr = 0x1c, 6078 .age_time_coeff = 15000, 6079 .g1_irqs = 9, 6080 .g2_irqs = 10, 6081 .atu_move_port_mask = 0xf, 6082 .pvt = true, 6083 .multi_chip = true, 6084 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6085 .ops = &mv88e6351_ops, 6086 }, 6087 6088 [MV88E6352] = { 6089 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6090 .family = MV88E6XXX_FAMILY_6352, 6091 .name = "Marvell 88E6352", 6092 .num_databases = 4096, 6093 .num_macs = 8192, 6094 .num_ports = 7, 6095 .num_internal_phys = 5, 6096 .num_gpio = 15, 6097 .max_vid = 4095, 6098 .max_sid = 63, 6099 .port_base_addr = 0x10, 6100 .phy_base_addr = 0x0, 6101 .global1_addr = 0x1b, 6102 .global2_addr = 0x1c, 6103 .age_time_coeff = 15000, 6104 .g1_irqs = 9, 6105 .g2_irqs = 10, 6106 .atu_move_port_mask = 0xf, 6107 .pvt = true, 6108 .multi_chip = true, 6109 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6110 .ptp_support = true, 6111 .ops = &mv88e6352_ops, 6112 }, 6113 [MV88E6390] = { 6114 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6115 .family = MV88E6XXX_FAMILY_6390, 6116 .name = "Marvell 88E6390", 6117 .num_databases = 4096, 6118 .num_macs = 16384, 6119 .num_ports = 11, /* 10 + Z80 */ 6120 .num_internal_phys = 9, 6121 .num_gpio = 16, 6122 .max_vid = 8191, 6123 .max_sid = 63, 6124 .port_base_addr = 0x0, 6125 .phy_base_addr = 0x0, 6126 .global1_addr = 0x1b, 6127 .global2_addr = 0x1c, 6128 .age_time_coeff = 3750, 6129 .g1_irqs = 9, 6130 .g2_irqs = 14, 6131 .atu_move_port_mask = 0x1f, 6132 .pvt = true, 6133 .multi_chip = true, 6134 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6135 .ptp_support = true, 6136 .ops = &mv88e6390_ops, 6137 }, 6138 [MV88E6390X] = { 6139 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6140 .family = MV88E6XXX_FAMILY_6390, 6141 .name = "Marvell 88E6390X", 6142 .num_databases = 4096, 6143 .num_macs = 16384, 6144 .num_ports = 11, /* 10 + Z80 */ 6145 .num_internal_phys = 9, 6146 .num_gpio = 16, 6147 .max_vid = 8191, 6148 .max_sid = 63, 6149 .port_base_addr = 0x0, 6150 .phy_base_addr = 0x0, 6151 .global1_addr = 0x1b, 6152 .global2_addr = 0x1c, 6153 .age_time_coeff = 3750, 6154 .g1_irqs = 9, 6155 .g2_irqs = 14, 6156 .atu_move_port_mask = 0x1f, 6157 .pvt = true, 6158 .multi_chip = true, 6159 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6160 .ptp_support = true, 6161 .ops = &mv88e6390x_ops, 6162 }, 6163 6164 [MV88E6393X] = { 6165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6166 .family = MV88E6XXX_FAMILY_6393, 6167 .name = "Marvell 88E6393X", 6168 .num_databases = 4096, 6169 .num_ports = 11, /* 10 + Z80 */ 6170 .num_internal_phys = 9, 6171 .max_vid = 8191, 6172 .max_sid = 63, 6173 .port_base_addr = 0x0, 6174 .phy_base_addr = 0x0, 6175 .global1_addr = 0x1b, 6176 .global2_addr = 0x1c, 6177 .age_time_coeff = 3750, 6178 .g1_irqs = 10, 6179 .g2_irqs = 14, 6180 .atu_move_port_mask = 0x1f, 6181 .pvt = true, 6182 .multi_chip = true, 6183 .ptp_support = true, 6184 .ops = &mv88e6393x_ops, 6185 }, 6186 }; 6187 6188 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6189 { 6190 int i; 6191 6192 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6193 if (mv88e6xxx_table[i].prod_num == prod_num) 6194 return &mv88e6xxx_table[i]; 6195 6196 return NULL; 6197 } 6198 6199 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6200 { 6201 const struct mv88e6xxx_info *info; 6202 unsigned int prod_num, rev; 6203 u16 id; 6204 int err; 6205 6206 mv88e6xxx_reg_lock(chip); 6207 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6208 mv88e6xxx_reg_unlock(chip); 6209 if (err) 6210 return err; 6211 6212 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6213 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6214 6215 info = mv88e6xxx_lookup_info(prod_num); 6216 if (!info) 6217 return -ENODEV; 6218 6219 /* Update the compatible info with the probed one */ 6220 chip->info = info; 6221 6222 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6223 chip->info->prod_num, chip->info->name, rev); 6224 6225 return 0; 6226 } 6227 6228 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6229 { 6230 struct mv88e6xxx_chip *chip; 6231 6232 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6233 if (!chip) 6234 return NULL; 6235 6236 chip->dev = dev; 6237 6238 mutex_init(&chip->reg_lock); 6239 INIT_LIST_HEAD(&chip->mdios); 6240 idr_init(&chip->policies); 6241 INIT_LIST_HEAD(&chip->msts); 6242 6243 return chip; 6244 } 6245 6246 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6247 int port, 6248 enum dsa_tag_protocol m) 6249 { 6250 struct mv88e6xxx_chip *chip = ds->priv; 6251 6252 return chip->tag_protocol; 6253 } 6254 6255 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 6256 enum dsa_tag_protocol proto) 6257 { 6258 struct mv88e6xxx_chip *chip = ds->priv; 6259 enum dsa_tag_protocol old_protocol; 6260 int err; 6261 6262 switch (proto) { 6263 case DSA_TAG_PROTO_EDSA: 6264 switch (chip->info->edsa_support) { 6265 case MV88E6XXX_EDSA_UNSUPPORTED: 6266 return -EPROTONOSUPPORT; 6267 case MV88E6XXX_EDSA_UNDOCUMENTED: 6268 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6269 fallthrough; 6270 case MV88E6XXX_EDSA_SUPPORTED: 6271 break; 6272 } 6273 break; 6274 case DSA_TAG_PROTO_DSA: 6275 break; 6276 default: 6277 return -EPROTONOSUPPORT; 6278 } 6279 6280 old_protocol = chip->tag_protocol; 6281 chip->tag_protocol = proto; 6282 6283 mv88e6xxx_reg_lock(chip); 6284 err = mv88e6xxx_setup_port_mode(chip, port); 6285 mv88e6xxx_reg_unlock(chip); 6286 6287 if (err) 6288 chip->tag_protocol = old_protocol; 6289 6290 return err; 6291 } 6292 6293 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6294 const struct switchdev_obj_port_mdb *mdb, 6295 struct dsa_db db) 6296 { 6297 struct mv88e6xxx_chip *chip = ds->priv; 6298 int err; 6299 6300 mv88e6xxx_reg_lock(chip); 6301 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6302 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6303 mv88e6xxx_reg_unlock(chip); 6304 6305 return err; 6306 } 6307 6308 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6309 const struct switchdev_obj_port_mdb *mdb, 6310 struct dsa_db db) 6311 { 6312 struct mv88e6xxx_chip *chip = ds->priv; 6313 int err; 6314 6315 mv88e6xxx_reg_lock(chip); 6316 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6317 mv88e6xxx_reg_unlock(chip); 6318 6319 return err; 6320 } 6321 6322 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6323 struct dsa_mall_mirror_tc_entry *mirror, 6324 bool ingress) 6325 { 6326 enum mv88e6xxx_egress_direction direction = ingress ? 6327 MV88E6XXX_EGRESS_DIR_INGRESS : 6328 MV88E6XXX_EGRESS_DIR_EGRESS; 6329 struct mv88e6xxx_chip *chip = ds->priv; 6330 bool other_mirrors = false; 6331 int i; 6332 int err; 6333 6334 mutex_lock(&chip->reg_lock); 6335 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6336 mirror->to_local_port) { 6337 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6338 other_mirrors |= ingress ? 6339 chip->ports[i].mirror_ingress : 6340 chip->ports[i].mirror_egress; 6341 6342 /* Can't change egress port when other mirror is active */ 6343 if (other_mirrors) { 6344 err = -EBUSY; 6345 goto out; 6346 } 6347 6348 err = mv88e6xxx_set_egress_port(chip, direction, 6349 mirror->to_local_port); 6350 if (err) 6351 goto out; 6352 } 6353 6354 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6355 out: 6356 mutex_unlock(&chip->reg_lock); 6357 6358 return err; 6359 } 6360 6361 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6362 struct dsa_mall_mirror_tc_entry *mirror) 6363 { 6364 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6365 MV88E6XXX_EGRESS_DIR_INGRESS : 6366 MV88E6XXX_EGRESS_DIR_EGRESS; 6367 struct mv88e6xxx_chip *chip = ds->priv; 6368 bool other_mirrors = false; 6369 int i; 6370 6371 mutex_lock(&chip->reg_lock); 6372 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6373 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6374 6375 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6376 other_mirrors |= mirror->ingress ? 6377 chip->ports[i].mirror_ingress : 6378 chip->ports[i].mirror_egress; 6379 6380 /* Reset egress port when no other mirror is active */ 6381 if (!other_mirrors) { 6382 if (mv88e6xxx_set_egress_port(chip, direction, 6383 dsa_upstream_port(ds, port))) 6384 dev_err(ds->dev, "failed to set egress port\n"); 6385 } 6386 6387 mutex_unlock(&chip->reg_lock); 6388 } 6389 6390 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6391 struct switchdev_brport_flags flags, 6392 struct netlink_ext_ack *extack) 6393 { 6394 struct mv88e6xxx_chip *chip = ds->priv; 6395 const struct mv88e6xxx_ops *ops; 6396 6397 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6398 BR_BCAST_FLOOD | BR_PORT_LOCKED)) 6399 return -EINVAL; 6400 6401 ops = chip->info->ops; 6402 6403 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6404 return -EINVAL; 6405 6406 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6407 return -EINVAL; 6408 6409 return 0; 6410 } 6411 6412 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6413 struct switchdev_brport_flags flags, 6414 struct netlink_ext_ack *extack) 6415 { 6416 struct mv88e6xxx_chip *chip = ds->priv; 6417 int err = -EOPNOTSUPP; 6418 6419 mv88e6xxx_reg_lock(chip); 6420 6421 if (flags.mask & BR_LEARNING) { 6422 bool learning = !!(flags.val & BR_LEARNING); 6423 u16 pav = learning ? (1 << port) : 0; 6424 6425 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6426 if (err) 6427 goto out; 6428 } 6429 6430 if (flags.mask & BR_FLOOD) { 6431 bool unicast = !!(flags.val & BR_FLOOD); 6432 6433 err = chip->info->ops->port_set_ucast_flood(chip, port, 6434 unicast); 6435 if (err) 6436 goto out; 6437 } 6438 6439 if (flags.mask & BR_MCAST_FLOOD) { 6440 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6441 6442 err = chip->info->ops->port_set_mcast_flood(chip, port, 6443 multicast); 6444 if (err) 6445 goto out; 6446 } 6447 6448 if (flags.mask & BR_BCAST_FLOOD) { 6449 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6450 6451 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6452 if (err) 6453 goto out; 6454 } 6455 6456 if (flags.mask & BR_PORT_LOCKED) { 6457 bool locked = !!(flags.val & BR_PORT_LOCKED); 6458 6459 err = mv88e6xxx_port_set_lock(chip, port, locked); 6460 if (err) 6461 goto out; 6462 } 6463 out: 6464 mv88e6xxx_reg_unlock(chip); 6465 6466 return err; 6467 } 6468 6469 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6470 struct dsa_lag lag, 6471 struct netdev_lag_upper_info *info) 6472 { 6473 struct mv88e6xxx_chip *chip = ds->priv; 6474 struct dsa_port *dp; 6475 int members = 0; 6476 6477 if (!mv88e6xxx_has_lag(chip)) 6478 return false; 6479 6480 if (!lag.id) 6481 return false; 6482 6483 dsa_lag_foreach_port(dp, ds->dst, &lag) 6484 /* Includes the port joining the LAG */ 6485 members++; 6486 6487 if (members > 8) 6488 return false; 6489 6490 /* We could potentially relax this to include active 6491 * backup in the future. 6492 */ 6493 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 6494 return false; 6495 6496 /* Ideally we would also validate that the hash type matches 6497 * the hardware. Alas, this is always set to unknown on team 6498 * interfaces. 6499 */ 6500 return true; 6501 } 6502 6503 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6504 { 6505 struct mv88e6xxx_chip *chip = ds->priv; 6506 struct dsa_port *dp; 6507 u16 map = 0; 6508 int id; 6509 6510 /* DSA LAG IDs are one-based, hardware is zero-based */ 6511 id = lag.id - 1; 6512 6513 /* Build the map of all ports to distribute flows destined for 6514 * this LAG. This can be either a local user port, or a DSA 6515 * port if the LAG port is on a remote chip. 6516 */ 6517 dsa_lag_foreach_port(dp, ds->dst, &lag) 6518 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6519 6520 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6521 } 6522 6523 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6524 /* Row number corresponds to the number of active members in a 6525 * LAG. Each column states which of the eight hash buckets are 6526 * mapped to the column:th port in the LAG. 6527 * 6528 * Example: In a LAG with three active ports, the second port 6529 * ([2][1]) would be selected for traffic mapped to buckets 6530 * 3,4,5 (0x38). 6531 */ 6532 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6533 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6534 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6535 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6536 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6537 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6538 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6539 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6540 }; 6541 6542 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6543 int num_tx, int nth) 6544 { 6545 u8 active = 0; 6546 int i; 6547 6548 num_tx = num_tx <= 8 ? num_tx : 8; 6549 if (nth < num_tx) 6550 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6551 6552 for (i = 0; i < 8; i++) { 6553 if (BIT(i) & active) 6554 mask[i] |= BIT(port); 6555 } 6556 } 6557 6558 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6559 { 6560 struct mv88e6xxx_chip *chip = ds->priv; 6561 unsigned int id, num_tx; 6562 struct dsa_port *dp; 6563 struct dsa_lag *lag; 6564 int i, err, nth; 6565 u16 mask[8]; 6566 u16 ivec; 6567 6568 /* Assume no port is a member of any LAG. */ 6569 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6570 6571 /* Disable all masks for ports that _are_ members of a LAG. */ 6572 dsa_switch_for_each_port(dp, ds) { 6573 if (!dp->lag) 6574 continue; 6575 6576 ivec &= ~BIT(dp->index); 6577 } 6578 6579 for (i = 0; i < 8; i++) 6580 mask[i] = ivec; 6581 6582 /* Enable the correct subset of masks for all LAG ports that 6583 * are in the Tx set. 6584 */ 6585 dsa_lags_foreach_id(id, ds->dst) { 6586 lag = dsa_lag_by_id(ds->dst, id); 6587 if (!lag) 6588 continue; 6589 6590 num_tx = 0; 6591 dsa_lag_foreach_port(dp, ds->dst, lag) { 6592 if (dp->lag_tx_enabled) 6593 num_tx++; 6594 } 6595 6596 if (!num_tx) 6597 continue; 6598 6599 nth = 0; 6600 dsa_lag_foreach_port(dp, ds->dst, lag) { 6601 if (!dp->lag_tx_enabled) 6602 continue; 6603 6604 if (dp->ds == ds) 6605 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6606 num_tx, nth); 6607 6608 nth++; 6609 } 6610 } 6611 6612 for (i = 0; i < 8; i++) { 6613 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6614 if (err) 6615 return err; 6616 } 6617 6618 return 0; 6619 } 6620 6621 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6622 struct dsa_lag lag) 6623 { 6624 int err; 6625 6626 err = mv88e6xxx_lag_sync_masks(ds); 6627 6628 if (!err) 6629 err = mv88e6xxx_lag_sync_map(ds, lag); 6630 6631 return err; 6632 } 6633 6634 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6635 { 6636 struct mv88e6xxx_chip *chip = ds->priv; 6637 int err; 6638 6639 mv88e6xxx_reg_lock(chip); 6640 err = mv88e6xxx_lag_sync_masks(ds); 6641 mv88e6xxx_reg_unlock(chip); 6642 return err; 6643 } 6644 6645 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6646 struct dsa_lag lag, 6647 struct netdev_lag_upper_info *info) 6648 { 6649 struct mv88e6xxx_chip *chip = ds->priv; 6650 int err, id; 6651 6652 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6653 return -EOPNOTSUPP; 6654 6655 /* DSA LAG IDs are one-based */ 6656 id = lag.id - 1; 6657 6658 mv88e6xxx_reg_lock(chip); 6659 6660 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6661 if (err) 6662 goto err_unlock; 6663 6664 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6665 if (err) 6666 goto err_clear_trunk; 6667 6668 mv88e6xxx_reg_unlock(chip); 6669 return 0; 6670 6671 err_clear_trunk: 6672 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6673 err_unlock: 6674 mv88e6xxx_reg_unlock(chip); 6675 return err; 6676 } 6677 6678 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6679 struct dsa_lag lag) 6680 { 6681 struct mv88e6xxx_chip *chip = ds->priv; 6682 int err_sync, err_trunk; 6683 6684 mv88e6xxx_reg_lock(chip); 6685 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6686 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6687 mv88e6xxx_reg_unlock(chip); 6688 return err_sync ? : err_trunk; 6689 } 6690 6691 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6692 int port) 6693 { 6694 struct mv88e6xxx_chip *chip = ds->priv; 6695 int err; 6696 6697 mv88e6xxx_reg_lock(chip); 6698 err = mv88e6xxx_lag_sync_masks(ds); 6699 mv88e6xxx_reg_unlock(chip); 6700 return err; 6701 } 6702 6703 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6704 int port, struct dsa_lag lag, 6705 struct netdev_lag_upper_info *info) 6706 { 6707 struct mv88e6xxx_chip *chip = ds->priv; 6708 int err; 6709 6710 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6711 return -EOPNOTSUPP; 6712 6713 mv88e6xxx_reg_lock(chip); 6714 6715 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6716 if (err) 6717 goto unlock; 6718 6719 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6720 6721 unlock: 6722 mv88e6xxx_reg_unlock(chip); 6723 return err; 6724 } 6725 6726 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6727 int port, struct dsa_lag lag) 6728 { 6729 struct mv88e6xxx_chip *chip = ds->priv; 6730 int err_sync, err_pvt; 6731 6732 mv88e6xxx_reg_lock(chip); 6733 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6734 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6735 mv88e6xxx_reg_unlock(chip); 6736 return err_sync ? : err_pvt; 6737 } 6738 6739 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6740 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6741 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6742 .setup = mv88e6xxx_setup, 6743 .teardown = mv88e6xxx_teardown, 6744 .port_setup = mv88e6xxx_port_setup, 6745 .port_teardown = mv88e6xxx_port_teardown, 6746 .phylink_get_caps = mv88e6xxx_get_caps, 6747 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6748 .phylink_mac_config = mv88e6xxx_mac_config, 6749 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6750 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6751 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6752 .get_strings = mv88e6xxx_get_strings, 6753 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6754 .get_sset_count = mv88e6xxx_get_sset_count, 6755 .port_enable = mv88e6xxx_port_enable, 6756 .port_disable = mv88e6xxx_port_disable, 6757 .port_max_mtu = mv88e6xxx_get_max_mtu, 6758 .port_change_mtu = mv88e6xxx_change_mtu, 6759 .get_mac_eee = mv88e6xxx_get_mac_eee, 6760 .set_mac_eee = mv88e6xxx_set_mac_eee, 6761 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6762 .get_eeprom = mv88e6xxx_get_eeprom, 6763 .set_eeprom = mv88e6xxx_set_eeprom, 6764 .get_regs_len = mv88e6xxx_get_regs_len, 6765 .get_regs = mv88e6xxx_get_regs, 6766 .get_rxnfc = mv88e6xxx_get_rxnfc, 6767 .set_rxnfc = mv88e6xxx_set_rxnfc, 6768 .set_ageing_time = mv88e6xxx_set_ageing_time, 6769 .port_bridge_join = mv88e6xxx_port_bridge_join, 6770 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6771 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6772 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6773 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6774 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6775 .port_fast_age = mv88e6xxx_port_fast_age, 6776 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6777 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6778 .port_vlan_add = mv88e6xxx_port_vlan_add, 6779 .port_vlan_del = mv88e6xxx_port_vlan_del, 6780 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6781 .port_fdb_add = mv88e6xxx_port_fdb_add, 6782 .port_fdb_del = mv88e6xxx_port_fdb_del, 6783 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6784 .port_mdb_add = mv88e6xxx_port_mdb_add, 6785 .port_mdb_del = mv88e6xxx_port_mdb_del, 6786 .port_mirror_add = mv88e6xxx_port_mirror_add, 6787 .port_mirror_del = mv88e6xxx_port_mirror_del, 6788 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6789 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6790 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6791 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6792 .port_txtstamp = mv88e6xxx_port_txtstamp, 6793 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6794 .get_ts_info = mv88e6xxx_get_ts_info, 6795 .devlink_param_get = mv88e6xxx_devlink_param_get, 6796 .devlink_param_set = mv88e6xxx_devlink_param_set, 6797 .devlink_info_get = mv88e6xxx_devlink_info_get, 6798 .port_lag_change = mv88e6xxx_port_lag_change, 6799 .port_lag_join = mv88e6xxx_port_lag_join, 6800 .port_lag_leave = mv88e6xxx_port_lag_leave, 6801 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6802 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6803 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6804 }; 6805 6806 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6807 { 6808 struct device *dev = chip->dev; 6809 struct dsa_switch *ds; 6810 6811 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6812 if (!ds) 6813 return -ENOMEM; 6814 6815 ds->dev = dev; 6816 ds->num_ports = mv88e6xxx_num_ports(chip); 6817 ds->priv = chip; 6818 ds->dev = dev; 6819 ds->ops = &mv88e6xxx_switch_ops; 6820 ds->ageing_time_min = chip->info->age_time_coeff; 6821 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6822 6823 /* Some chips support up to 32, but that requires enabling the 6824 * 5-bit port mode, which we do not support. 640k^W16 ought to 6825 * be enough for anyone. 6826 */ 6827 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6828 6829 dev_set_drvdata(dev, ds); 6830 6831 return dsa_register_switch(ds); 6832 } 6833 6834 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6835 { 6836 dsa_unregister_switch(chip->ds); 6837 } 6838 6839 static const void *pdata_device_get_match_data(struct device *dev) 6840 { 6841 const struct of_device_id *matches = dev->driver->of_match_table; 6842 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6843 6844 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6845 matches++) { 6846 if (!strcmp(pdata->compatible, matches->compatible)) 6847 return matches->data; 6848 } 6849 return NULL; 6850 } 6851 6852 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6853 * would be lost after a power cycle so prevent it to be suspended. 6854 */ 6855 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6856 { 6857 return -EOPNOTSUPP; 6858 } 6859 6860 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6861 { 6862 return 0; 6863 } 6864 6865 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6866 6867 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6868 { 6869 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6870 const struct mv88e6xxx_info *compat_info = NULL; 6871 struct device *dev = &mdiodev->dev; 6872 struct device_node *np = dev->of_node; 6873 struct mv88e6xxx_chip *chip; 6874 int port; 6875 int err; 6876 6877 if (!np && !pdata) 6878 return -EINVAL; 6879 6880 if (np) 6881 compat_info = of_device_get_match_data(dev); 6882 6883 if (pdata) { 6884 compat_info = pdata_device_get_match_data(dev); 6885 6886 if (!pdata->netdev) 6887 return -EINVAL; 6888 6889 for (port = 0; port < DSA_MAX_PORTS; port++) { 6890 if (!(pdata->enabled_ports & (1 << port))) 6891 continue; 6892 if (strcmp(pdata->cd.port_names[port], "cpu")) 6893 continue; 6894 pdata->cd.netdev[port] = &pdata->netdev->dev; 6895 break; 6896 } 6897 } 6898 6899 if (!compat_info) 6900 return -EINVAL; 6901 6902 chip = mv88e6xxx_alloc_chip(dev); 6903 if (!chip) { 6904 err = -ENOMEM; 6905 goto out; 6906 } 6907 6908 chip->info = compat_info; 6909 6910 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6911 if (err) 6912 goto out; 6913 6914 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6915 if (IS_ERR(chip->reset)) { 6916 err = PTR_ERR(chip->reset); 6917 goto out; 6918 } 6919 if (chip->reset) 6920 usleep_range(1000, 2000); 6921 6922 err = mv88e6xxx_detect(chip); 6923 if (err) 6924 goto out; 6925 6926 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6927 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6928 else 6929 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6930 6931 mv88e6xxx_phy_init(chip); 6932 6933 if (chip->info->ops->get_eeprom) { 6934 if (np) 6935 of_property_read_u32(np, "eeprom-length", 6936 &chip->eeprom_len); 6937 else 6938 chip->eeprom_len = pdata->eeprom_len; 6939 } 6940 6941 mv88e6xxx_reg_lock(chip); 6942 err = mv88e6xxx_switch_reset(chip); 6943 mv88e6xxx_reg_unlock(chip); 6944 if (err) 6945 goto out; 6946 6947 if (np) { 6948 chip->irq = of_irq_get(np, 0); 6949 if (chip->irq == -EPROBE_DEFER) { 6950 err = chip->irq; 6951 goto out; 6952 } 6953 } 6954 6955 if (pdata) 6956 chip->irq = pdata->irq; 6957 6958 /* Has to be performed before the MDIO bus is created, because 6959 * the PHYs will link their interrupts to these interrupt 6960 * controllers 6961 */ 6962 mv88e6xxx_reg_lock(chip); 6963 if (chip->irq > 0) 6964 err = mv88e6xxx_g1_irq_setup(chip); 6965 else 6966 err = mv88e6xxx_irq_poll_setup(chip); 6967 mv88e6xxx_reg_unlock(chip); 6968 6969 if (err) 6970 goto out; 6971 6972 if (chip->info->g2_irqs > 0) { 6973 err = mv88e6xxx_g2_irq_setup(chip); 6974 if (err) 6975 goto out_g1_irq; 6976 } 6977 6978 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6979 if (err) 6980 goto out_g2_irq; 6981 6982 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6983 if (err) 6984 goto out_g1_atu_prob_irq; 6985 6986 err = mv88e6xxx_mdios_register(chip, np); 6987 if (err) 6988 goto out_g1_vtu_prob_irq; 6989 6990 err = mv88e6xxx_register_switch(chip); 6991 if (err) 6992 goto out_mdio; 6993 6994 return 0; 6995 6996 out_mdio: 6997 mv88e6xxx_mdios_unregister(chip); 6998 out_g1_vtu_prob_irq: 6999 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7000 out_g1_atu_prob_irq: 7001 mv88e6xxx_g1_atu_prob_irq_free(chip); 7002 out_g2_irq: 7003 if (chip->info->g2_irqs > 0) 7004 mv88e6xxx_g2_irq_free(chip); 7005 out_g1_irq: 7006 if (chip->irq > 0) 7007 mv88e6xxx_g1_irq_free(chip); 7008 else 7009 mv88e6xxx_irq_poll_free(chip); 7010 out: 7011 if (pdata) 7012 dev_put(pdata->netdev); 7013 7014 return err; 7015 } 7016 7017 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7018 { 7019 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7020 struct mv88e6xxx_chip *chip; 7021 7022 if (!ds) 7023 return; 7024 7025 chip = ds->priv; 7026 7027 if (chip->info->ptp_support) { 7028 mv88e6xxx_hwtstamp_free(chip); 7029 mv88e6xxx_ptp_free(chip); 7030 } 7031 7032 mv88e6xxx_phy_destroy(chip); 7033 mv88e6xxx_unregister_switch(chip); 7034 mv88e6xxx_mdios_unregister(chip); 7035 7036 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7037 mv88e6xxx_g1_atu_prob_irq_free(chip); 7038 7039 if (chip->info->g2_irqs > 0) 7040 mv88e6xxx_g2_irq_free(chip); 7041 7042 if (chip->irq > 0) 7043 mv88e6xxx_g1_irq_free(chip); 7044 else 7045 mv88e6xxx_irq_poll_free(chip); 7046 7047 dev_set_drvdata(&mdiodev->dev, NULL); 7048 } 7049 7050 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7051 { 7052 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7053 7054 if (!ds) 7055 return; 7056 7057 dsa_switch_shutdown(ds); 7058 7059 dev_set_drvdata(&mdiodev->dev, NULL); 7060 } 7061 7062 static const struct of_device_id mv88e6xxx_of_match[] = { 7063 { 7064 .compatible = "marvell,mv88e6085", 7065 .data = &mv88e6xxx_table[MV88E6085], 7066 }, 7067 { 7068 .compatible = "marvell,mv88e6190", 7069 .data = &mv88e6xxx_table[MV88E6190], 7070 }, 7071 { 7072 .compatible = "marvell,mv88e6250", 7073 .data = &mv88e6xxx_table[MV88E6250], 7074 }, 7075 { /* sentinel */ }, 7076 }; 7077 7078 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7079 7080 static struct mdio_driver mv88e6xxx_driver = { 7081 .probe = mv88e6xxx_probe, 7082 .remove = mv88e6xxx_remove, 7083 .shutdown = mv88e6xxx_shutdown, 7084 .mdiodrv.driver = { 7085 .name = "mv88e6085", 7086 .of_match_table = mv88e6xxx_of_match, 7087 .pm = &mv88e6xxx_pm_ops, 7088 }, 7089 }; 7090 7091 mdio_module_driver(mv88e6xxx_driver); 7092 7093 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7094 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7095 MODULE_LICENSE("GPL"); 7096