1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_mdio.h> 27 #include <linux/netdevice.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/phy.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 #include "mv88e6xxx.h" 33 34 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 35 { 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 37 dev_err(chip->dev, "Switch registers lock not held!\n"); 38 dump_stack(); 39 } 40 } 41 42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 44 * 45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 46 * is the only device connected to the SMI master. In this mode it responds to 47 * all 32 possible SMI addresses, and thus maps directly the internal devices. 48 * 49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 50 * multiple devices to share the SMI interface. In this mode it responds to only 51 * 2 registers, used to indirectly access the internal SMI devices. 52 */ 53 54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 55 int addr, int reg, u16 *val) 56 { 57 if (!chip->smi_ops) 58 return -EOPNOTSUPP; 59 60 return chip->smi_ops->read(chip, addr, reg, val); 61 } 62 63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->write(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 *val) 74 { 75 int ret; 76 77 ret = mdiobus_read_nested(chip->bus, addr, reg); 78 if (ret < 0) 79 return ret; 80 81 *val = ret & 0xffff; 82 83 return 0; 84 } 85 86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 87 int addr, int reg, u16 val) 88 { 89 int ret; 90 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 92 if (ret < 0) 93 return ret; 94 95 return 0; 96 } 97 98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = { 99 .read = mv88e6xxx_smi_single_chip_read, 100 .write = mv88e6xxx_smi_single_chip_write, 101 }; 102 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 104 { 105 int ret; 106 int i; 107 108 for (i = 0; i < 16; i++) { 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 110 if (ret < 0) 111 return ret; 112 113 if ((ret & SMI_CMD_BUSY) == 0) 114 return 0; 115 } 116 117 return -ETIMEDOUT; 118 } 119 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 121 int addr, int reg, u16 *val) 122 { 123 int ret; 124 125 /* Wait for the bus to become free. */ 126 ret = mv88e6xxx_smi_multi_chip_wait(chip); 127 if (ret < 0) 128 return ret; 129 130 /* Transmit the read command. */ 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 132 SMI_CMD_OP_22_READ | (addr << 5) | reg); 133 if (ret < 0) 134 return ret; 135 136 /* Wait for the read command to complete. */ 137 ret = mv88e6xxx_smi_multi_chip_wait(chip); 138 if (ret < 0) 139 return ret; 140 141 /* Read the data. */ 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 143 if (ret < 0) 144 return ret; 145 146 *val = ret & 0xffff; 147 148 return 0; 149 } 150 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 152 int addr, int reg, u16 val) 153 { 154 int ret; 155 156 /* Wait for the bus to become free. */ 157 ret = mv88e6xxx_smi_multi_chip_wait(chip); 158 if (ret < 0) 159 return ret; 160 161 /* Transmit the data to write. */ 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 163 if (ret < 0) 164 return ret; 165 166 /* Transmit the write command. */ 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 169 if (ret < 0) 170 return ret; 171 172 /* Wait for the write command to complete. */ 173 ret = mv88e6xxx_smi_multi_chip_wait(chip); 174 if (ret < 0) 175 return ret; 176 177 return 0; 178 } 179 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = { 181 .read = mv88e6xxx_smi_multi_chip_read, 182 .write = mv88e6xxx_smi_multi_chip_write, 183 }; 184 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip, 186 int addr, int reg, u16 *val) 187 { 188 int err; 189 190 assert_reg_lock(chip); 191 192 err = mv88e6xxx_smi_read(chip, addr, reg, val); 193 if (err) 194 return err; 195 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 197 addr, reg, *val); 198 199 return 0; 200 } 201 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip, 203 int addr, int reg, u16 val) 204 { 205 int err; 206 207 assert_reg_lock(chip); 208 209 err = mv88e6xxx_smi_write(chip, addr, reg, val); 210 if (err) 211 return err; 212 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 214 addr, reg, val); 215 216 return 0; 217 } 218 219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 220 int reg, u16 *val) 221 { 222 int addr = phy; /* PHY devices addresses start at 0x0 */ 223 224 if (!chip->phy_ops) 225 return -EOPNOTSUPP; 226 227 return chip->phy_ops->read(chip, addr, reg, val); 228 } 229 230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 231 int reg, u16 val) 232 { 233 int addr = phy; /* PHY devices addresses start at 0x0 */ 234 235 if (!chip->phy_ops) 236 return -EOPNOTSUPP; 237 238 return chip->phy_ops->write(chip, addr, reg, val); 239 } 240 241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 242 { 243 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 244 return -EOPNOTSUPP; 245 246 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 247 } 248 249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 250 { 251 int err; 252 253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 254 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 255 if (unlikely(err)) { 256 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 257 phy, err); 258 } 259 } 260 261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 262 u8 page, int reg, u16 *val) 263 { 264 int err; 265 266 /* There is no paging for registers 22 */ 267 if (reg == PHY_PAGE) 268 return -EINVAL; 269 270 err = mv88e6xxx_phy_page_get(chip, phy, page); 271 if (!err) { 272 err = mv88e6xxx_phy_read(chip, phy, reg, val); 273 mv88e6xxx_phy_page_put(chip, phy); 274 } 275 276 return err; 277 } 278 279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 280 u8 page, int reg, u16 val) 281 { 282 int err; 283 284 /* There is no paging for registers 22 */ 285 if (reg == PHY_PAGE) 286 return -EINVAL; 287 288 err = mv88e6xxx_phy_page_get(chip, phy, page); 289 if (!err) { 290 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 291 mv88e6xxx_phy_page_put(chip, phy); 292 } 293 294 return err; 295 } 296 297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 298 { 299 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 300 reg, val); 301 } 302 303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 304 { 305 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 306 reg, val); 307 } 308 309 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, 310 u16 mask) 311 { 312 int i; 313 314 for (i = 0; i < 16; i++) { 315 u16 val; 316 int err; 317 318 err = mv88e6xxx_read(chip, addr, reg, &val); 319 if (err) 320 return err; 321 322 if (!(val & mask)) 323 return 0; 324 325 usleep_range(1000, 2000); 326 } 327 328 dev_err(chip->dev, "Timeout while waiting for switch\n"); 329 return -ETIMEDOUT; 330 } 331 332 /* Indirect write to single pointer-data register with an Update bit */ 333 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 334 u16 update) 335 { 336 u16 val; 337 int err; 338 339 /* Wait until the previous operation is completed */ 340 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 341 if (err) 342 return err; 343 344 /* Set the Update bit to trigger a write operation */ 345 val = BIT(15) | update; 346 347 return mv88e6xxx_write(chip, addr, reg, val); 348 } 349 350 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg) 351 { 352 u16 val; 353 int err; 354 355 err = mv88e6xxx_read(chip, addr, reg, &val); 356 if (err) 357 return err; 358 359 return val; 360 } 361 362 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr, 363 int reg, u16 val) 364 { 365 return mv88e6xxx_write(chip, addr, reg, val); 366 } 367 368 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 369 { 370 int ret; 371 int i; 372 373 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); 374 if (ret < 0) 375 return ret; 376 377 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, 378 ret & ~GLOBAL_CONTROL_PPU_ENABLE); 379 if (ret) 380 return ret; 381 382 for (i = 0; i < 16; i++) { 383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); 384 if (ret < 0) 385 return ret; 386 387 usleep_range(1000, 2000); 388 if ((ret & GLOBAL_STATUS_PPU_MASK) != 389 GLOBAL_STATUS_PPU_POLLING) 390 return 0; 391 } 392 393 return -ETIMEDOUT; 394 } 395 396 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 397 { 398 int ret, err, i; 399 400 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL); 401 if (ret < 0) 402 return ret; 403 404 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, 405 ret | GLOBAL_CONTROL_PPU_ENABLE); 406 if (err) 407 return err; 408 409 for (i = 0; i < 16; i++) { 410 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS); 411 if (ret < 0) 412 return ret; 413 414 usleep_range(1000, 2000); 415 if ((ret & GLOBAL_STATUS_PPU_MASK) == 416 GLOBAL_STATUS_PPU_POLLING) 417 return 0; 418 } 419 420 return -ETIMEDOUT; 421 } 422 423 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 424 { 425 struct mv88e6xxx_chip *chip; 426 427 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 428 429 mutex_lock(&chip->reg_lock); 430 431 if (mutex_trylock(&chip->ppu_mutex)) { 432 if (mv88e6xxx_ppu_enable(chip) == 0) 433 chip->ppu_disabled = 0; 434 mutex_unlock(&chip->ppu_mutex); 435 } 436 437 mutex_unlock(&chip->reg_lock); 438 } 439 440 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 441 { 442 struct mv88e6xxx_chip *chip = (void *)_ps; 443 444 schedule_work(&chip->ppu_work); 445 } 446 447 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 448 { 449 int ret; 450 451 mutex_lock(&chip->ppu_mutex); 452 453 /* If the PHY polling unit is enabled, disable it so that 454 * we can access the PHY registers. If it was already 455 * disabled, cancel the timer that is going to re-enable 456 * it. 457 */ 458 if (!chip->ppu_disabled) { 459 ret = mv88e6xxx_ppu_disable(chip); 460 if (ret < 0) { 461 mutex_unlock(&chip->ppu_mutex); 462 return ret; 463 } 464 chip->ppu_disabled = 1; 465 } else { 466 del_timer(&chip->ppu_timer); 467 ret = 0; 468 } 469 470 return ret; 471 } 472 473 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 474 { 475 /* Schedule a timer to re-enable the PHY polling unit. */ 476 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 477 mutex_unlock(&chip->ppu_mutex); 478 } 479 480 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 481 { 482 mutex_init(&chip->ppu_mutex); 483 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 484 init_timer(&chip->ppu_timer); 485 chip->ppu_timer.data = (unsigned long)chip; 486 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; 487 } 488 489 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, 490 int reg, u16 *val) 491 { 492 int err; 493 494 err = mv88e6xxx_ppu_access_get(chip); 495 if (!err) { 496 err = mv88e6xxx_read(chip, addr, reg, val); 497 mv88e6xxx_ppu_access_put(chip); 498 } 499 500 return err; 501 } 502 503 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, 504 int reg, u16 val) 505 { 506 int err; 507 508 err = mv88e6xxx_ppu_access_get(chip); 509 if (!err) { 510 err = mv88e6xxx_write(chip, addr, reg, val); 511 mv88e6xxx_ppu_access_put(chip); 512 } 513 514 return err; 515 } 516 517 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = { 518 .read = mv88e6xxx_phy_ppu_read, 519 .write = mv88e6xxx_phy_ppu_write, 520 }; 521 522 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) 523 { 524 return chip->info->family == MV88E6XXX_FAMILY_6065; 525 } 526 527 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) 528 { 529 return chip->info->family == MV88E6XXX_FAMILY_6095; 530 } 531 532 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 533 { 534 return chip->info->family == MV88E6XXX_FAMILY_6097; 535 } 536 537 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 538 { 539 return chip->info->family == MV88E6XXX_FAMILY_6165; 540 } 541 542 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) 543 { 544 return chip->info->family == MV88E6XXX_FAMILY_6185; 545 } 546 547 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 548 { 549 return chip->info->family == MV88E6XXX_FAMILY_6320; 550 } 551 552 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 553 { 554 return chip->info->family == MV88E6XXX_FAMILY_6351; 555 } 556 557 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 558 { 559 return chip->info->family == MV88E6XXX_FAMILY_6352; 560 } 561 562 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 563 { 564 return chip->info->num_databases; 565 } 566 567 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip) 568 { 569 /* Does the device have dedicated FID registers for ATU and VTU ops? */ 570 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 571 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) 572 return true; 573 574 return false; 575 } 576 577 /* We expect the switch to perform auto negotiation if there is a real 578 * phy. However, in the case of a fixed link phy, we force the port 579 * settings from the fixed link settings. 580 */ 581 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 582 struct phy_device *phydev) 583 { 584 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 585 u32 reg; 586 int ret; 587 588 if (!phy_is_pseudo_fixed_link(phydev)) 589 return; 590 591 mutex_lock(&chip->reg_lock); 592 593 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL); 594 if (ret < 0) 595 goto out; 596 597 reg = ret & ~(PORT_PCS_CTRL_LINK_UP | 598 PORT_PCS_CTRL_FORCE_LINK | 599 PORT_PCS_CTRL_DUPLEX_FULL | 600 PORT_PCS_CTRL_FORCE_DUPLEX | 601 PORT_PCS_CTRL_UNFORCED); 602 603 reg |= PORT_PCS_CTRL_FORCE_LINK; 604 if (phydev->link) 605 reg |= PORT_PCS_CTRL_LINK_UP; 606 607 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100) 608 goto out; 609 610 switch (phydev->speed) { 611 case SPEED_1000: 612 reg |= PORT_PCS_CTRL_1000; 613 break; 614 case SPEED_100: 615 reg |= PORT_PCS_CTRL_100; 616 break; 617 case SPEED_10: 618 reg |= PORT_PCS_CTRL_10; 619 break; 620 default: 621 pr_info("Unknown speed"); 622 goto out; 623 } 624 625 reg |= PORT_PCS_CTRL_FORCE_DUPLEX; 626 if (phydev->duplex == DUPLEX_FULL) 627 reg |= PORT_PCS_CTRL_DUPLEX_FULL; 628 629 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) && 630 (port >= chip->info->num_ports - 2)) { 631 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 632 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; 633 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 634 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; 635 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 636 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 637 PORT_PCS_CTRL_RGMII_DELAY_TXCLK); 638 } 639 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg); 640 641 out: 642 mutex_unlock(&chip->reg_lock); 643 } 644 645 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) 646 { 647 int ret; 648 int i; 649 650 for (i = 0; i < 10; i++) { 651 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP); 652 if ((ret & GLOBAL_STATS_OP_BUSY) == 0) 653 return 0; 654 } 655 656 return -ETIMEDOUT; 657 } 658 659 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 660 { 661 int ret; 662 663 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 664 port = (port + 1) << 5; 665 666 /* Snapshot the hardware statistics counters for this port. */ 667 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, 668 GLOBAL_STATS_OP_CAPTURE_PORT | 669 GLOBAL_STATS_OP_HIST_RX_TX | port); 670 if (ret < 0) 671 return ret; 672 673 /* Wait for the snapshotting to complete. */ 674 ret = _mv88e6xxx_stats_wait(chip); 675 if (ret < 0) 676 return ret; 677 678 return 0; 679 } 680 681 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, 682 int stat, u32 *val) 683 { 684 u32 _val; 685 int ret; 686 687 *val = 0; 688 689 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, 690 GLOBAL_STATS_OP_READ_CAPTURED | 691 GLOBAL_STATS_OP_HIST_RX_TX | stat); 692 if (ret < 0) 693 return; 694 695 ret = _mv88e6xxx_stats_wait(chip); 696 if (ret < 0) 697 return; 698 699 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); 700 if (ret < 0) 701 return; 702 703 _val = ret << 16; 704 705 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); 706 if (ret < 0) 707 return; 708 709 *val = _val | ret; 710 } 711 712 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 713 { "in_good_octets", 8, 0x00, BANK0, }, 714 { "in_bad_octets", 4, 0x02, BANK0, }, 715 { "in_unicast", 4, 0x04, BANK0, }, 716 { "in_broadcasts", 4, 0x06, BANK0, }, 717 { "in_multicasts", 4, 0x07, BANK0, }, 718 { "in_pause", 4, 0x16, BANK0, }, 719 { "in_undersize", 4, 0x18, BANK0, }, 720 { "in_fragments", 4, 0x19, BANK0, }, 721 { "in_oversize", 4, 0x1a, BANK0, }, 722 { "in_jabber", 4, 0x1b, BANK0, }, 723 { "in_rx_error", 4, 0x1c, BANK0, }, 724 { "in_fcs_error", 4, 0x1d, BANK0, }, 725 { "out_octets", 8, 0x0e, BANK0, }, 726 { "out_unicast", 4, 0x10, BANK0, }, 727 { "out_broadcasts", 4, 0x13, BANK0, }, 728 { "out_multicasts", 4, 0x12, BANK0, }, 729 { "out_pause", 4, 0x15, BANK0, }, 730 { "excessive", 4, 0x11, BANK0, }, 731 { "collisions", 4, 0x1e, BANK0, }, 732 { "deferred", 4, 0x05, BANK0, }, 733 { "single", 4, 0x14, BANK0, }, 734 { "multiple", 4, 0x17, BANK0, }, 735 { "out_fcs_error", 4, 0x03, BANK0, }, 736 { "late", 4, 0x1f, BANK0, }, 737 { "hist_64bytes", 4, 0x08, BANK0, }, 738 { "hist_65_127bytes", 4, 0x09, BANK0, }, 739 { "hist_128_255bytes", 4, 0x0a, BANK0, }, 740 { "hist_256_511bytes", 4, 0x0b, BANK0, }, 741 { "hist_512_1023bytes", 4, 0x0c, BANK0, }, 742 { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, 743 { "sw_in_discards", 4, 0x10, PORT, }, 744 { "sw_in_filtered", 2, 0x12, PORT, }, 745 { "sw_out_filtered", 2, 0x13, PORT, }, 746 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 747 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 748 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 749 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 750 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 751 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 752 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 753 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 754 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 755 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 756 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, 757 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, 758 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, 759 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, 760 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 761 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 762 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 763 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 764 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 765 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 766 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 767 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 768 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 769 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, 770 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, 771 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, 772 }; 773 774 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, 775 struct mv88e6xxx_hw_stat *stat) 776 { 777 switch (stat->type) { 778 case BANK0: 779 return true; 780 case BANK1: 781 return mv88e6xxx_6320_family(chip); 782 case PORT: 783 return mv88e6xxx_6095_family(chip) || 784 mv88e6xxx_6185_family(chip) || 785 mv88e6xxx_6097_family(chip) || 786 mv88e6xxx_6165_family(chip) || 787 mv88e6xxx_6351_family(chip) || 788 mv88e6xxx_6352_family(chip); 789 } 790 return false; 791 } 792 793 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 794 struct mv88e6xxx_hw_stat *s, 795 int port) 796 { 797 u32 low; 798 u32 high = 0; 799 int ret; 800 u64 value; 801 802 switch (s->type) { 803 case PORT: 804 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg); 805 if (ret < 0) 806 return UINT64_MAX; 807 808 low = ret; 809 if (s->sizeof_stat == 4) { 810 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), 811 s->reg + 1); 812 if (ret < 0) 813 return UINT64_MAX; 814 high = ret; 815 } 816 break; 817 case BANK0: 818 case BANK1: 819 _mv88e6xxx_stats_read(chip, s->reg, &low); 820 if (s->sizeof_stat == 8) 821 _mv88e6xxx_stats_read(chip, s->reg + 1, &high); 822 } 823 value = (((u64)high) << 16) | low; 824 return value; 825 } 826 827 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 828 uint8_t *data) 829 { 830 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 831 struct mv88e6xxx_hw_stat *stat; 832 int i, j; 833 834 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 835 stat = &mv88e6xxx_hw_stats[i]; 836 if (mv88e6xxx_has_stat(chip, stat)) { 837 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 838 ETH_GSTRING_LEN); 839 j++; 840 } 841 } 842 } 843 844 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 845 { 846 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 847 struct mv88e6xxx_hw_stat *stat; 848 int i, j; 849 850 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 851 stat = &mv88e6xxx_hw_stats[i]; 852 if (mv88e6xxx_has_stat(chip, stat)) 853 j++; 854 } 855 return j; 856 } 857 858 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 859 uint64_t *data) 860 { 861 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 862 struct mv88e6xxx_hw_stat *stat; 863 int ret; 864 int i, j; 865 866 mutex_lock(&chip->reg_lock); 867 868 ret = _mv88e6xxx_stats_snapshot(chip, port); 869 if (ret < 0) { 870 mutex_unlock(&chip->reg_lock); 871 return; 872 } 873 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 874 stat = &mv88e6xxx_hw_stats[i]; 875 if (mv88e6xxx_has_stat(chip, stat)) { 876 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); 877 j++; 878 } 879 } 880 881 mutex_unlock(&chip->reg_lock); 882 } 883 884 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 885 { 886 return 32 * sizeof(u16); 887 } 888 889 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 890 struct ethtool_regs *regs, void *_p) 891 { 892 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 893 u16 *p = _p; 894 int i; 895 896 regs->version = 0; 897 898 memset(p, 0xff, 32 * sizeof(u16)); 899 900 mutex_lock(&chip->reg_lock); 901 902 for (i = 0; i < 32; i++) { 903 int ret; 904 905 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i); 906 if (ret >= 0) 907 p[i] = ret; 908 } 909 910 mutex_unlock(&chip->reg_lock); 911 } 912 913 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 914 { 915 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP, 916 GLOBAL_ATU_OP_BUSY); 917 } 918 919 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 920 struct ethtool_eee *e) 921 { 922 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 923 u16 reg; 924 int err; 925 926 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 927 return -EOPNOTSUPP; 928 929 mutex_lock(&chip->reg_lock); 930 931 err = mv88e6xxx_phy_read(chip, port, 16, ®); 932 if (err) 933 goto out; 934 935 e->eee_enabled = !!(reg & 0x0200); 936 e->tx_lpi_enabled = !!(reg & 0x0100); 937 938 err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, ®); 939 if (err) 940 goto out; 941 942 e->eee_active = !!(reg & PORT_STATUS_EEE); 943 out: 944 mutex_unlock(&chip->reg_lock); 945 946 return err; 947 } 948 949 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 950 struct phy_device *phydev, struct ethtool_eee *e) 951 { 952 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 953 u16 reg; 954 int err; 955 956 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 957 return -EOPNOTSUPP; 958 959 mutex_lock(&chip->reg_lock); 960 961 err = mv88e6xxx_phy_read(chip, port, 16, ®); 962 if (err) 963 goto out; 964 965 reg &= ~0x0300; 966 if (e->eee_enabled) 967 reg |= 0x0200; 968 if (e->tx_lpi_enabled) 969 reg |= 0x0100; 970 971 err = mv88e6xxx_phy_write(chip, port, 16, reg); 972 out: 973 mutex_unlock(&chip->reg_lock); 974 975 return err; 976 } 977 978 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 979 { 980 int ret; 981 982 if (mv88e6xxx_has_fid_reg(chip)) { 983 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID, 984 fid); 985 if (ret < 0) 986 return ret; 987 } else if (mv88e6xxx_num_databases(chip) == 256) { 988 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 989 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL); 990 if (ret < 0) 991 return ret; 992 993 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, 994 (ret & 0xfff) | 995 ((fid << 8) & 0xf000)); 996 if (ret < 0) 997 return ret; 998 999 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1000 cmd |= fid & 0xf; 1001 } 1002 1003 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd); 1004 if (ret < 0) 1005 return ret; 1006 1007 return _mv88e6xxx_atu_wait(chip); 1008 } 1009 1010 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 1011 struct mv88e6xxx_atu_entry *entry) 1012 { 1013 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1014 1015 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 1016 unsigned int mask, shift; 1017 1018 if (entry->trunk) { 1019 data |= GLOBAL_ATU_DATA_TRUNK; 1020 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 1021 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 1022 } else { 1023 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1024 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1025 } 1026 1027 data |= (entry->portv_trunkid << shift) & mask; 1028 } 1029 1030 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data); 1031 } 1032 1033 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1034 struct mv88e6xxx_atu_entry *entry, 1035 bool static_too) 1036 { 1037 int op; 1038 int err; 1039 1040 err = _mv88e6xxx_atu_wait(chip); 1041 if (err) 1042 return err; 1043 1044 err = _mv88e6xxx_atu_data_write(chip, entry); 1045 if (err) 1046 return err; 1047 1048 if (entry->fid) { 1049 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1050 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1051 } else { 1052 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1053 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1054 } 1055 1056 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1057 } 1058 1059 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1060 u16 fid, bool static_too) 1061 { 1062 struct mv88e6xxx_atu_entry entry = { 1063 .fid = fid, 1064 .state = 0, /* EntryState bits must be 0 */ 1065 }; 1066 1067 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1068 } 1069 1070 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1071 int from_port, int to_port, bool static_too) 1072 { 1073 struct mv88e6xxx_atu_entry entry = { 1074 .trunk = false, 1075 .fid = fid, 1076 }; 1077 1078 /* EntryState bits must be 0xF */ 1079 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1080 1081 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1082 entry.portv_trunkid = (to_port & 0x0f) << 4; 1083 entry.portv_trunkid |= from_port & 0x0f; 1084 1085 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1086 } 1087 1088 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1089 int port, bool static_too) 1090 { 1091 /* Destination port 0xF means remove the entries */ 1092 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1093 } 1094 1095 static const char * const mv88e6xxx_port_state_names[] = { 1096 [PORT_CONTROL_STATE_DISABLED] = "Disabled", 1097 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", 1098 [PORT_CONTROL_STATE_LEARNING] = "Learning", 1099 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", 1100 }; 1101 1102 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port, 1103 u8 state) 1104 { 1105 struct dsa_switch *ds = chip->ds; 1106 int reg, ret = 0; 1107 u8 oldstate; 1108 1109 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL); 1110 if (reg < 0) 1111 return reg; 1112 1113 oldstate = reg & PORT_CONTROL_STATE_MASK; 1114 1115 if (oldstate != state) { 1116 /* Flush forwarding database if we're moving a port 1117 * from Learning or Forwarding state to Disabled or 1118 * Blocking or Listening state. 1119 */ 1120 if ((oldstate == PORT_CONTROL_STATE_LEARNING || 1121 oldstate == PORT_CONTROL_STATE_FORWARDING) && 1122 (state == PORT_CONTROL_STATE_DISABLED || 1123 state == PORT_CONTROL_STATE_BLOCKING)) { 1124 ret = _mv88e6xxx_atu_remove(chip, 0, port, false); 1125 if (ret) 1126 return ret; 1127 } 1128 1129 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; 1130 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL, 1131 reg); 1132 if (ret) 1133 return ret; 1134 1135 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n", 1136 mv88e6xxx_port_state_names[state], 1137 mv88e6xxx_port_state_names[oldstate]); 1138 } 1139 1140 return ret; 1141 } 1142 1143 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1144 { 1145 struct net_device *bridge = chip->ports[port].bridge_dev; 1146 const u16 mask = (1 << chip->info->num_ports) - 1; 1147 struct dsa_switch *ds = chip->ds; 1148 u16 output_ports = 0; 1149 int reg; 1150 int i; 1151 1152 /* allow CPU port or DSA link(s) to send frames to every port */ 1153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1154 output_ports = mask; 1155 } else { 1156 for (i = 0; i < chip->info->num_ports; ++i) { 1157 /* allow sending frames to every group member */ 1158 if (bridge && chip->ports[i].bridge_dev == bridge) 1159 output_ports |= BIT(i); 1160 1161 /* allow sending frames to CPU port and DSA link(s) */ 1162 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1163 output_ports |= BIT(i); 1164 } 1165 } 1166 1167 /* prevent frames from going back out of the port they came in on */ 1168 output_ports &= ~BIT(port); 1169 1170 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN); 1171 if (reg < 0) 1172 return reg; 1173 1174 reg &= ~mask; 1175 reg |= output_ports & mask; 1176 1177 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg); 1178 } 1179 1180 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1181 u8 state) 1182 { 1183 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1184 int stp_state; 1185 int err; 1186 1187 switch (state) { 1188 case BR_STATE_DISABLED: 1189 stp_state = PORT_CONTROL_STATE_DISABLED; 1190 break; 1191 case BR_STATE_BLOCKING: 1192 case BR_STATE_LISTENING: 1193 stp_state = PORT_CONTROL_STATE_BLOCKING; 1194 break; 1195 case BR_STATE_LEARNING: 1196 stp_state = PORT_CONTROL_STATE_LEARNING; 1197 break; 1198 case BR_STATE_FORWARDING: 1199 default: 1200 stp_state = PORT_CONTROL_STATE_FORWARDING; 1201 break; 1202 } 1203 1204 mutex_lock(&chip->reg_lock); 1205 err = _mv88e6xxx_port_state(chip, port, stp_state); 1206 mutex_unlock(&chip->reg_lock); 1207 1208 if (err) 1209 netdev_err(ds->ports[port].netdev, 1210 "failed to update state to %s\n", 1211 mv88e6xxx_port_state_names[stp_state]); 1212 } 1213 1214 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port, 1215 u16 *new, u16 *old) 1216 { 1217 struct dsa_switch *ds = chip->ds; 1218 u16 pvid; 1219 int ret; 1220 1221 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN); 1222 if (ret < 0) 1223 return ret; 1224 1225 pvid = ret & PORT_DEFAULT_VLAN_MASK; 1226 1227 if (new) { 1228 ret &= ~PORT_DEFAULT_VLAN_MASK; 1229 ret |= *new & PORT_DEFAULT_VLAN_MASK; 1230 1231 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 1232 PORT_DEFAULT_VLAN, ret); 1233 if (ret < 0) 1234 return ret; 1235 1236 netdev_dbg(ds->ports[port].netdev, 1237 "DefaultVID %d (was %d)\n", *new, pvid); 1238 } 1239 1240 if (old) 1241 *old = pvid; 1242 1243 return 0; 1244 } 1245 1246 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip, 1247 int port, u16 *pvid) 1248 { 1249 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid); 1250 } 1251 1252 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip, 1253 int port, u16 pvid) 1254 { 1255 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL); 1256 } 1257 1258 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1259 { 1260 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP, 1261 GLOBAL_VTU_OP_BUSY); 1262 } 1263 1264 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1265 { 1266 int ret; 1267 1268 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op); 1269 if (ret < 0) 1270 return ret; 1271 1272 return _mv88e6xxx_vtu_wait(chip); 1273 } 1274 1275 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1276 { 1277 int ret; 1278 1279 ret = _mv88e6xxx_vtu_wait(chip); 1280 if (ret < 0) 1281 return ret; 1282 1283 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1284 } 1285 1286 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1287 struct mv88e6xxx_vtu_stu_entry *entry, 1288 unsigned int nibble_offset) 1289 { 1290 u16 regs[3]; 1291 int i; 1292 int ret; 1293 1294 for (i = 0; i < 3; ++i) { 1295 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 1296 GLOBAL_VTU_DATA_0_3 + i); 1297 if (ret < 0) 1298 return ret; 1299 1300 regs[i] = ret; 1301 } 1302 1303 for (i = 0; i < chip->info->num_ports; ++i) { 1304 unsigned int shift = (i % 4) * 4 + nibble_offset; 1305 u16 reg = regs[i / 4]; 1306 1307 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1314 struct mv88e6xxx_vtu_stu_entry *entry) 1315 { 1316 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1317 } 1318 1319 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1320 struct mv88e6xxx_vtu_stu_entry *entry) 1321 { 1322 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1323 } 1324 1325 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1326 struct mv88e6xxx_vtu_stu_entry *entry, 1327 unsigned int nibble_offset) 1328 { 1329 u16 regs[3] = { 0 }; 1330 int i; 1331 int ret; 1332 1333 for (i = 0; i < chip->info->num_ports; ++i) { 1334 unsigned int shift = (i % 4) * 4 + nibble_offset; 1335 u8 data = entry->data[i]; 1336 1337 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1338 } 1339 1340 for (i = 0; i < 3; ++i) { 1341 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 1342 GLOBAL_VTU_DATA_0_3 + i, regs[i]); 1343 if (ret < 0) 1344 return ret; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1351 struct mv88e6xxx_vtu_stu_entry *entry) 1352 { 1353 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1354 } 1355 1356 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1357 struct mv88e6xxx_vtu_stu_entry *entry) 1358 { 1359 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1360 } 1361 1362 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1363 { 1364 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, 1365 vid & GLOBAL_VTU_VID_MASK); 1366 } 1367 1368 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1369 struct mv88e6xxx_vtu_stu_entry *entry) 1370 { 1371 struct mv88e6xxx_vtu_stu_entry next = { 0 }; 1372 int ret; 1373 1374 ret = _mv88e6xxx_vtu_wait(chip); 1375 if (ret < 0) 1376 return ret; 1377 1378 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1379 if (ret < 0) 1380 return ret; 1381 1382 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); 1383 if (ret < 0) 1384 return ret; 1385 1386 next.vid = ret & GLOBAL_VTU_VID_MASK; 1387 next.valid = !!(ret & GLOBAL_VTU_VID_VALID); 1388 1389 if (next.valid) { 1390 ret = mv88e6xxx_vtu_data_read(chip, &next); 1391 if (ret < 0) 1392 return ret; 1393 1394 if (mv88e6xxx_has_fid_reg(chip)) { 1395 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 1396 GLOBAL_VTU_FID); 1397 if (ret < 0) 1398 return ret; 1399 1400 next.fid = ret & GLOBAL_VTU_FID_MASK; 1401 } else if (mv88e6xxx_num_databases(chip) == 256) { 1402 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1403 * VTU DBNum[3:0] are located in VTU Operation 3:0 1404 */ 1405 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 1406 GLOBAL_VTU_OP); 1407 if (ret < 0) 1408 return ret; 1409 1410 next.fid = (ret & 0xf00) >> 4; 1411 next.fid |= ret & 0xf; 1412 } 1413 1414 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1415 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 1416 GLOBAL_VTU_SID); 1417 if (ret < 0) 1418 return ret; 1419 1420 next.sid = ret & GLOBAL_VTU_SID_MASK; 1421 } 1422 } 1423 1424 *entry = next; 1425 return 0; 1426 } 1427 1428 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1429 struct switchdev_obj_port_vlan *vlan, 1430 int (*cb)(struct switchdev_obj *obj)) 1431 { 1432 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1433 struct mv88e6xxx_vtu_stu_entry next; 1434 u16 pvid; 1435 int err; 1436 1437 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1438 return -EOPNOTSUPP; 1439 1440 mutex_lock(&chip->reg_lock); 1441 1442 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); 1443 if (err) 1444 goto unlock; 1445 1446 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1447 if (err) 1448 goto unlock; 1449 1450 do { 1451 err = _mv88e6xxx_vtu_getnext(chip, &next); 1452 if (err) 1453 break; 1454 1455 if (!next.valid) 1456 break; 1457 1458 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1459 continue; 1460 1461 /* reinit and dump this VLAN obj */ 1462 vlan->vid_begin = next.vid; 1463 vlan->vid_end = next.vid; 1464 vlan->flags = 0; 1465 1466 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1467 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1468 1469 if (next.vid == pvid) 1470 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1471 1472 err = cb(&vlan->obj); 1473 if (err) 1474 break; 1475 } while (next.vid < GLOBAL_VTU_VID_MASK); 1476 1477 unlock: 1478 mutex_unlock(&chip->reg_lock); 1479 1480 return err; 1481 } 1482 1483 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1484 struct mv88e6xxx_vtu_stu_entry *entry) 1485 { 1486 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1487 u16 reg = 0; 1488 int ret; 1489 1490 ret = _mv88e6xxx_vtu_wait(chip); 1491 if (ret < 0) 1492 return ret; 1493 1494 if (!entry->valid) 1495 goto loadpurge; 1496 1497 /* Write port member tags */ 1498 ret = mv88e6xxx_vtu_data_write(chip, entry); 1499 if (ret < 0) 1500 return ret; 1501 1502 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1503 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1504 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, 1505 reg); 1506 if (ret < 0) 1507 return ret; 1508 } 1509 1510 if (mv88e6xxx_has_fid_reg(chip)) { 1511 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1512 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID, 1513 reg); 1514 if (ret < 0) 1515 return ret; 1516 } else if (mv88e6xxx_num_databases(chip) == 256) { 1517 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1518 * VTU DBNum[3:0] are located in VTU Operation 3:0 1519 */ 1520 op |= (entry->fid & 0xf0) << 8; 1521 op |= entry->fid & 0xf; 1522 } 1523 1524 reg = GLOBAL_VTU_VID_VALID; 1525 loadpurge: 1526 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1527 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); 1528 if (ret < 0) 1529 return ret; 1530 1531 return _mv88e6xxx_vtu_cmd(chip, op); 1532 } 1533 1534 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1535 struct mv88e6xxx_vtu_stu_entry *entry) 1536 { 1537 struct mv88e6xxx_vtu_stu_entry next = { 0 }; 1538 int ret; 1539 1540 ret = _mv88e6xxx_vtu_wait(chip); 1541 if (ret < 0) 1542 return ret; 1543 1544 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, 1545 sid & GLOBAL_VTU_SID_MASK); 1546 if (ret < 0) 1547 return ret; 1548 1549 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1550 if (ret < 0) 1551 return ret; 1552 1553 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID); 1554 if (ret < 0) 1555 return ret; 1556 1557 next.sid = ret & GLOBAL_VTU_SID_MASK; 1558 1559 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID); 1560 if (ret < 0) 1561 return ret; 1562 1563 next.valid = !!(ret & GLOBAL_VTU_VID_VALID); 1564 1565 if (next.valid) { 1566 ret = mv88e6xxx_stu_data_read(chip, &next); 1567 if (ret < 0) 1568 return ret; 1569 } 1570 1571 *entry = next; 1572 return 0; 1573 } 1574 1575 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1576 struct mv88e6xxx_vtu_stu_entry *entry) 1577 { 1578 u16 reg = 0; 1579 int ret; 1580 1581 ret = _mv88e6xxx_vtu_wait(chip); 1582 if (ret < 0) 1583 return ret; 1584 1585 if (!entry->valid) 1586 goto loadpurge; 1587 1588 /* Write port states */ 1589 ret = mv88e6xxx_stu_data_write(chip, entry); 1590 if (ret < 0) 1591 return ret; 1592 1593 reg = GLOBAL_VTU_VID_VALID; 1594 loadpurge: 1595 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg); 1596 if (ret < 0) 1597 return ret; 1598 1599 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1600 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg); 1601 if (ret < 0) 1602 return ret; 1603 1604 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1605 } 1606 1607 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port, 1608 u16 *new, u16 *old) 1609 { 1610 struct dsa_switch *ds = chip->ds; 1611 u16 upper_mask; 1612 u16 fid; 1613 int ret; 1614 1615 if (mv88e6xxx_num_databases(chip) == 4096) 1616 upper_mask = 0xff; 1617 else if (mv88e6xxx_num_databases(chip) == 256) 1618 upper_mask = 0xf; 1619 else 1620 return -EOPNOTSUPP; 1621 1622 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ 1623 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN); 1624 if (ret < 0) 1625 return ret; 1626 1627 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; 1628 1629 if (new) { 1630 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK; 1631 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; 1632 1633 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, 1634 ret); 1635 if (ret < 0) 1636 return ret; 1637 } 1638 1639 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ 1640 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1); 1641 if (ret < 0) 1642 return ret; 1643 1644 fid |= (ret & upper_mask) << 4; 1645 1646 if (new) { 1647 ret &= ~upper_mask; 1648 ret |= (*new >> 4) & upper_mask; 1649 1650 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1, 1651 ret); 1652 if (ret < 0) 1653 return ret; 1654 1655 netdev_dbg(ds->ports[port].netdev, 1656 "FID %d (was %d)\n", *new, fid); 1657 } 1658 1659 if (old) 1660 *old = fid; 1661 1662 return 0; 1663 } 1664 1665 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip, 1666 int port, u16 *fid) 1667 { 1668 return _mv88e6xxx_port_fid(chip, port, NULL, fid); 1669 } 1670 1671 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip, 1672 int port, u16 fid) 1673 { 1674 return _mv88e6xxx_port_fid(chip, port, &fid, NULL); 1675 } 1676 1677 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1678 { 1679 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1680 struct mv88e6xxx_vtu_stu_entry vlan; 1681 int i, err; 1682 1683 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1684 1685 /* Set every FID bit used by the (un)bridged ports */ 1686 for (i = 0; i < chip->info->num_ports; ++i) { 1687 err = _mv88e6xxx_port_fid_get(chip, i, fid); 1688 if (err) 1689 return err; 1690 1691 set_bit(*fid, fid_bitmap); 1692 } 1693 1694 /* Set every FID bit used by the VLAN entries */ 1695 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1696 if (err) 1697 return err; 1698 1699 do { 1700 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1701 if (err) 1702 return err; 1703 1704 if (!vlan.valid) 1705 break; 1706 1707 set_bit(vlan.fid, fid_bitmap); 1708 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1709 1710 /* The reset value 0x000 is used to indicate that multiple address 1711 * databases are not needed. Return the next positive available. 1712 */ 1713 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1714 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1715 return -ENOSPC; 1716 1717 /* Clear the database */ 1718 return _mv88e6xxx_atu_flush(chip, *fid, true); 1719 } 1720 1721 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1722 struct mv88e6xxx_vtu_stu_entry *entry) 1723 { 1724 struct dsa_switch *ds = chip->ds; 1725 struct mv88e6xxx_vtu_stu_entry vlan = { 1726 .valid = true, 1727 .vid = vid, 1728 }; 1729 int i, err; 1730 1731 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1732 if (err) 1733 return err; 1734 1735 /* exclude all ports except the CPU and DSA ports */ 1736 for (i = 0; i < chip->info->num_ports; ++i) 1737 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1738 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1739 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1740 1741 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1742 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { 1743 struct mv88e6xxx_vtu_stu_entry vstp; 1744 1745 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1746 * implemented, only one STU entry is needed to cover all VTU 1747 * entries. Thus, validate the SID 0. 1748 */ 1749 vlan.sid = 0; 1750 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1751 if (err) 1752 return err; 1753 1754 if (vstp.sid != vlan.sid || !vstp.valid) { 1755 memset(&vstp, 0, sizeof(vstp)); 1756 vstp.valid = true; 1757 vstp.sid = vlan.sid; 1758 1759 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1760 if (err) 1761 return err; 1762 } 1763 } 1764 1765 *entry = vlan; 1766 return 0; 1767 } 1768 1769 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1770 struct mv88e6xxx_vtu_stu_entry *entry, bool creat) 1771 { 1772 int err; 1773 1774 if (!vid) 1775 return -EINVAL; 1776 1777 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1778 if (err) 1779 return err; 1780 1781 err = _mv88e6xxx_vtu_getnext(chip, entry); 1782 if (err) 1783 return err; 1784 1785 if (entry->vid != vid || !entry->valid) { 1786 if (!creat) 1787 return -EOPNOTSUPP; 1788 /* -ENOENT would've been more appropriate, but switchdev expects 1789 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1790 */ 1791 1792 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1793 } 1794 1795 return err; 1796 } 1797 1798 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1799 u16 vid_begin, u16 vid_end) 1800 { 1801 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1802 struct mv88e6xxx_vtu_stu_entry vlan; 1803 int i, err; 1804 1805 if (!vid_begin) 1806 return -EOPNOTSUPP; 1807 1808 mutex_lock(&chip->reg_lock); 1809 1810 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1811 if (err) 1812 goto unlock; 1813 1814 do { 1815 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1816 if (err) 1817 goto unlock; 1818 1819 if (!vlan.valid) 1820 break; 1821 1822 if (vlan.vid > vid_end) 1823 break; 1824 1825 for (i = 0; i < chip->info->num_ports; ++i) { 1826 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1827 continue; 1828 1829 if (vlan.data[i] == 1830 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1831 continue; 1832 1833 if (chip->ports[i].bridge_dev == 1834 chip->ports[port].bridge_dev) 1835 break; /* same bridge, check next VLAN */ 1836 1837 netdev_warn(ds->ports[port].netdev, 1838 "hardware VLAN %d already used by %s\n", 1839 vlan.vid, 1840 netdev_name(chip->ports[i].bridge_dev)); 1841 err = -EOPNOTSUPP; 1842 goto unlock; 1843 } 1844 } while (vlan.vid < vid_end); 1845 1846 unlock: 1847 mutex_unlock(&chip->reg_lock); 1848 1849 return err; 1850 } 1851 1852 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1853 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", 1854 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", 1855 [PORT_CONTROL_2_8021Q_CHECK] = "Check", 1856 [PORT_CONTROL_2_8021Q_SECURE] = "Secure", 1857 }; 1858 1859 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1860 bool vlan_filtering) 1861 { 1862 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1863 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1864 PORT_CONTROL_2_8021Q_DISABLED; 1865 int ret; 1866 1867 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1868 return -EOPNOTSUPP; 1869 1870 mutex_lock(&chip->reg_lock); 1871 1872 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2); 1873 if (ret < 0) 1874 goto unlock; 1875 1876 old = ret & PORT_CONTROL_2_8021Q_MASK; 1877 1878 if (new != old) { 1879 ret &= ~PORT_CONTROL_2_8021Q_MASK; 1880 ret |= new & PORT_CONTROL_2_8021Q_MASK; 1881 1882 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2, 1883 ret); 1884 if (ret < 0) 1885 goto unlock; 1886 1887 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n", 1888 mv88e6xxx_port_8021q_mode_names[new], 1889 mv88e6xxx_port_8021q_mode_names[old]); 1890 } 1891 1892 ret = 0; 1893 unlock: 1894 mutex_unlock(&chip->reg_lock); 1895 1896 return ret; 1897 } 1898 1899 static int 1900 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1901 const struct switchdev_obj_port_vlan *vlan, 1902 struct switchdev_trans *trans) 1903 { 1904 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1905 int err; 1906 1907 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1908 return -EOPNOTSUPP; 1909 1910 /* If the requested port doesn't belong to the same bridge as the VLAN 1911 * members, do not support it (yet) and fallback to software VLAN. 1912 */ 1913 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1914 vlan->vid_end); 1915 if (err) 1916 return err; 1917 1918 /* We don't need any dynamic resource from the kernel (yet), 1919 * so skip the prepare phase. 1920 */ 1921 return 0; 1922 } 1923 1924 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1925 u16 vid, bool untagged) 1926 { 1927 struct mv88e6xxx_vtu_stu_entry vlan; 1928 int err; 1929 1930 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1931 if (err) 1932 return err; 1933 1934 vlan.data[port] = untagged ? 1935 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1936 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1937 1938 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1939 } 1940 1941 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1942 const struct switchdev_obj_port_vlan *vlan, 1943 struct switchdev_trans *trans) 1944 { 1945 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 1946 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1947 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1948 u16 vid; 1949 1950 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1951 return; 1952 1953 mutex_lock(&chip->reg_lock); 1954 1955 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1956 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1957 netdev_err(ds->ports[port].netdev, 1958 "failed to add VLAN %d%c\n", 1959 vid, untagged ? 'u' : 't'); 1960 1961 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end)) 1962 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1963 vlan->vid_end); 1964 1965 mutex_unlock(&chip->reg_lock); 1966 } 1967 1968 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1969 int port, u16 vid) 1970 { 1971 struct dsa_switch *ds = chip->ds; 1972 struct mv88e6xxx_vtu_stu_entry vlan; 1973 int i, err; 1974 1975 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1976 if (err) 1977 return err; 1978 1979 /* Tell switchdev if this VLAN is handled in software */ 1980 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1981 return -EOPNOTSUPP; 1982 1983 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1984 1985 /* keep the VLAN unless all ports are excluded */ 1986 vlan.valid = false; 1987 for (i = 0; i < chip->info->num_ports; ++i) { 1988 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1989 continue; 1990 1991 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1992 vlan.valid = true; 1993 break; 1994 } 1995 } 1996 1997 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1998 if (err) 1999 return err; 2000 2001 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 2002 } 2003 2004 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2005 const struct switchdev_obj_port_vlan *vlan) 2006 { 2007 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2008 u16 pvid, vid; 2009 int err = 0; 2010 2011 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 2012 return -EOPNOTSUPP; 2013 2014 mutex_lock(&chip->reg_lock); 2015 2016 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); 2017 if (err) 2018 goto unlock; 2019 2020 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2021 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 2022 if (err) 2023 goto unlock; 2024 2025 if (vid == pvid) { 2026 err = _mv88e6xxx_port_pvid_set(chip, port, 0); 2027 if (err) 2028 goto unlock; 2029 } 2030 } 2031 2032 unlock: 2033 mutex_unlock(&chip->reg_lock); 2034 2035 return err; 2036 } 2037 2038 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 2039 const unsigned char *addr) 2040 { 2041 int i, ret; 2042 2043 for (i = 0; i < 3; i++) { 2044 ret = _mv88e6xxx_reg_write( 2045 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, 2046 (addr[i * 2] << 8) | addr[i * 2 + 1]); 2047 if (ret < 0) 2048 return ret; 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 2055 unsigned char *addr) 2056 { 2057 int i, ret; 2058 2059 for (i = 0; i < 3; i++) { 2060 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 2061 GLOBAL_ATU_MAC_01 + i); 2062 if (ret < 0) 2063 return ret; 2064 addr[i * 2] = ret >> 8; 2065 addr[i * 2 + 1] = ret & 0xff; 2066 } 2067 2068 return 0; 2069 } 2070 2071 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 2072 struct mv88e6xxx_atu_entry *entry) 2073 { 2074 int ret; 2075 2076 ret = _mv88e6xxx_atu_wait(chip); 2077 if (ret < 0) 2078 return ret; 2079 2080 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2081 if (ret < 0) 2082 return ret; 2083 2084 ret = _mv88e6xxx_atu_data_write(chip, entry); 2085 if (ret < 0) 2086 return ret; 2087 2088 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2089 } 2090 2091 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port, 2092 const unsigned char *addr, u16 vid, 2093 u8 state) 2094 { 2095 struct mv88e6xxx_atu_entry entry = { 0 }; 2096 struct mv88e6xxx_vtu_stu_entry vlan; 2097 int err; 2098 2099 /* Null VLAN ID corresponds to the port private database */ 2100 if (vid == 0) 2101 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid); 2102 else 2103 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2104 if (err) 2105 return err; 2106 2107 entry.fid = vlan.fid; 2108 entry.state = state; 2109 ether_addr_copy(entry.mac, addr); 2110 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2111 entry.trunk = false; 2112 entry.portv_trunkid = BIT(port); 2113 } 2114 2115 return _mv88e6xxx_atu_load(chip, &entry); 2116 } 2117 2118 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2119 const struct switchdev_obj_port_fdb *fdb, 2120 struct switchdev_trans *trans) 2121 { 2122 /* We don't need any dynamic resource from the kernel (yet), 2123 * so skip the prepare phase. 2124 */ 2125 return 0; 2126 } 2127 2128 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2129 const struct switchdev_obj_port_fdb *fdb, 2130 struct switchdev_trans *trans) 2131 { 2132 int state = is_multicast_ether_addr(fdb->addr) ? 2133 GLOBAL_ATU_DATA_STATE_MC_STATIC : 2134 GLOBAL_ATU_DATA_STATE_UC_STATIC; 2135 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2136 2137 mutex_lock(&chip->reg_lock); 2138 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state)) 2139 netdev_err(ds->ports[port].netdev, 2140 "failed to load MAC address\n"); 2141 mutex_unlock(&chip->reg_lock); 2142 } 2143 2144 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2145 const struct switchdev_obj_port_fdb *fdb) 2146 { 2147 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2148 int ret; 2149 2150 mutex_lock(&chip->reg_lock); 2151 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, 2152 GLOBAL_ATU_DATA_STATE_UNUSED); 2153 mutex_unlock(&chip->reg_lock); 2154 2155 return ret; 2156 } 2157 2158 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2159 struct mv88e6xxx_atu_entry *entry) 2160 { 2161 struct mv88e6xxx_atu_entry next = { 0 }; 2162 int ret; 2163 2164 next.fid = fid; 2165 2166 ret = _mv88e6xxx_atu_wait(chip); 2167 if (ret < 0) 2168 return ret; 2169 2170 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2171 if (ret < 0) 2172 return ret; 2173 2174 ret = _mv88e6xxx_atu_mac_read(chip, next.mac); 2175 if (ret < 0) 2176 return ret; 2177 2178 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA); 2179 if (ret < 0) 2180 return ret; 2181 2182 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; 2183 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2184 unsigned int mask, shift; 2185 2186 if (ret & GLOBAL_ATU_DATA_TRUNK) { 2187 next.trunk = true; 2188 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2189 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2190 } else { 2191 next.trunk = false; 2192 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2193 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2194 } 2195 2196 next.portv_trunkid = (ret & mask) >> shift; 2197 } 2198 2199 *entry = next; 2200 return 0; 2201 } 2202 2203 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip, 2204 u16 fid, u16 vid, int port, 2205 struct switchdev_obj_port_fdb *fdb, 2206 int (*cb)(struct switchdev_obj *obj)) 2207 { 2208 struct mv88e6xxx_atu_entry addr = { 2209 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2210 }; 2211 int err; 2212 2213 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2214 if (err) 2215 return err; 2216 2217 do { 2218 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2219 if (err) 2220 break; 2221 2222 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2223 break; 2224 2225 if (!addr.trunk && addr.portv_trunkid & BIT(port)) { 2226 bool is_static = addr.state == 2227 (is_multicast_ether_addr(addr.mac) ? 2228 GLOBAL_ATU_DATA_STATE_MC_STATIC : 2229 GLOBAL_ATU_DATA_STATE_UC_STATIC); 2230 2231 fdb->vid = vid; 2232 ether_addr_copy(fdb->addr, addr.mac); 2233 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 2234 2235 err = cb(&fdb->obj); 2236 if (err) 2237 break; 2238 } 2239 } while (!is_broadcast_ether_addr(addr.mac)); 2240 2241 return err; 2242 } 2243 2244 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2245 struct switchdev_obj_port_fdb *fdb, 2246 int (*cb)(struct switchdev_obj *obj)) 2247 { 2248 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2249 struct mv88e6xxx_vtu_stu_entry vlan = { 2250 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2251 }; 2252 u16 fid; 2253 int err; 2254 2255 mutex_lock(&chip->reg_lock); 2256 2257 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2258 err = _mv88e6xxx_port_fid_get(chip, port, &fid); 2259 if (err) 2260 goto unlock; 2261 2262 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb); 2263 if (err) 2264 goto unlock; 2265 2266 /* Dump VLANs' Filtering Information Databases */ 2267 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2268 if (err) 2269 goto unlock; 2270 2271 do { 2272 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2273 if (err) 2274 break; 2275 2276 if (!vlan.valid) 2277 break; 2278 2279 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid, 2280 port, fdb, cb); 2281 if (err) 2282 break; 2283 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2284 2285 unlock: 2286 mutex_unlock(&chip->reg_lock); 2287 2288 return err; 2289 } 2290 2291 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2292 struct net_device *bridge) 2293 { 2294 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2295 int i, err = 0; 2296 2297 mutex_lock(&chip->reg_lock); 2298 2299 /* Assign the bridge and remap each port's VLANTable */ 2300 chip->ports[port].bridge_dev = bridge; 2301 2302 for (i = 0; i < chip->info->num_ports; ++i) { 2303 if (chip->ports[i].bridge_dev == bridge) { 2304 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2305 if (err) 2306 break; 2307 } 2308 } 2309 2310 mutex_unlock(&chip->reg_lock); 2311 2312 return err; 2313 } 2314 2315 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2316 { 2317 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2318 struct net_device *bridge = chip->ports[port].bridge_dev; 2319 int i; 2320 2321 mutex_lock(&chip->reg_lock); 2322 2323 /* Unassign the bridge and remap each port's VLANTable */ 2324 chip->ports[port].bridge_dev = NULL; 2325 2326 for (i = 0; i < chip->info->num_ports; ++i) 2327 if (i == port || chip->ports[i].bridge_dev == bridge) 2328 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2329 netdev_warn(ds->ports[i].netdev, 2330 "failed to remap\n"); 2331 2332 mutex_unlock(&chip->reg_lock); 2333 } 2334 2335 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2336 { 2337 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); 2338 u16 is_reset = (ppu_active ? 0x8800 : 0xc800); 2339 struct gpio_desc *gpiod = chip->reset; 2340 unsigned long timeout; 2341 int ret; 2342 int i; 2343 2344 /* Set all ports to the disabled state. */ 2345 for (i = 0; i < chip->info->num_ports; i++) { 2346 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL); 2347 if (ret < 0) 2348 return ret; 2349 2350 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL, 2351 ret & 0xfffc); 2352 if (ret) 2353 return ret; 2354 } 2355 2356 /* Wait for transmit queues to drain. */ 2357 usleep_range(2000, 4000); 2358 2359 /* If there is a gpio connected to the reset pin, toggle it */ 2360 if (gpiod) { 2361 gpiod_set_value_cansleep(gpiod, 1); 2362 usleep_range(10000, 20000); 2363 gpiod_set_value_cansleep(gpiod, 0); 2364 usleep_range(10000, 20000); 2365 } 2366 2367 /* Reset the switch. Keep the PPU active if requested. The PPU 2368 * needs to be active to support indirect phy register access 2369 * through global registers 0x18 and 0x19. 2370 */ 2371 if (ppu_active) 2372 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000); 2373 else 2374 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400); 2375 if (ret) 2376 return ret; 2377 2378 /* Wait up to one second for reset to complete. */ 2379 timeout = jiffies + 1 * HZ; 2380 while (time_before(jiffies, timeout)) { 2381 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00); 2382 if (ret < 0) 2383 return ret; 2384 2385 if ((ret & is_reset) == is_reset) 2386 break; 2387 usleep_range(1000, 2000); 2388 } 2389 if (time_after(jiffies, timeout)) 2390 ret = -ETIMEDOUT; 2391 else 2392 ret = 0; 2393 2394 return ret; 2395 } 2396 2397 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2398 { 2399 u16 val; 2400 int err; 2401 2402 /* Clear Power Down bit */ 2403 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2404 if (err) 2405 return err; 2406 2407 if (val & BMCR_PDOWN) { 2408 val &= ~BMCR_PDOWN; 2409 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2410 } 2411 2412 return err; 2413 } 2414 2415 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, 2416 int reg, u16 *val) 2417 { 2418 int addr = chip->info->port_base_addr + port; 2419 2420 if (port >= chip->info->num_ports) 2421 return -EINVAL; 2422 2423 return mv88e6xxx_read(chip, addr, reg, val); 2424 } 2425 2426 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2427 { 2428 struct dsa_switch *ds = chip->ds; 2429 int ret; 2430 u16 reg; 2431 2432 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2433 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2434 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || 2435 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) { 2436 /* MAC Forcing register: don't force link, speed, 2437 * duplex or flow control state to any particular 2438 * values on physical ports, but force the CPU port 2439 * and all DSA ports to their maximum bandwidth and 2440 * full duplex. 2441 */ 2442 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL); 2443 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 2444 reg &= ~PORT_PCS_CTRL_UNFORCED; 2445 reg |= PORT_PCS_CTRL_FORCE_LINK | 2446 PORT_PCS_CTRL_LINK_UP | 2447 PORT_PCS_CTRL_DUPLEX_FULL | 2448 PORT_PCS_CTRL_FORCE_DUPLEX; 2449 if (mv88e6xxx_6065_family(chip)) 2450 reg |= PORT_PCS_CTRL_100; 2451 else 2452 reg |= PORT_PCS_CTRL_1000; 2453 } else { 2454 reg |= PORT_PCS_CTRL_UNFORCED; 2455 } 2456 2457 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2458 PORT_PCS_CTRL, reg); 2459 if (ret) 2460 return ret; 2461 } 2462 2463 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2464 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2465 * tunneling, determine priority by looking at 802.1p and IP 2466 * priority fields (IP prio has precedence), and set STP state 2467 * to Forwarding. 2468 * 2469 * If this is the CPU link, use DSA or EDSA tagging depending 2470 * on which tagging mode was configured. 2471 * 2472 * If this is a link to another switch, use DSA tagging mode. 2473 * 2474 * If this is the upstream port for this switch, enable 2475 * forwarding of unknown unicasts and multicasts. 2476 */ 2477 reg = 0; 2478 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2479 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2480 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || 2481 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) 2482 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2483 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2484 PORT_CONTROL_STATE_FORWARDING; 2485 if (dsa_is_cpu_port(ds, port)) { 2486 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) 2487 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | 2488 PORT_CONTROL_FORWARD_UNKNOWN | 2489 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2490 else 2491 reg |= PORT_CONTROL_DSA_TAG; 2492 reg |= PORT_CONTROL_EGRESS_ADD_TAG; 2493 } 2494 if (dsa_is_dsa_port(ds, port)) { 2495 if (mv88e6xxx_6095_family(chip) || 2496 mv88e6xxx_6185_family(chip)) 2497 reg |= PORT_CONTROL_DSA_TAG; 2498 if (mv88e6xxx_6352_family(chip) || 2499 mv88e6xxx_6351_family(chip) || 2500 mv88e6xxx_6165_family(chip) || 2501 mv88e6xxx_6097_family(chip) || 2502 mv88e6xxx_6320_family(chip)) { 2503 reg |= PORT_CONTROL_FRAME_MODE_DSA; 2504 } 2505 2506 if (port == dsa_upstream_port(ds)) 2507 reg |= PORT_CONTROL_FORWARD_UNKNOWN | 2508 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2509 } 2510 if (reg) { 2511 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2512 PORT_CONTROL, reg); 2513 if (ret) 2514 return ret; 2515 } 2516 2517 /* If this port is connected to a SerDes, make sure the SerDes is not 2518 * powered down. 2519 */ 2520 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2521 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS); 2522 if (ret < 0) 2523 return ret; 2524 ret &= PORT_STATUS_CMODE_MASK; 2525 if ((ret == PORT_STATUS_CMODE_100BASE_X) || 2526 (ret == PORT_STATUS_CMODE_1000BASE_X) || 2527 (ret == PORT_STATUS_CMODE_SGMII)) { 2528 ret = mv88e6xxx_serdes_power_on(chip); 2529 if (ret < 0) 2530 return ret; 2531 } 2532 } 2533 2534 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2535 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2536 * untagged frames on this port, do a destination address lookup on all 2537 * received packets as usual, disable ARP mirroring and don't send a 2538 * copy of all transmitted/received frames on this port to the CPU. 2539 */ 2540 reg = 0; 2541 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2542 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2543 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || 2544 mv88e6xxx_6185_family(chip)) 2545 reg = PORT_CONTROL_2_MAP_DA; 2546 2547 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2548 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) 2549 reg |= PORT_CONTROL_2_JUMBO_10240; 2550 2551 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { 2552 /* Set the upstream port this port should use */ 2553 reg |= dsa_upstream_port(ds); 2554 /* enable forwarding of unknown multicast addresses to 2555 * the upstream port 2556 */ 2557 if (port == dsa_upstream_port(ds)) 2558 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; 2559 } 2560 2561 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2562 2563 if (reg) { 2564 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2565 PORT_CONTROL_2, reg); 2566 if (ret) 2567 return ret; 2568 } 2569 2570 /* Port Association Vector: when learning source addresses 2571 * of packets, add the address to the address database using 2572 * a port bitmap that has only the bit for this port set and 2573 * the other bits clear. 2574 */ 2575 reg = 1 << port; 2576 /* Disable learning for CPU port */ 2577 if (dsa_is_cpu_port(ds, port)) 2578 reg = 0; 2579 2580 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR, 2581 reg); 2582 if (ret) 2583 return ret; 2584 2585 /* Egress rate control 2: disable egress rate control. */ 2586 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2, 2587 0x0000); 2588 if (ret) 2589 return ret; 2590 2591 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2592 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2593 mv88e6xxx_6320_family(chip)) { 2594 /* Do not limit the period of time that this port can 2595 * be paused for by the remote end or the period of 2596 * time that this port can pause the remote end. 2597 */ 2598 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2599 PORT_PAUSE_CTRL, 0x0000); 2600 if (ret) 2601 return ret; 2602 2603 /* Port ATU control: disable limiting the number of 2604 * address database entries that this port is allowed 2605 * to use. 2606 */ 2607 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2608 PORT_ATU_CONTROL, 0x0000); 2609 /* Priority Override: disable DA, SA and VTU priority 2610 * override. 2611 */ 2612 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2613 PORT_PRI_OVERRIDE, 0x0000); 2614 if (ret) 2615 return ret; 2616 2617 /* Port Ethertype: use the Ethertype DSA Ethertype 2618 * value. 2619 */ 2620 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) { 2621 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2622 PORT_ETH_TYPE, ETH_P_EDSA); 2623 if (ret) 2624 return ret; 2625 } 2626 2627 /* Tag Remap: use an identity 802.1p prio -> switch 2628 * prio mapping. 2629 */ 2630 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2631 PORT_TAG_REGMAP_0123, 0x3210); 2632 if (ret) 2633 return ret; 2634 2635 /* Tag Remap 2: use an identity 802.1p prio -> switch 2636 * prio mapping. 2637 */ 2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2639 PORT_TAG_REGMAP_4567, 0x7654); 2640 if (ret) 2641 return ret; 2642 } 2643 2644 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2645 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2646 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || 2647 mv88e6xxx_6320_family(chip)) { 2648 /* Rate Control: disable ingress rate limiting. */ 2649 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), 2650 PORT_RATE_CONTROL, 0x0001); 2651 if (ret) 2652 return ret; 2653 } 2654 2655 /* Port Control 1: disable trunking, disable sending 2656 * learning messages to this port. 2657 */ 2658 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1, 2659 0x0000); 2660 if (ret) 2661 return ret; 2662 2663 /* Port based VLAN map: give each port the same default address 2664 * database, and allow bidirectional communication between the 2665 * CPU and DSA port(s), and the other ports. 2666 */ 2667 ret = _mv88e6xxx_port_fid_set(chip, port, 0); 2668 if (ret) 2669 return ret; 2670 2671 ret = _mv88e6xxx_port_based_vlan_map(chip, port); 2672 if (ret) 2673 return ret; 2674 2675 /* Default VLAN ID and priority: don't set a default VLAN 2676 * ID, and set the default packet priority to zero. 2677 */ 2678 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN, 2679 0x0000); 2680 if (ret) 2681 return ret; 2682 2683 return 0; 2684 } 2685 2686 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2687 { 2688 int err; 2689 2690 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01, 2691 (addr[0] << 8) | addr[1]); 2692 if (err) 2693 return err; 2694 2695 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23, 2696 (addr[2] << 8) | addr[3]); 2697 if (err) 2698 return err; 2699 2700 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45, 2701 (addr[4] << 8) | addr[5]); 2702 } 2703 2704 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2705 unsigned int msecs) 2706 { 2707 const unsigned int coeff = chip->info->age_time_coeff; 2708 const unsigned int min = 0x01 * coeff; 2709 const unsigned int max = 0xff * coeff; 2710 u8 age_time; 2711 u16 val; 2712 int err; 2713 2714 if (msecs < min || msecs > max) 2715 return -ERANGE; 2716 2717 /* Round to nearest multiple of coeff */ 2718 age_time = (msecs + coeff / 2) / coeff; 2719 2720 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val); 2721 if (err) 2722 return err; 2723 2724 /* AgeTime is 11:4 bits */ 2725 val &= ~0xff0; 2726 val |= age_time << 4; 2727 2728 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val); 2729 } 2730 2731 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2732 unsigned int ageing_time) 2733 { 2734 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 2735 int err; 2736 2737 mutex_lock(&chip->reg_lock); 2738 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2739 mutex_unlock(&chip->reg_lock); 2740 2741 return err; 2742 } 2743 2744 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2745 { 2746 struct dsa_switch *ds = chip->ds; 2747 u32 upstream_port = dsa_upstream_port(ds); 2748 u16 reg; 2749 int err; 2750 2751 /* Enable the PHY Polling Unit if present, don't discard any packets, 2752 * and mask all interrupt sources. 2753 */ 2754 reg = 0; 2755 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || 2756 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) 2757 reg |= GLOBAL_CONTROL_PPU_ENABLE; 2758 2759 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg); 2760 if (err) 2761 return err; 2762 2763 /* Configure the upstream port, and configure it as the port to which 2764 * ingress and egress and ARP monitor frames are to be sent. 2765 */ 2766 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | 2767 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | 2768 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; 2769 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, 2770 reg); 2771 if (err) 2772 return err; 2773 2774 /* Disable remote management, and set the switch's DSA device number. */ 2775 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2, 2776 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2777 (ds->index & 0x1f)); 2778 if (err) 2779 return err; 2780 2781 /* Clear all the VTU and STU entries */ 2782 err = _mv88e6xxx_vtu_stu_flush(chip); 2783 if (err < 0) 2784 return err; 2785 2786 /* Set the default address aging time to 5 minutes, and 2787 * enable address learn messages to be sent to all message 2788 * ports. 2789 */ 2790 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, 2791 GLOBAL_ATU_CONTROL_LEARN2ALL); 2792 if (err) 2793 return err; 2794 2795 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2796 if (err) 2797 return err; 2798 2799 /* Clear all ATU entries */ 2800 err = _mv88e6xxx_atu_flush(chip, 0, true); 2801 if (err) 2802 return err; 2803 2804 /* Configure the IP ToS mapping registers. */ 2805 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); 2806 if (err) 2807 return err; 2808 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); 2809 if (err) 2810 return err; 2811 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); 2812 if (err) 2813 return err; 2814 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); 2815 if (err) 2816 return err; 2817 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); 2818 if (err) 2819 return err; 2820 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); 2821 if (err) 2822 return err; 2823 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); 2824 if (err) 2825 return err; 2826 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); 2827 if (err) 2828 return err; 2829 2830 /* Configure the IEEE 802.1p priority mapping register. */ 2831 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); 2832 if (err) 2833 return err; 2834 2835 /* Clear the statistics counters for all ports */ 2836 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP, 2837 GLOBAL_STATS_OP_FLUSH_ALL); 2838 if (err) 2839 return err; 2840 2841 /* Wait for the flush to complete. */ 2842 err = _mv88e6xxx_stats_wait(chip); 2843 if (err) 2844 return err; 2845 2846 return 0; 2847 } 2848 2849 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, 2850 int target, int port) 2851 { 2852 u16 val = (target << 8) | (port & 0xf); 2853 2854 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val); 2855 } 2856 2857 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip) 2858 { 2859 int target, port; 2860 int err; 2861 2862 /* Initialize the routing port to the 32 possible target devices */ 2863 for (target = 0; target < 32; ++target) { 2864 port = 0xf; 2865 2866 if (target < DSA_MAX_SWITCHES) { 2867 port = chip->ds->rtable[target]; 2868 if (port == DSA_RTABLE_NONE) 2869 port = 0xf; 2870 } 2871 2872 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 2873 if (err) 2874 break; 2875 } 2876 2877 return err; 2878 } 2879 2880 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 2881 bool hask, u16 mask) 2882 { 2883 const u16 port_mask = BIT(chip->info->num_ports) - 1; 2884 u16 val = (num << 12) | (mask & port_mask); 2885 2886 if (hask) 2887 val |= GLOBAL2_TRUNK_MASK_HASK; 2888 2889 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val); 2890 } 2891 2892 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 2893 u16 map) 2894 { 2895 const u16 port_mask = BIT(chip->info->num_ports) - 1; 2896 u16 val = (id << 11) | (map & port_mask); 2897 2898 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val); 2899 } 2900 2901 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip) 2902 { 2903 const u16 port_mask = BIT(chip->info->num_ports) - 1; 2904 int i, err; 2905 2906 /* Clear all eight possible Trunk Mask vectors */ 2907 for (i = 0; i < 8; ++i) { 2908 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask); 2909 if (err) 2910 return err; 2911 } 2912 2913 /* Clear all sixteen possible Trunk ID routing vectors */ 2914 for (i = 0; i < 16; ++i) { 2915 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0); 2916 if (err) 2917 return err; 2918 } 2919 2920 return 0; 2921 } 2922 2923 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip) 2924 { 2925 int port, err; 2926 2927 /* Init all Ingress Rate Limit resources of all ports */ 2928 for (port = 0; port < chip->info->num_ports; ++port) { 2929 /* XXX newer chips (like 88E6390) have different 2-bit ops */ 2930 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD, 2931 GLOBAL2_IRL_CMD_OP_INIT_ALL | 2932 (port << 8)); 2933 if (err) 2934 break; 2935 2936 /* Wait for the operation to complete */ 2937 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD, 2938 GLOBAL2_IRL_CMD_BUSY); 2939 if (err) 2940 break; 2941 } 2942 2943 return err; 2944 } 2945 2946 /* Indirect write to the Switch MAC/WoL/WoF register */ 2947 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip, 2948 unsigned int pointer, u8 data) 2949 { 2950 u16 val = (pointer << 8) | data; 2951 2952 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val); 2953 } 2954 2955 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2956 { 2957 int i, err; 2958 2959 for (i = 0; i < 6; i++) { 2960 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]); 2961 if (err) 2962 break; 2963 } 2964 2965 return err; 2966 } 2967 2968 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer, 2969 u8 data) 2970 { 2971 u16 val = (pointer << 8) | (data & 0x7); 2972 2973 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val); 2974 } 2975 2976 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip) 2977 { 2978 int i, err; 2979 2980 /* Clear all sixteen possible Priority Override entries */ 2981 for (i = 0; i < 16; i++) { 2982 err = mv88e6xxx_g2_pot_write(chip, i, 0); 2983 if (err) 2984 break; 2985 } 2986 2987 return err; 2988 } 2989 2990 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip) 2991 { 2992 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, 2993 GLOBAL2_EEPROM_CMD_BUSY | 2994 GLOBAL2_EEPROM_CMD_RUNNING); 2995 } 2996 2997 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 2998 { 2999 int err; 3000 3001 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd); 3002 if (err) 3003 return err; 3004 3005 return mv88e6xxx_g2_eeprom_wait(chip); 3006 } 3007 3008 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip, 3009 u8 addr, u16 *data) 3010 { 3011 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr; 3012 int err; 3013 3014 err = mv88e6xxx_g2_eeprom_wait(chip); 3015 if (err) 3016 return err; 3017 3018 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 3019 if (err) 3020 return err; 3021 3022 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); 3023 } 3024 3025 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip, 3026 u8 addr, u16 data) 3027 { 3028 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr; 3029 int err; 3030 3031 err = mv88e6xxx_g2_eeprom_wait(chip); 3032 if (err) 3033 return err; 3034 3035 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); 3036 if (err) 3037 return err; 3038 3039 return mv88e6xxx_g2_eeprom_cmd(chip, cmd); 3040 } 3041 3042 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip) 3043 { 3044 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, 3045 GLOBAL2_SMI_PHY_CMD_BUSY); 3046 } 3047 3048 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 3049 { 3050 int err; 3051 3052 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd); 3053 if (err) 3054 return err; 3055 3056 return mv88e6xxx_g2_smi_phy_wait(chip); 3057 } 3058 3059 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr, 3060 int reg, u16 *val) 3061 { 3062 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg; 3063 int err; 3064 3065 err = mv88e6xxx_g2_smi_phy_wait(chip); 3066 if (err) 3067 return err; 3068 3069 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 3070 if (err) 3071 return err; 3072 3073 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val); 3074 } 3075 3076 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, 3077 int reg, u16 val) 3078 { 3079 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg; 3080 int err; 3081 3082 err = mv88e6xxx_g2_smi_phy_wait(chip); 3083 if (err) 3084 return err; 3085 3086 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val); 3087 if (err) 3088 return err; 3089 3090 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 3091 } 3092 3093 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = { 3094 .read = mv88e6xxx_g2_smi_phy_read, 3095 .write = mv88e6xxx_g2_smi_phy_write, 3096 }; 3097 3098 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 3099 { 3100 u16 reg; 3101 int err; 3102 3103 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) { 3104 /* Consider the frames with reserved multicast destination 3105 * addresses matching 01:80:c2:00:00:2x as MGMT. 3106 */ 3107 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 3108 0xffff); 3109 if (err) 3110 return err; 3111 } 3112 3113 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) { 3114 /* Consider the frames with reserved multicast destination 3115 * addresses matching 01:80:c2:00:00:0x as MGMT. 3116 */ 3117 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 3118 0xffff); 3119 if (err) 3120 return err; 3121 } 3122 3123 /* Ignore removed tag data on doubly tagged packets, disable 3124 * flow control messages, force flow control priority to the 3125 * highest, and send all special multicast frames to the CPU 3126 * port at the highest priority. 3127 */ 3128 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4); 3129 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) || 3130 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) 3131 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7; 3132 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg); 3133 if (err) 3134 return err; 3135 3136 /* Program the DSA routing table. */ 3137 err = mv88e6xxx_g2_set_device_mapping(chip); 3138 if (err) 3139 return err; 3140 3141 /* Clear all trunk masks and mapping. */ 3142 err = mv88e6xxx_g2_clear_trunk(chip); 3143 if (err) 3144 return err; 3145 3146 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) { 3147 /* Disable ingress rate limiting by resetting all per port 3148 * ingress rate limit resources to their initial state. 3149 */ 3150 err = mv88e6xxx_g2_clear_irl(chip); 3151 if (err) 3152 return err; 3153 } 3154 3155 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) { 3156 /* Initialize Cross-chip Port VLAN Table to reset defaults */ 3157 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR, 3158 GLOBAL2_PVT_ADDR_OP_INIT_ONES); 3159 if (err) 3160 return err; 3161 } 3162 3163 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) { 3164 /* Clear the priority override table. */ 3165 err = mv88e6xxx_g2_clear_pot(chip); 3166 if (err) 3167 return err; 3168 } 3169 3170 return 0; 3171 } 3172 3173 static int mv88e6xxx_setup(struct dsa_switch *ds) 3174 { 3175 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3176 int err; 3177 int i; 3178 3179 chip->ds = ds; 3180 ds->slave_mii_bus = chip->mdio_bus; 3181 3182 mutex_lock(&chip->reg_lock); 3183 3184 err = mv88e6xxx_switch_reset(chip); 3185 if (err) 3186 goto unlock; 3187 3188 /* Setup Switch Port Registers */ 3189 for (i = 0; i < chip->info->num_ports; i++) { 3190 err = mv88e6xxx_setup_port(chip, i); 3191 if (err) 3192 goto unlock; 3193 } 3194 3195 /* Setup Switch Global 1 Registers */ 3196 err = mv88e6xxx_g1_setup(chip); 3197 if (err) 3198 goto unlock; 3199 3200 /* Setup Switch Global 2 Registers */ 3201 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 3202 err = mv88e6xxx_g2_setup(chip); 3203 if (err) 3204 goto unlock; 3205 } 3206 3207 unlock: 3208 mutex_unlock(&chip->reg_lock); 3209 3210 return err; 3211 } 3212 3213 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 3214 { 3215 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3216 int err; 3217 3218 mutex_lock(&chip->reg_lock); 3219 3220 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */ 3221 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC)) 3222 err = mv88e6xxx_g2_set_switch_mac(chip, addr); 3223 else 3224 err = mv88e6xxx_g1_set_switch_mac(chip, addr); 3225 3226 mutex_unlock(&chip->reg_lock); 3227 3228 return err; 3229 } 3230 3231 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3232 { 3233 struct mv88e6xxx_chip *chip = bus->priv; 3234 u16 val; 3235 int err; 3236 3237 if (phy >= chip->info->num_ports) 3238 return 0xffff; 3239 3240 mutex_lock(&chip->reg_lock); 3241 err = mv88e6xxx_phy_read(chip, phy, reg, &val); 3242 mutex_unlock(&chip->reg_lock); 3243 3244 return err ? err : val; 3245 } 3246 3247 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3248 { 3249 struct mv88e6xxx_chip *chip = bus->priv; 3250 int err; 3251 3252 if (phy >= chip->info->num_ports) 3253 return 0xffff; 3254 3255 mutex_lock(&chip->reg_lock); 3256 err = mv88e6xxx_phy_write(chip, phy, reg, val); 3257 mutex_unlock(&chip->reg_lock); 3258 3259 return err; 3260 } 3261 3262 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3263 struct device_node *np) 3264 { 3265 static int index; 3266 struct mii_bus *bus; 3267 int err; 3268 3269 if (np) 3270 chip->mdio_np = of_get_child_by_name(np, "mdio"); 3271 3272 bus = devm_mdiobus_alloc(chip->dev); 3273 if (!bus) 3274 return -ENOMEM; 3275 3276 bus->priv = (void *)chip; 3277 if (np) { 3278 bus->name = np->full_name; 3279 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 3280 } else { 3281 bus->name = "mv88e6xxx SMI"; 3282 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3283 } 3284 3285 bus->read = mv88e6xxx_mdio_read; 3286 bus->write = mv88e6xxx_mdio_write; 3287 bus->parent = chip->dev; 3288 3289 if (chip->mdio_np) 3290 err = of_mdiobus_register(bus, chip->mdio_np); 3291 else 3292 err = mdiobus_register(bus); 3293 if (err) { 3294 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3295 goto out; 3296 } 3297 chip->mdio_bus = bus; 3298 3299 return 0; 3300 3301 out: 3302 if (chip->mdio_np) 3303 of_node_put(chip->mdio_np); 3304 3305 return err; 3306 } 3307 3308 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) 3309 3310 { 3311 struct mii_bus *bus = chip->mdio_bus; 3312 3313 mdiobus_unregister(bus); 3314 3315 if (chip->mdio_np) 3316 of_node_put(chip->mdio_np); 3317 } 3318 3319 #ifdef CONFIG_NET_DSA_HWMON 3320 3321 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 3322 { 3323 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3324 u16 val; 3325 int ret; 3326 3327 *temp = 0; 3328 3329 mutex_lock(&chip->reg_lock); 3330 3331 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); 3332 if (ret < 0) 3333 goto error; 3334 3335 /* Enable temperature sensor */ 3336 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3337 if (ret < 0) 3338 goto error; 3339 3340 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); 3341 if (ret < 0) 3342 goto error; 3343 3344 /* Wait for temperature to stabilize */ 3345 usleep_range(10000, 12000); 3346 3347 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3348 if (ret < 0) 3349 goto error; 3350 3351 /* Disable temperature sensor */ 3352 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); 3353 if (ret < 0) 3354 goto error; 3355 3356 *temp = ((val & 0x1f) - 5) * 5; 3357 3358 error: 3359 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); 3360 mutex_unlock(&chip->reg_lock); 3361 return ret; 3362 } 3363 3364 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3365 { 3366 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3367 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3368 u16 val; 3369 int ret; 3370 3371 *temp = 0; 3372 3373 mutex_lock(&chip->reg_lock); 3374 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); 3375 mutex_unlock(&chip->reg_lock); 3376 if (ret < 0) 3377 return ret; 3378 3379 *temp = (val & 0xff) - 25; 3380 3381 return 0; 3382 } 3383 3384 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3385 { 3386 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3387 3388 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) 3389 return -EOPNOTSUPP; 3390 3391 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 3392 return mv88e63xx_get_temp(ds, temp); 3393 3394 return mv88e61xx_get_temp(ds, temp); 3395 } 3396 3397 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3398 { 3399 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3400 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3401 u16 val; 3402 int ret; 3403 3404 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3405 return -EOPNOTSUPP; 3406 3407 *temp = 0; 3408 3409 mutex_lock(&chip->reg_lock); 3410 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3411 mutex_unlock(&chip->reg_lock); 3412 if (ret < 0) 3413 return ret; 3414 3415 *temp = (((val >> 8) & 0x1f) * 5) - 25; 3416 3417 return 0; 3418 } 3419 3420 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3421 { 3422 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3423 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3424 u16 val; 3425 int err; 3426 3427 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3428 return -EOPNOTSUPP; 3429 3430 mutex_lock(&chip->reg_lock); 3431 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3432 if (err) 3433 goto unlock; 3434 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 3435 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, 3436 (val & 0xe0ff) | (temp << 8)); 3437 unlock: 3438 mutex_unlock(&chip->reg_lock); 3439 3440 return err; 3441 } 3442 3443 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3444 { 3445 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3446 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3447 u16 val; 3448 int ret; 3449 3450 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3451 return -EOPNOTSUPP; 3452 3453 *alarm = false; 3454 3455 mutex_lock(&chip->reg_lock); 3456 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3457 mutex_unlock(&chip->reg_lock); 3458 if (ret < 0) 3459 return ret; 3460 3461 *alarm = !!(val & 0x40); 3462 3463 return 0; 3464 } 3465 #endif /* CONFIG_NET_DSA_HWMON */ 3466 3467 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3468 { 3469 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3470 3471 return chip->eeprom_len; 3472 } 3473 3474 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip, 3475 struct ethtool_eeprom *eeprom, u8 *data) 3476 { 3477 unsigned int offset = eeprom->offset; 3478 unsigned int len = eeprom->len; 3479 u16 val; 3480 int err; 3481 3482 eeprom->len = 0; 3483 3484 if (offset & 1) { 3485 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 3486 if (err) 3487 return err; 3488 3489 *data++ = (val >> 8) & 0xff; 3490 3491 offset++; 3492 len--; 3493 eeprom->len++; 3494 } 3495 3496 while (len >= 2) { 3497 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 3498 if (err) 3499 return err; 3500 3501 *data++ = val & 0xff; 3502 *data++ = (val >> 8) & 0xff; 3503 3504 offset += 2; 3505 len -= 2; 3506 eeprom->len += 2; 3507 } 3508 3509 if (len) { 3510 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 3511 if (err) 3512 return err; 3513 3514 *data++ = val & 0xff; 3515 3516 offset++; 3517 len--; 3518 eeprom->len++; 3519 } 3520 3521 return 0; 3522 } 3523 3524 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3525 struct ethtool_eeprom *eeprom, u8 *data) 3526 { 3527 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3528 int err; 3529 3530 mutex_lock(&chip->reg_lock); 3531 3532 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) 3533 err = mv88e6xxx_get_eeprom16(chip, eeprom, data); 3534 else 3535 err = -EOPNOTSUPP; 3536 3537 mutex_unlock(&chip->reg_lock); 3538 3539 if (err) 3540 return err; 3541 3542 eeprom->magic = 0xc3ec4951; 3543 3544 return 0; 3545 } 3546 3547 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip, 3548 struct ethtool_eeprom *eeprom, u8 *data) 3549 { 3550 unsigned int offset = eeprom->offset; 3551 unsigned int len = eeprom->len; 3552 u16 val; 3553 int err; 3554 3555 /* Ensure the RO WriteEn bit is set */ 3556 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val); 3557 if (err) 3558 return err; 3559 3560 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN)) 3561 return -EROFS; 3562 3563 eeprom->len = 0; 3564 3565 if (offset & 1) { 3566 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 3567 if (err) 3568 return err; 3569 3570 val = (*data++ << 8) | (val & 0xff); 3571 3572 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 3573 if (err) 3574 return err; 3575 3576 offset++; 3577 len--; 3578 eeprom->len++; 3579 } 3580 3581 while (len >= 2) { 3582 val = *data++; 3583 val |= *data++ << 8; 3584 3585 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 3586 if (err) 3587 return err; 3588 3589 offset += 2; 3590 len -= 2; 3591 eeprom->len += 2; 3592 } 3593 3594 if (len) { 3595 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 3596 if (err) 3597 return err; 3598 3599 val = (val & 0xff00) | *data++; 3600 3601 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 3602 if (err) 3603 return err; 3604 3605 offset++; 3606 len--; 3607 eeprom->len++; 3608 } 3609 3610 return 0; 3611 } 3612 3613 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3614 struct ethtool_eeprom *eeprom, u8 *data) 3615 { 3616 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3617 int err; 3618 3619 if (eeprom->magic != 0xc3ec4951) 3620 return -EINVAL; 3621 3622 mutex_lock(&chip->reg_lock); 3623 3624 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16)) 3625 err = mv88e6xxx_set_eeprom16(chip, eeprom, data); 3626 else 3627 err = -EOPNOTSUPP; 3628 3629 mutex_unlock(&chip->reg_lock); 3630 3631 return err; 3632 } 3633 3634 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3635 [MV88E6085] = { 3636 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3637 .family = MV88E6XXX_FAMILY_6097, 3638 .name = "Marvell 88E6085", 3639 .num_databases = 4096, 3640 .num_ports = 10, 3641 .port_base_addr = 0x10, 3642 .age_time_coeff = 15000, 3643 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3644 }, 3645 3646 [MV88E6095] = { 3647 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3648 .family = MV88E6XXX_FAMILY_6095, 3649 .name = "Marvell 88E6095/88E6095F", 3650 .num_databases = 256, 3651 .num_ports = 11, 3652 .port_base_addr = 0x10, 3653 .age_time_coeff = 15000, 3654 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3655 }, 3656 3657 [MV88E6123] = { 3658 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3659 .family = MV88E6XXX_FAMILY_6165, 3660 .name = "Marvell 88E6123", 3661 .num_databases = 4096, 3662 .num_ports = 3, 3663 .port_base_addr = 0x10, 3664 .age_time_coeff = 15000, 3665 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3666 }, 3667 3668 [MV88E6131] = { 3669 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3670 .family = MV88E6XXX_FAMILY_6185, 3671 .name = "Marvell 88E6131", 3672 .num_databases = 256, 3673 .num_ports = 8, 3674 .port_base_addr = 0x10, 3675 .age_time_coeff = 15000, 3676 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3677 }, 3678 3679 [MV88E6161] = { 3680 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3681 .family = MV88E6XXX_FAMILY_6165, 3682 .name = "Marvell 88E6161", 3683 .num_databases = 4096, 3684 .num_ports = 6, 3685 .port_base_addr = 0x10, 3686 .age_time_coeff = 15000, 3687 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3688 }, 3689 3690 [MV88E6165] = { 3691 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3692 .family = MV88E6XXX_FAMILY_6165, 3693 .name = "Marvell 88E6165", 3694 .num_databases = 4096, 3695 .num_ports = 6, 3696 .port_base_addr = 0x10, 3697 .age_time_coeff = 15000, 3698 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3699 }, 3700 3701 [MV88E6171] = { 3702 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3703 .family = MV88E6XXX_FAMILY_6351, 3704 .name = "Marvell 88E6171", 3705 .num_databases = 4096, 3706 .num_ports = 7, 3707 .port_base_addr = 0x10, 3708 .age_time_coeff = 15000, 3709 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3710 }, 3711 3712 [MV88E6172] = { 3713 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3714 .family = MV88E6XXX_FAMILY_6352, 3715 .name = "Marvell 88E6172", 3716 .num_databases = 4096, 3717 .num_ports = 7, 3718 .port_base_addr = 0x10, 3719 .age_time_coeff = 15000, 3720 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3721 }, 3722 3723 [MV88E6175] = { 3724 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3725 .family = MV88E6XXX_FAMILY_6351, 3726 .name = "Marvell 88E6175", 3727 .num_databases = 4096, 3728 .num_ports = 7, 3729 .port_base_addr = 0x10, 3730 .age_time_coeff = 15000, 3731 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3732 }, 3733 3734 [MV88E6176] = { 3735 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3736 .family = MV88E6XXX_FAMILY_6352, 3737 .name = "Marvell 88E6176", 3738 .num_databases = 4096, 3739 .num_ports = 7, 3740 .port_base_addr = 0x10, 3741 .age_time_coeff = 15000, 3742 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3743 }, 3744 3745 [MV88E6185] = { 3746 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 3747 .family = MV88E6XXX_FAMILY_6185, 3748 .name = "Marvell 88E6185", 3749 .num_databases = 256, 3750 .num_ports = 10, 3751 .port_base_addr = 0x10, 3752 .age_time_coeff = 15000, 3753 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3754 }, 3755 3756 [MV88E6240] = { 3757 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 3758 .family = MV88E6XXX_FAMILY_6352, 3759 .name = "Marvell 88E6240", 3760 .num_databases = 4096, 3761 .num_ports = 7, 3762 .port_base_addr = 0x10, 3763 .age_time_coeff = 15000, 3764 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3765 }, 3766 3767 [MV88E6320] = { 3768 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 3769 .family = MV88E6XXX_FAMILY_6320, 3770 .name = "Marvell 88E6320", 3771 .num_databases = 4096, 3772 .num_ports = 7, 3773 .port_base_addr = 0x10, 3774 .age_time_coeff = 15000, 3775 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3776 }, 3777 3778 [MV88E6321] = { 3779 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 3780 .family = MV88E6XXX_FAMILY_6320, 3781 .name = "Marvell 88E6321", 3782 .num_databases = 4096, 3783 .num_ports = 7, 3784 .port_base_addr = 0x10, 3785 .age_time_coeff = 15000, 3786 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3787 }, 3788 3789 [MV88E6350] = { 3790 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 3791 .family = MV88E6XXX_FAMILY_6351, 3792 .name = "Marvell 88E6350", 3793 .num_databases = 4096, 3794 .num_ports = 7, 3795 .port_base_addr = 0x10, 3796 .age_time_coeff = 15000, 3797 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3798 }, 3799 3800 [MV88E6351] = { 3801 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 3802 .family = MV88E6XXX_FAMILY_6351, 3803 .name = "Marvell 88E6351", 3804 .num_databases = 4096, 3805 .num_ports = 7, 3806 .port_base_addr = 0x10, 3807 .age_time_coeff = 15000, 3808 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3809 }, 3810 3811 [MV88E6352] = { 3812 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 3813 .family = MV88E6XXX_FAMILY_6352, 3814 .name = "Marvell 88E6352", 3815 .num_databases = 4096, 3816 .num_ports = 7, 3817 .port_base_addr = 0x10, 3818 .age_time_coeff = 15000, 3819 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3820 }, 3821 }; 3822 3823 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3824 { 3825 int i; 3826 3827 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3828 if (mv88e6xxx_table[i].prod_num == prod_num) 3829 return &mv88e6xxx_table[i]; 3830 3831 return NULL; 3832 } 3833 3834 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3835 { 3836 const struct mv88e6xxx_info *info; 3837 unsigned int prod_num, rev; 3838 u16 id; 3839 int err; 3840 3841 mutex_lock(&chip->reg_lock); 3842 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 3843 mutex_unlock(&chip->reg_lock); 3844 if (err) 3845 return err; 3846 3847 prod_num = (id & 0xfff0) >> 4; 3848 rev = id & 0x000f; 3849 3850 info = mv88e6xxx_lookup_info(prod_num); 3851 if (!info) 3852 return -ENODEV; 3853 3854 /* Update the compatible info with the probed one */ 3855 chip->info = info; 3856 3857 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3858 chip->info->prod_num, chip->info->name, rev); 3859 3860 return 0; 3861 } 3862 3863 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3864 { 3865 struct mv88e6xxx_chip *chip; 3866 3867 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3868 if (!chip) 3869 return NULL; 3870 3871 chip->dev = dev; 3872 3873 mutex_init(&chip->reg_lock); 3874 3875 return chip; 3876 } 3877 3878 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = { 3879 .read = mv88e6xxx_read, 3880 .write = mv88e6xxx_write, 3881 }; 3882 3883 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 3884 { 3885 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) { 3886 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops; 3887 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) { 3888 chip->phy_ops = &mv88e6xxx_phy_ppu_ops; 3889 mv88e6xxx_ppu_state_init(chip); 3890 } else { 3891 chip->phy_ops = &mv88e6xxx_phy_ops; 3892 } 3893 } 3894 3895 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3896 struct mii_bus *bus, int sw_addr) 3897 { 3898 /* ADDR[0] pin is unavailable externally and considered zero */ 3899 if (sw_addr & 0x1) 3900 return -EINVAL; 3901 3902 if (sw_addr == 0) 3903 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3904 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 3905 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3906 else 3907 return -EINVAL; 3908 3909 chip->bus = bus; 3910 chip->sw_addr = sw_addr; 3911 3912 return 0; 3913 } 3914 3915 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3916 { 3917 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 3918 3919 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) 3920 return DSA_TAG_PROTO_EDSA; 3921 3922 return DSA_TAG_PROTO_DSA; 3923 } 3924 3925 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3926 struct device *host_dev, int sw_addr, 3927 void **priv) 3928 { 3929 struct mv88e6xxx_chip *chip; 3930 struct mii_bus *bus; 3931 int err; 3932 3933 bus = dsa_host_dev_to_mii_bus(host_dev); 3934 if (!bus) 3935 return NULL; 3936 3937 chip = mv88e6xxx_alloc_chip(dsa_dev); 3938 if (!chip) 3939 return NULL; 3940 3941 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3942 chip->info = &mv88e6xxx_table[MV88E6085]; 3943 3944 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3945 if (err) 3946 goto free; 3947 3948 err = mv88e6xxx_detect(chip); 3949 if (err) 3950 goto free; 3951 3952 mv88e6xxx_phy_init(chip); 3953 3954 err = mv88e6xxx_mdio_register(chip, NULL); 3955 if (err) 3956 goto free; 3957 3958 *priv = chip; 3959 3960 return chip->info->name; 3961 free: 3962 devm_kfree(dsa_dev, chip); 3963 3964 return NULL; 3965 } 3966 3967 static struct dsa_switch_driver mv88e6xxx_switch_driver = { 3968 .probe = mv88e6xxx_drv_probe, 3969 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3970 .setup = mv88e6xxx_setup, 3971 .set_addr = mv88e6xxx_set_addr, 3972 .adjust_link = mv88e6xxx_adjust_link, 3973 .get_strings = mv88e6xxx_get_strings, 3974 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3975 .get_sset_count = mv88e6xxx_get_sset_count, 3976 .set_eee = mv88e6xxx_set_eee, 3977 .get_eee = mv88e6xxx_get_eee, 3978 #ifdef CONFIG_NET_DSA_HWMON 3979 .get_temp = mv88e6xxx_get_temp, 3980 .get_temp_limit = mv88e6xxx_get_temp_limit, 3981 .set_temp_limit = mv88e6xxx_set_temp_limit, 3982 .get_temp_alarm = mv88e6xxx_get_temp_alarm, 3983 #endif 3984 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3985 .get_eeprom = mv88e6xxx_get_eeprom, 3986 .set_eeprom = mv88e6xxx_set_eeprom, 3987 .get_regs_len = mv88e6xxx_get_regs_len, 3988 .get_regs = mv88e6xxx_get_regs, 3989 .set_ageing_time = mv88e6xxx_set_ageing_time, 3990 .port_bridge_join = mv88e6xxx_port_bridge_join, 3991 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3992 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3993 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3994 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3995 .port_vlan_add = mv88e6xxx_port_vlan_add, 3996 .port_vlan_del = mv88e6xxx_port_vlan_del, 3997 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 3998 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 3999 .port_fdb_add = mv88e6xxx_port_fdb_add, 4000 .port_fdb_del = mv88e6xxx_port_fdb_del, 4001 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4002 }; 4003 4004 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, 4005 struct device_node *np) 4006 { 4007 struct device *dev = chip->dev; 4008 struct dsa_switch *ds; 4009 4010 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 4011 if (!ds) 4012 return -ENOMEM; 4013 4014 ds->dev = dev; 4015 ds->priv = chip; 4016 ds->drv = &mv88e6xxx_switch_driver; 4017 4018 dev_set_drvdata(dev, ds); 4019 4020 return dsa_register_switch(ds, np); 4021 } 4022 4023 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4024 { 4025 dsa_unregister_switch(chip->ds); 4026 } 4027 4028 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4029 { 4030 struct device *dev = &mdiodev->dev; 4031 struct device_node *np = dev->of_node; 4032 const struct mv88e6xxx_info *compat_info; 4033 struct mv88e6xxx_chip *chip; 4034 u32 eeprom_len; 4035 int err; 4036 4037 compat_info = of_device_get_match_data(dev); 4038 if (!compat_info) 4039 return -EINVAL; 4040 4041 chip = mv88e6xxx_alloc_chip(dev); 4042 if (!chip) 4043 return -ENOMEM; 4044 4045 chip->info = compat_info; 4046 4047 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4048 if (err) 4049 return err; 4050 4051 err = mv88e6xxx_detect(chip); 4052 if (err) 4053 return err; 4054 4055 mv88e6xxx_phy_init(chip); 4056 4057 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); 4058 if (IS_ERR(chip->reset)) 4059 return PTR_ERR(chip->reset); 4060 4061 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) && 4062 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4063 chip->eeprom_len = eeprom_len; 4064 4065 err = mv88e6xxx_mdio_register(chip, np); 4066 if (err) 4067 return err; 4068 4069 err = mv88e6xxx_register_switch(chip, np); 4070 if (err) { 4071 mv88e6xxx_mdio_unregister(chip); 4072 return err; 4073 } 4074 4075 return 0; 4076 } 4077 4078 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4079 { 4080 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4081 struct mv88e6xxx_chip *chip = ds_to_priv(ds); 4082 4083 mv88e6xxx_unregister_switch(chip); 4084 mv88e6xxx_mdio_unregister(chip); 4085 } 4086 4087 static const struct of_device_id mv88e6xxx_of_match[] = { 4088 { 4089 .compatible = "marvell,mv88e6085", 4090 .data = &mv88e6xxx_table[MV88E6085], 4091 }, 4092 { /* sentinel */ }, 4093 }; 4094 4095 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4096 4097 static struct mdio_driver mv88e6xxx_driver = { 4098 .probe = mv88e6xxx_probe, 4099 .remove = mv88e6xxx_remove, 4100 .mdiodrv.driver = { 4101 .name = "mv88e6085", 4102 .of_match_table = mv88e6xxx_of_match, 4103 }, 4104 }; 4105 4106 static int __init mv88e6xxx_init(void) 4107 { 4108 register_switch_driver(&mv88e6xxx_switch_driver); 4109 return mdio_driver_register(&mv88e6xxx_driver); 4110 } 4111 module_init(mv88e6xxx_init); 4112 4113 static void __exit mv88e6xxx_cleanup(void) 4114 { 4115 mdio_driver_unregister(&mv88e6xxx_driver); 4116 unregister_switch_driver(&mv88e6xxx_switch_driver); 4117 } 4118 module_exit(mv88e6xxx_cleanup); 4119 4120 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4121 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4122 MODULE_LICENSE("GPL"); 4123