12dcb8e87SMartin Jerabek /* SPDX-License-Identifier: GPL-2.0-or-later */ 22dcb8e87SMartin Jerabek /******************************************************************************* 32dcb8e87SMartin Jerabek * 42dcb8e87SMartin Jerabek * CTU CAN FD IP Core 52dcb8e87SMartin Jerabek * 62dcb8e87SMartin Jerabek * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU 7*9e7c9b8eSPavel Pisa * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded 82dcb8e87SMartin Jerabek * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU 9*9e7c9b8eSPavel Pisa * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded 102dcb8e87SMartin Jerabek * 112dcb8e87SMartin Jerabek * Project advisors: 122dcb8e87SMartin Jerabek * Jiri Novak <jnovak@fel.cvut.cz> 132dcb8e87SMartin Jerabek * Pavel Pisa <pisa@cmp.felk.cvut.cz> 142dcb8e87SMartin Jerabek * 152dcb8e87SMartin Jerabek * Department of Measurement (http://meas.fel.cvut.cz/) 162dcb8e87SMartin Jerabek * Faculty of Electrical Engineering (http://www.fel.cvut.cz) 172dcb8e87SMartin Jerabek * Czech Technical University (http://www.cvut.cz/) 182dcb8e87SMartin Jerabek ******************************************************************************/ 192dcb8e87SMartin Jerabek 202dcb8e87SMartin Jerabek /* This file is autogenerated, DO NOT EDIT! */ 212dcb8e87SMartin Jerabek 222dcb8e87SMartin Jerabek #ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__ 232dcb8e87SMartin Jerabek #define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__ 242dcb8e87SMartin Jerabek 252dcb8e87SMartin Jerabek #include <linux/bits.h> 262dcb8e87SMartin Jerabek 272dcb8e87SMartin Jerabek /* CAN_Registers memory map */ 282dcb8e87SMartin Jerabek enum ctu_can_fd_can_registers { 292dcb8e87SMartin Jerabek CTUCANFD_DEVICE_ID = 0x0, 302dcb8e87SMartin Jerabek CTUCANFD_VERSION = 0x2, 312dcb8e87SMartin Jerabek CTUCANFD_MODE = 0x4, 322dcb8e87SMartin Jerabek CTUCANFD_SETTINGS = 0x6, 332dcb8e87SMartin Jerabek CTUCANFD_STATUS = 0x8, 342dcb8e87SMartin Jerabek CTUCANFD_COMMAND = 0xc, 352dcb8e87SMartin Jerabek CTUCANFD_INT_STAT = 0x10, 362dcb8e87SMartin Jerabek CTUCANFD_INT_ENA_SET = 0x14, 372dcb8e87SMartin Jerabek CTUCANFD_INT_ENA_CLR = 0x18, 382dcb8e87SMartin Jerabek CTUCANFD_INT_MASK_SET = 0x1c, 392dcb8e87SMartin Jerabek CTUCANFD_INT_MASK_CLR = 0x20, 402dcb8e87SMartin Jerabek CTUCANFD_BTR = 0x24, 412dcb8e87SMartin Jerabek CTUCANFD_BTR_FD = 0x28, 422dcb8e87SMartin Jerabek CTUCANFD_EWL = 0x2c, 432dcb8e87SMartin Jerabek CTUCANFD_ERP = 0x2d, 442dcb8e87SMartin Jerabek CTUCANFD_FAULT_STATE = 0x2e, 452dcb8e87SMartin Jerabek CTUCANFD_REC = 0x30, 462dcb8e87SMartin Jerabek CTUCANFD_TEC = 0x32, 472dcb8e87SMartin Jerabek CTUCANFD_ERR_NORM = 0x34, 482dcb8e87SMartin Jerabek CTUCANFD_ERR_FD = 0x36, 492dcb8e87SMartin Jerabek CTUCANFD_CTR_PRES = 0x38, 502dcb8e87SMartin Jerabek CTUCANFD_FILTER_A_MASK = 0x3c, 512dcb8e87SMartin Jerabek CTUCANFD_FILTER_A_VAL = 0x40, 522dcb8e87SMartin Jerabek CTUCANFD_FILTER_B_MASK = 0x44, 532dcb8e87SMartin Jerabek CTUCANFD_FILTER_B_VAL = 0x48, 542dcb8e87SMartin Jerabek CTUCANFD_FILTER_C_MASK = 0x4c, 552dcb8e87SMartin Jerabek CTUCANFD_FILTER_C_VAL = 0x50, 562dcb8e87SMartin Jerabek CTUCANFD_FILTER_RAN_LOW = 0x54, 572dcb8e87SMartin Jerabek CTUCANFD_FILTER_RAN_HIGH = 0x58, 582dcb8e87SMartin Jerabek CTUCANFD_FILTER_CONTROL = 0x5c, 592dcb8e87SMartin Jerabek CTUCANFD_FILTER_STATUS = 0x5e, 602dcb8e87SMartin Jerabek CTUCANFD_RX_MEM_INFO = 0x60, 612dcb8e87SMartin Jerabek CTUCANFD_RX_POINTERS = 0x64, 622dcb8e87SMartin Jerabek CTUCANFD_RX_STATUS = 0x68, 632dcb8e87SMartin Jerabek CTUCANFD_RX_SETTINGS = 0x6a, 642dcb8e87SMartin Jerabek CTUCANFD_RX_DATA = 0x6c, 652dcb8e87SMartin Jerabek CTUCANFD_TX_STATUS = 0x70, 662dcb8e87SMartin Jerabek CTUCANFD_TX_COMMAND = 0x74, 67*9e7c9b8eSPavel Pisa CTUCANFD_TXTB_INFO = 0x76, 682dcb8e87SMartin Jerabek CTUCANFD_TX_PRIORITY = 0x78, 692dcb8e87SMartin Jerabek CTUCANFD_ERR_CAPT = 0x7c, 70*9e7c9b8eSPavel Pisa CTUCANFD_RETR_CTR = 0x7d, 712dcb8e87SMartin Jerabek CTUCANFD_ALC = 0x7e, 72*9e7c9b8eSPavel Pisa CTUCANFD_TS_INFO = 0x7f, 732dcb8e87SMartin Jerabek CTUCANFD_TRV_DELAY = 0x80, 742dcb8e87SMartin Jerabek CTUCANFD_SSP_CFG = 0x82, 752dcb8e87SMartin Jerabek CTUCANFD_RX_FR_CTR = 0x84, 762dcb8e87SMartin Jerabek CTUCANFD_TX_FR_CTR = 0x88, 772dcb8e87SMartin Jerabek CTUCANFD_DEBUG_REGISTER = 0x8c, 782dcb8e87SMartin Jerabek CTUCANFD_YOLO_REG = 0x90, 792dcb8e87SMartin Jerabek CTUCANFD_TIMESTAMP_LOW = 0x94, 802dcb8e87SMartin Jerabek CTUCANFD_TIMESTAMP_HIGH = 0x98, 812dcb8e87SMartin Jerabek CTUCANFD_TXTB1_DATA_1 = 0x100, 822dcb8e87SMartin Jerabek CTUCANFD_TXTB1_DATA_2 = 0x104, 832dcb8e87SMartin Jerabek CTUCANFD_TXTB1_DATA_20 = 0x14c, 842dcb8e87SMartin Jerabek CTUCANFD_TXTB2_DATA_1 = 0x200, 852dcb8e87SMartin Jerabek CTUCANFD_TXTB2_DATA_2 = 0x204, 862dcb8e87SMartin Jerabek CTUCANFD_TXTB2_DATA_20 = 0x24c, 872dcb8e87SMartin Jerabek CTUCANFD_TXTB3_DATA_1 = 0x300, 882dcb8e87SMartin Jerabek CTUCANFD_TXTB3_DATA_2 = 0x304, 892dcb8e87SMartin Jerabek CTUCANFD_TXTB3_DATA_20 = 0x34c, 902dcb8e87SMartin Jerabek CTUCANFD_TXTB4_DATA_1 = 0x400, 912dcb8e87SMartin Jerabek CTUCANFD_TXTB4_DATA_2 = 0x404, 922dcb8e87SMartin Jerabek CTUCANFD_TXTB4_DATA_20 = 0x44c, 932dcb8e87SMartin Jerabek }; 942dcb8e87SMartin Jerabek 952dcb8e87SMartin Jerabek /* Control_registers memory region */ 962dcb8e87SMartin Jerabek 972dcb8e87SMartin Jerabek /* DEVICE_ID VERSION registers */ 982dcb8e87SMartin Jerabek #define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0) 992dcb8e87SMartin Jerabek #define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16) 1002dcb8e87SMartin Jerabek #define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24) 1012dcb8e87SMartin Jerabek 1022dcb8e87SMartin Jerabek /* MODE SETTINGS registers */ 1032dcb8e87SMartin Jerabek #define REG_MODE_RST BIT(0) 1042dcb8e87SMartin Jerabek #define REG_MODE_BMM BIT(1) 1052dcb8e87SMartin Jerabek #define REG_MODE_STM BIT(2) 1062dcb8e87SMartin Jerabek #define REG_MODE_AFM BIT(3) 1072dcb8e87SMartin Jerabek #define REG_MODE_FDE BIT(4) 108*9e7c9b8eSPavel Pisa #define REG_MODE_TTTM BIT(5) 109*9e7c9b8eSPavel Pisa #define REG_MODE_ROM BIT(6) 1102dcb8e87SMartin Jerabek #define REG_MODE_ACF BIT(7) 1112dcb8e87SMartin Jerabek #define REG_MODE_TSTM BIT(8) 112*9e7c9b8eSPavel Pisa #define REG_MODE_RXBAM BIT(9) 113*9e7c9b8eSPavel Pisa #define REG_MODE_SAM BIT(11) 1142dcb8e87SMartin Jerabek #define REG_MODE_RTRLE BIT(16) 1152dcb8e87SMartin Jerabek #define REG_MODE_RTRTH GENMASK(20, 17) 1162dcb8e87SMartin Jerabek #define REG_MODE_ILBP BIT(21) 1172dcb8e87SMartin Jerabek #define REG_MODE_ENA BIT(22) 1182dcb8e87SMartin Jerabek #define REG_MODE_NISOFD BIT(23) 1192dcb8e87SMartin Jerabek #define REG_MODE_PEX BIT(24) 1202dcb8e87SMartin Jerabek #define REG_MODE_TBFBO BIT(25) 1212dcb8e87SMartin Jerabek #define REG_MODE_FDRF BIT(26) 1222dcb8e87SMartin Jerabek 1232dcb8e87SMartin Jerabek /* STATUS registers */ 1242dcb8e87SMartin Jerabek #define REG_STATUS_RXNE BIT(0) 1252dcb8e87SMartin Jerabek #define REG_STATUS_DOR BIT(1) 1262dcb8e87SMartin Jerabek #define REG_STATUS_TXNF BIT(2) 1272dcb8e87SMartin Jerabek #define REG_STATUS_EFT BIT(3) 1282dcb8e87SMartin Jerabek #define REG_STATUS_RXS BIT(4) 1292dcb8e87SMartin Jerabek #define REG_STATUS_TXS BIT(5) 1302dcb8e87SMartin Jerabek #define REG_STATUS_EWL BIT(6) 1312dcb8e87SMartin Jerabek #define REG_STATUS_IDLE BIT(7) 1322dcb8e87SMartin Jerabek #define REG_STATUS_PEXS BIT(8) 133*9e7c9b8eSPavel Pisa #define REG_STATUS_STCNT BIT(16) 1342dcb8e87SMartin Jerabek 1352dcb8e87SMartin Jerabek /* COMMAND registers */ 136*9e7c9b8eSPavel Pisa #define REG_COMMAND_RXRPMV BIT(1) 1372dcb8e87SMartin Jerabek #define REG_COMMAND_RRB BIT(2) 1382dcb8e87SMartin Jerabek #define REG_COMMAND_CDO BIT(3) 1392dcb8e87SMartin Jerabek #define REG_COMMAND_ERCRST BIT(4) 1402dcb8e87SMartin Jerabek #define REG_COMMAND_RXFCRST BIT(5) 1412dcb8e87SMartin Jerabek #define REG_COMMAND_TXFCRST BIT(6) 1422dcb8e87SMartin Jerabek #define REG_COMMAND_CPEXS BIT(7) 1432dcb8e87SMartin Jerabek 1442dcb8e87SMartin Jerabek /* INT_STAT registers */ 1452dcb8e87SMartin Jerabek #define REG_INT_STAT_RXI BIT(0) 1462dcb8e87SMartin Jerabek #define REG_INT_STAT_TXI BIT(1) 1472dcb8e87SMartin Jerabek #define REG_INT_STAT_EWLI BIT(2) 1482dcb8e87SMartin Jerabek #define REG_INT_STAT_DOI BIT(3) 1492dcb8e87SMartin Jerabek #define REG_INT_STAT_FCSI BIT(4) 1502dcb8e87SMartin Jerabek #define REG_INT_STAT_ALI BIT(5) 1512dcb8e87SMartin Jerabek #define REG_INT_STAT_BEI BIT(6) 1522dcb8e87SMartin Jerabek #define REG_INT_STAT_OFI BIT(7) 1532dcb8e87SMartin Jerabek #define REG_INT_STAT_RXFI BIT(8) 1542dcb8e87SMartin Jerabek #define REG_INT_STAT_BSI BIT(9) 1552dcb8e87SMartin Jerabek #define REG_INT_STAT_RBNEI BIT(10) 1562dcb8e87SMartin Jerabek #define REG_INT_STAT_TXBHCI BIT(11) 1572dcb8e87SMartin Jerabek 1582dcb8e87SMartin Jerabek /* INT_ENA_SET registers */ 1592dcb8e87SMartin Jerabek #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0) 1602dcb8e87SMartin Jerabek 1612dcb8e87SMartin Jerabek /* INT_ENA_CLR registers */ 1622dcb8e87SMartin Jerabek #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0) 1632dcb8e87SMartin Jerabek 1642dcb8e87SMartin Jerabek /* INT_MASK_SET registers */ 1652dcb8e87SMartin Jerabek #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0) 1662dcb8e87SMartin Jerabek 1672dcb8e87SMartin Jerabek /* INT_MASK_CLR registers */ 1682dcb8e87SMartin Jerabek #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0) 1692dcb8e87SMartin Jerabek 1702dcb8e87SMartin Jerabek /* BTR registers */ 1712dcb8e87SMartin Jerabek #define REG_BTR_PROP GENMASK(6, 0) 1722dcb8e87SMartin Jerabek #define REG_BTR_PH1 GENMASK(12, 7) 1732dcb8e87SMartin Jerabek #define REG_BTR_PH2 GENMASK(18, 13) 1742dcb8e87SMartin Jerabek #define REG_BTR_BRP GENMASK(26, 19) 1752dcb8e87SMartin Jerabek #define REG_BTR_SJW GENMASK(31, 27) 1762dcb8e87SMartin Jerabek 1772dcb8e87SMartin Jerabek /* BTR_FD registers */ 1782dcb8e87SMartin Jerabek #define REG_BTR_FD_PROP_FD GENMASK(5, 0) 1792dcb8e87SMartin Jerabek #define REG_BTR_FD_PH1_FD GENMASK(11, 7) 1802dcb8e87SMartin Jerabek #define REG_BTR_FD_PH2_FD GENMASK(17, 13) 1812dcb8e87SMartin Jerabek #define REG_BTR_FD_BRP_FD GENMASK(26, 19) 1822dcb8e87SMartin Jerabek #define REG_BTR_FD_SJW_FD GENMASK(31, 27) 1832dcb8e87SMartin Jerabek 1842dcb8e87SMartin Jerabek /* EWL ERP FAULT_STATE registers */ 1852dcb8e87SMartin Jerabek #define REG_EWL_EW_LIMIT GENMASK(7, 0) 1862dcb8e87SMartin Jerabek #define REG_EWL_ERP_LIMIT GENMASK(15, 8) 1872dcb8e87SMartin Jerabek #define REG_EWL_ERA BIT(16) 1882dcb8e87SMartin Jerabek #define REG_EWL_ERP BIT(17) 1892dcb8e87SMartin Jerabek #define REG_EWL_BOF BIT(18) 1902dcb8e87SMartin Jerabek 1912dcb8e87SMartin Jerabek /* REC TEC registers */ 1922dcb8e87SMartin Jerabek #define REG_REC_REC_VAL GENMASK(8, 0) 1932dcb8e87SMartin Jerabek #define REG_REC_TEC_VAL GENMASK(24, 16) 1942dcb8e87SMartin Jerabek 1952dcb8e87SMartin Jerabek /* ERR_NORM ERR_FD registers */ 1962dcb8e87SMartin Jerabek #define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0) 1972dcb8e87SMartin Jerabek #define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16) 1982dcb8e87SMartin Jerabek 1992dcb8e87SMartin Jerabek /* CTR_PRES registers */ 2002dcb8e87SMartin Jerabek #define REG_CTR_PRES_CTPV GENMASK(8, 0) 2012dcb8e87SMartin Jerabek #define REG_CTR_PRES_PTX BIT(9) 2022dcb8e87SMartin Jerabek #define REG_CTR_PRES_PRX BIT(10) 2032dcb8e87SMartin Jerabek #define REG_CTR_PRES_ENORM BIT(11) 2042dcb8e87SMartin Jerabek #define REG_CTR_PRES_EFD BIT(12) 2052dcb8e87SMartin Jerabek 2062dcb8e87SMartin Jerabek /* FILTER_A_MASK registers */ 2072dcb8e87SMartin Jerabek #define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0) 2082dcb8e87SMartin Jerabek 2092dcb8e87SMartin Jerabek /* FILTER_A_VAL registers */ 2102dcb8e87SMartin Jerabek #define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0) 2112dcb8e87SMartin Jerabek 2122dcb8e87SMartin Jerabek /* FILTER_B_MASK registers */ 2132dcb8e87SMartin Jerabek #define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0) 2142dcb8e87SMartin Jerabek 2152dcb8e87SMartin Jerabek /* FILTER_B_VAL registers */ 2162dcb8e87SMartin Jerabek #define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0) 2172dcb8e87SMartin Jerabek 2182dcb8e87SMartin Jerabek /* FILTER_C_MASK registers */ 2192dcb8e87SMartin Jerabek #define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0) 2202dcb8e87SMartin Jerabek 2212dcb8e87SMartin Jerabek /* FILTER_C_VAL registers */ 2222dcb8e87SMartin Jerabek #define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0) 2232dcb8e87SMartin Jerabek 2242dcb8e87SMartin Jerabek /* FILTER_RAN_LOW registers */ 2252dcb8e87SMartin Jerabek #define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0) 2262dcb8e87SMartin Jerabek 2272dcb8e87SMartin Jerabek /* FILTER_RAN_HIGH registers */ 2282dcb8e87SMartin Jerabek #define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0) 2292dcb8e87SMartin Jerabek 2302dcb8e87SMartin Jerabek /* FILTER_CONTROL FILTER_STATUS registers */ 2312dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FANB BIT(0) 2322dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FANE BIT(1) 2332dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FAFB BIT(2) 2342dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FAFE BIT(3) 2352dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FBNB BIT(4) 2362dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FBNE BIT(5) 2372dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FBFB BIT(6) 2382dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FBFE BIT(7) 2392dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FCNB BIT(8) 2402dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FCNE BIT(9) 2412dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FCFB BIT(10) 2422dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FCFE BIT(11) 2432dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FRNB BIT(12) 2442dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FRNE BIT(13) 2452dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FRFB BIT(14) 2462dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_FRFE BIT(15) 2472dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_SFA BIT(16) 2482dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_SFB BIT(17) 2492dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_SFC BIT(18) 2502dcb8e87SMartin Jerabek #define REG_FILTER_CONTROL_SFR BIT(19) 2512dcb8e87SMartin Jerabek 2522dcb8e87SMartin Jerabek /* RX_MEM_INFO registers */ 2532dcb8e87SMartin Jerabek #define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0) 2542dcb8e87SMartin Jerabek #define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16) 2552dcb8e87SMartin Jerabek 2562dcb8e87SMartin Jerabek /* RX_POINTERS registers */ 2572dcb8e87SMartin Jerabek #define REG_RX_POINTERS_RX_WPP GENMASK(11, 0) 2582dcb8e87SMartin Jerabek #define REG_RX_POINTERS_RX_RPP GENMASK(27, 16) 2592dcb8e87SMartin Jerabek 2602dcb8e87SMartin Jerabek /* RX_STATUS RX_SETTINGS registers */ 2612dcb8e87SMartin Jerabek #define REG_RX_STATUS_RXE BIT(0) 2622dcb8e87SMartin Jerabek #define REG_RX_STATUS_RXF BIT(1) 2632dcb8e87SMartin Jerabek #define REG_RX_STATUS_RXMOF BIT(2) 2642dcb8e87SMartin Jerabek #define REG_RX_STATUS_RXFRC GENMASK(14, 4) 2652dcb8e87SMartin Jerabek #define REG_RX_STATUS_RTSOP BIT(16) 2662dcb8e87SMartin Jerabek 2672dcb8e87SMartin Jerabek /* RX_DATA registers */ 2682dcb8e87SMartin Jerabek #define REG_RX_DATA_RX_DATA GENMASK(31, 0) 2692dcb8e87SMartin Jerabek 2702dcb8e87SMartin Jerabek /* TX_STATUS registers */ 2712dcb8e87SMartin Jerabek #define REG_TX_STATUS_TX1S GENMASK(3, 0) 2722dcb8e87SMartin Jerabek #define REG_TX_STATUS_TX2S GENMASK(7, 4) 2732dcb8e87SMartin Jerabek #define REG_TX_STATUS_TX3S GENMASK(11, 8) 2742dcb8e87SMartin Jerabek #define REG_TX_STATUS_TX4S GENMASK(15, 12) 275*9e7c9b8eSPavel Pisa #define REG_TX_STATUS_TX5S GENMASK(19, 16) 276*9e7c9b8eSPavel Pisa #define REG_TX_STATUS_TX6S GENMASK(23, 20) 277*9e7c9b8eSPavel Pisa #define REG_TX_STATUS_TX7S GENMASK(27, 24) 278*9e7c9b8eSPavel Pisa #define REG_TX_STATUS_TX8S GENMASK(31, 28) 2792dcb8e87SMartin Jerabek 280*9e7c9b8eSPavel Pisa /* TX_COMMAND TXTB_INFO registers */ 2812dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXCE BIT(0) 2822dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXCR BIT(1) 2832dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXCA BIT(2) 2842dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXB1 BIT(8) 2852dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXB2 BIT(9) 2862dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXB3 BIT(10) 2872dcb8e87SMartin Jerabek #define REG_TX_COMMAND_TXB4 BIT(11) 288*9e7c9b8eSPavel Pisa #define REG_TX_COMMAND_TXB5 BIT(12) 289*9e7c9b8eSPavel Pisa #define REG_TX_COMMAND_TXB6 BIT(13) 290*9e7c9b8eSPavel Pisa #define REG_TX_COMMAND_TXB7 BIT(14) 291*9e7c9b8eSPavel Pisa #define REG_TX_COMMAND_TXB8 BIT(15) 292*9e7c9b8eSPavel Pisa #define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16) 2932dcb8e87SMartin Jerabek 2942dcb8e87SMartin Jerabek /* TX_PRIORITY registers */ 2952dcb8e87SMartin Jerabek #define REG_TX_PRIORITY_TXT1P GENMASK(2, 0) 2962dcb8e87SMartin Jerabek #define REG_TX_PRIORITY_TXT2P GENMASK(6, 4) 2972dcb8e87SMartin Jerabek #define REG_TX_PRIORITY_TXT3P GENMASK(10, 8) 2982dcb8e87SMartin Jerabek #define REG_TX_PRIORITY_TXT4P GENMASK(14, 12) 299*9e7c9b8eSPavel Pisa #define REG_TX_PRIORITY_TXT5P GENMASK(18, 16) 300*9e7c9b8eSPavel Pisa #define REG_TX_PRIORITY_TXT6P GENMASK(22, 20) 301*9e7c9b8eSPavel Pisa #define REG_TX_PRIORITY_TXT7P GENMASK(26, 24) 302*9e7c9b8eSPavel Pisa #define REG_TX_PRIORITY_TXT8P GENMASK(30, 28) 3032dcb8e87SMartin Jerabek 304*9e7c9b8eSPavel Pisa /* ERR_CAPT RETR_CTR ALC TS_INFO registers */ 3052dcb8e87SMartin Jerabek #define REG_ERR_CAPT_ERR_POS GENMASK(4, 0) 3062dcb8e87SMartin Jerabek #define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5) 307*9e7c9b8eSPavel Pisa #define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8) 3082dcb8e87SMartin Jerabek #define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16) 3092dcb8e87SMartin Jerabek #define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21) 310*9e7c9b8eSPavel Pisa #define REG_ERR_CAPT_TS_BITS GENMASK(29, 24) 3112dcb8e87SMartin Jerabek 3122dcb8e87SMartin Jerabek /* TRV_DELAY SSP_CFG registers */ 3132dcb8e87SMartin Jerabek #define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0) 3142dcb8e87SMartin Jerabek #define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16) 3152dcb8e87SMartin Jerabek #define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24) 3162dcb8e87SMartin Jerabek 3172dcb8e87SMartin Jerabek /* RX_FR_CTR registers */ 3182dcb8e87SMartin Jerabek #define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0) 3192dcb8e87SMartin Jerabek 3202dcb8e87SMartin Jerabek /* TX_FR_CTR registers */ 3212dcb8e87SMartin Jerabek #define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0) 3222dcb8e87SMartin Jerabek 3232dcb8e87SMartin Jerabek /* DEBUG_REGISTER registers */ 3242dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0) 3252dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3) 3262dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_ARB BIT(6) 3272dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_CON BIT(7) 3282dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_DAT BIT(8) 3292dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_STC BIT(9) 3302dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_CRC BIT(10) 3312dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_CRCD BIT(11) 3322dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_ACK BIT(12) 3332dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_ACKD BIT(13) 3342dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_EOF BIT(14) 3352dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_INT BIT(15) 3362dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_SUSP BIT(16) 3372dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_OVR BIT(17) 3382dcb8e87SMartin Jerabek #define REG_DEBUG_REGISTER_PC_SOF BIT(18) 3392dcb8e87SMartin Jerabek 3402dcb8e87SMartin Jerabek /* YOLO_REG registers */ 3412dcb8e87SMartin Jerabek #define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0) 3422dcb8e87SMartin Jerabek 3432dcb8e87SMartin Jerabek /* TIMESTAMP_LOW registers */ 3442dcb8e87SMartin Jerabek #define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0) 3452dcb8e87SMartin Jerabek 3462dcb8e87SMartin Jerabek /* TIMESTAMP_HIGH registers */ 3472dcb8e87SMartin Jerabek #define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0) 3482dcb8e87SMartin Jerabek 3492dcb8e87SMartin Jerabek #endif 350