12dcb8e87SMartin Jerabekconfig CAN_CTUCANFD 294737ef5SGeert Uytterhoeven tristate "CTU CAN-FD IP core" if COMPILE_TEST 32dcb8e87SMartin Jerabek help 42dcb8e87SMartin Jerabek This driver adds support for the CTU CAN FD open-source IP core. 52dcb8e87SMartin Jerabek More documentation and core sources at project page 62dcb8e87SMartin Jerabek (https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core). 72dcb8e87SMartin Jerabek The core integration to Xilinx Zynq system as platform driver 82dcb8e87SMartin Jerabek is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top). 92dcb8e87SMartin Jerabek Implementation on Intel FPGA-based PCI Express board is available 102dcb8e87SMartin Jerabek from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and 112dcb8e87SMartin Jerabek on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd). 122dcb8e87SMartin Jerabek Guidepost CTU FEE CAN bus projects page https://canbus.pages.fel.cvut.cz/ . 13792a5b67SPavel Pisa 14792a5b67SPavel Pisaconfig CAN_CTUCANFD_PCI 15792a5b67SPavel Pisa tristate "CTU CAN-FD IP core PCI/PCIe driver" 16792a5b67SPavel Pisa depends on PCI 1794737ef5SGeert Uytterhoeven select CAN_CTUCANFD 18792a5b67SPavel Pisa help 19792a5b67SPavel Pisa This driver adds PCI/PCIe support for CTU CAN-FD IP core. 20792a5b67SPavel Pisa The project providing FPGA design for Intel EP4CGX15 based DB4CGX15 21792a5b67SPavel Pisa PCIe board with PiKRON.com designed transceiver riser shield is available 22792a5b67SPavel Pisa at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd . 23e8f0c23aSPavel Pisa 24e8f0c23aSPavel Pisaconfig CAN_CTUCANFD_PLATFORM 25e8f0c23aSPavel Pisa tristate "CTU CAN-FD IP core platform (FPGA, SoC) driver" 26*005c5427SJean Delvare depends on HAS_IOMEM && OF 2794737ef5SGeert Uytterhoeven select CAN_CTUCANFD 28e8f0c23aSPavel Pisa help 29e8f0c23aSPavel Pisa The core has been tested together with OpenCores SJA1000 30e8f0c23aSPavel Pisa modified to be CAN FD frames tolerant on MicroZed Zynq based 31e8f0c23aSPavel Pisa MZ_APO education kits designed by Petr Porazil from PiKRON.com 32e8f0c23aSPavel Pisa company. FPGA design https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top. 33e8f0c23aSPavel Pisa The kit description at the Computer Architectures course pages 34e8f0c23aSPavel Pisa https://cw.fel.cvut.cz/wiki/courses/b35apo/documentation/mz_apo/start . 35