xref: /openbmc/linux/drivers/mtd/nand/raw/denali_dt.c (revision d8e8fd0ebf8b1b8d26a160c2363479a88c1f72c2)
1f1bf52e8SMasahiro Yamada // SPDX-License-Identifier: GPL-2.0
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon  * NAND Flash Controller Device Driver for DT
493db446aSBoris Brezillon  *
593db446aSBoris Brezillon  * Copyright © 2011, Picochip.
693db446aSBoris Brezillon  */
793db446aSBoris Brezillon 
893db446aSBoris Brezillon #include <linux/clk.h>
993db446aSBoris Brezillon #include <linux/err.h>
1093db446aSBoris Brezillon #include <linux/io.h>
1193db446aSBoris Brezillon #include <linux/ioport.h>
1293db446aSBoris Brezillon #include <linux/kernel.h>
1393db446aSBoris Brezillon #include <linux/module.h>
1493db446aSBoris Brezillon #include <linux/of.h>
1593db446aSBoris Brezillon #include <linux/of_device.h>
1693db446aSBoris Brezillon #include <linux/platform_device.h>
1793db446aSBoris Brezillon 
1893db446aSBoris Brezillon #include "denali.h"
1993db446aSBoris Brezillon 
2093db446aSBoris Brezillon struct denali_dt {
21*d8e8fd0eSMasahiro Yamada 	struct denali_controller controller;
226f1fe97bSMasahiro Yamada 	struct clk *clk;	/* core clock */
236f1fe97bSMasahiro Yamada 	struct clk *clk_x;	/* bus interface clock */
246f1fe97bSMasahiro Yamada 	struct clk *clk_ecc;	/* ECC circuit clock */
2593db446aSBoris Brezillon };
2693db446aSBoris Brezillon 
2793db446aSBoris Brezillon struct denali_dt_data {
2893db446aSBoris Brezillon 	unsigned int revision;
2993db446aSBoris Brezillon 	unsigned int caps;
3093db446aSBoris Brezillon 	const struct nand_ecc_caps *ecc_caps;
3193db446aSBoris Brezillon };
3293db446aSBoris Brezillon 
3393db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
3493db446aSBoris Brezillon 		     512, 8, 15);
3593db446aSBoris Brezillon static const struct denali_dt_data denali_socfpga_data = {
3693db446aSBoris Brezillon 	.caps = DENALI_CAP_HW_ECC_FIXUP,
3793db446aSBoris Brezillon 	.ecc_caps = &denali_socfpga_ecc_caps,
3893db446aSBoris Brezillon };
3993db446aSBoris Brezillon 
4093db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
4193db446aSBoris Brezillon 		     1024, 8, 16, 24);
4293db446aSBoris Brezillon static const struct denali_dt_data denali_uniphier_v5a_data = {
4393db446aSBoris Brezillon 	.caps = DENALI_CAP_HW_ECC_FIXUP |
4493db446aSBoris Brezillon 		DENALI_CAP_DMA_64BIT,
4593db446aSBoris Brezillon 	.ecc_caps = &denali_uniphier_v5a_ecc_caps,
4693db446aSBoris Brezillon };
4793db446aSBoris Brezillon 
4893db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
4993db446aSBoris Brezillon 		     1024, 8, 16);
5093db446aSBoris Brezillon static const struct denali_dt_data denali_uniphier_v5b_data = {
5193db446aSBoris Brezillon 	.revision = 0x0501,
5293db446aSBoris Brezillon 	.caps = DENALI_CAP_HW_ECC_FIXUP |
5393db446aSBoris Brezillon 		DENALI_CAP_DMA_64BIT,
5493db446aSBoris Brezillon 	.ecc_caps = &denali_uniphier_v5b_ecc_caps,
5593db446aSBoris Brezillon };
5693db446aSBoris Brezillon 
5793db446aSBoris Brezillon static const struct of_device_id denali_nand_dt_ids[] = {
5893db446aSBoris Brezillon 	{
5993db446aSBoris Brezillon 		.compatible = "altr,socfpga-denali-nand",
6093db446aSBoris Brezillon 		.data = &denali_socfpga_data,
6193db446aSBoris Brezillon 	},
6293db446aSBoris Brezillon 	{
6393db446aSBoris Brezillon 		.compatible = "socionext,uniphier-denali-nand-v5a",
6493db446aSBoris Brezillon 		.data = &denali_uniphier_v5a_data,
6593db446aSBoris Brezillon 	},
6693db446aSBoris Brezillon 	{
6793db446aSBoris Brezillon 		.compatible = "socionext,uniphier-denali-nand-v5b",
6893db446aSBoris Brezillon 		.data = &denali_uniphier_v5b_data,
6993db446aSBoris Brezillon 	},
7093db446aSBoris Brezillon 	{ /* sentinel */ }
7193db446aSBoris Brezillon };
7293db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
7393db446aSBoris Brezillon 
74*d8e8fd0eSMasahiro Yamada static int denali_dt_chip_init(struct denali_controller *denali,
75*d8e8fd0eSMasahiro Yamada 			       struct device_node *chip_np)
76*d8e8fd0eSMasahiro Yamada {
77*d8e8fd0eSMasahiro Yamada 	struct denali_chip *dchip;
78*d8e8fd0eSMasahiro Yamada 	u32 bank;
79*d8e8fd0eSMasahiro Yamada 	int nsels, i, ret;
80*d8e8fd0eSMasahiro Yamada 
81*d8e8fd0eSMasahiro Yamada 	nsels = of_property_count_u32_elems(chip_np, "reg");
82*d8e8fd0eSMasahiro Yamada 	if (nsels < 0)
83*d8e8fd0eSMasahiro Yamada 		return nsels;
84*d8e8fd0eSMasahiro Yamada 
85*d8e8fd0eSMasahiro Yamada 	dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
86*d8e8fd0eSMasahiro Yamada 			     GFP_KERNEL);
87*d8e8fd0eSMasahiro Yamada 	if (!dchip)
88*d8e8fd0eSMasahiro Yamada 		return -ENOMEM;
89*d8e8fd0eSMasahiro Yamada 
90*d8e8fd0eSMasahiro Yamada 	dchip->nsels = nsels;
91*d8e8fd0eSMasahiro Yamada 
92*d8e8fd0eSMasahiro Yamada 	for (i = 0; i < nsels; i++) {
93*d8e8fd0eSMasahiro Yamada 		ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
94*d8e8fd0eSMasahiro Yamada 		if (ret)
95*d8e8fd0eSMasahiro Yamada 			return ret;
96*d8e8fd0eSMasahiro Yamada 
97*d8e8fd0eSMasahiro Yamada 		dchip->sels[i].bank = bank;
98*d8e8fd0eSMasahiro Yamada 
99*d8e8fd0eSMasahiro Yamada 		nand_set_flash_node(&dchip->chip, chip_np);
100*d8e8fd0eSMasahiro Yamada 	}
101*d8e8fd0eSMasahiro Yamada 
102*d8e8fd0eSMasahiro Yamada 	return denali_chip_init(denali, dchip);
103*d8e8fd0eSMasahiro Yamada }
104*d8e8fd0eSMasahiro Yamada 
105*d8e8fd0eSMasahiro Yamada /* Backward compatibility for old platforms */
106*d8e8fd0eSMasahiro Yamada static int denali_dt_legacy_chip_init(struct denali_controller *denali)
107*d8e8fd0eSMasahiro Yamada {
108*d8e8fd0eSMasahiro Yamada 	struct denali_chip *dchip;
109*d8e8fd0eSMasahiro Yamada 	int nsels, i;
110*d8e8fd0eSMasahiro Yamada 
111*d8e8fd0eSMasahiro Yamada 	nsels = denali->nbanks;
112*d8e8fd0eSMasahiro Yamada 
113*d8e8fd0eSMasahiro Yamada 	dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
114*d8e8fd0eSMasahiro Yamada 			     GFP_KERNEL);
115*d8e8fd0eSMasahiro Yamada 	if (!dchip)
116*d8e8fd0eSMasahiro Yamada 		return -ENOMEM;
117*d8e8fd0eSMasahiro Yamada 
118*d8e8fd0eSMasahiro Yamada 	dchip->nsels = nsels;
119*d8e8fd0eSMasahiro Yamada 
120*d8e8fd0eSMasahiro Yamada 	for (i = 0; i < nsels; i++)
121*d8e8fd0eSMasahiro Yamada 		dchip->sels[i].bank = i;
122*d8e8fd0eSMasahiro Yamada 
123*d8e8fd0eSMasahiro Yamada 	nand_set_flash_node(&dchip->chip, denali->dev->of_node);
124*d8e8fd0eSMasahiro Yamada 
125*d8e8fd0eSMasahiro Yamada 	return denali_chip_init(denali, dchip);
126*d8e8fd0eSMasahiro Yamada }
127*d8e8fd0eSMasahiro Yamada 
128*d8e8fd0eSMasahiro Yamada /*
129*d8e8fd0eSMasahiro Yamada  * Check the DT binding.
130*d8e8fd0eSMasahiro Yamada  * The new binding expects chip subnodes in the controller node.
131*d8e8fd0eSMasahiro Yamada  * So, #address-cells = <1>; #size-cells = <0>; are required.
132*d8e8fd0eSMasahiro Yamada  * Check the #size-cells to distinguish the binding.
133*d8e8fd0eSMasahiro Yamada  */
134*d8e8fd0eSMasahiro Yamada static bool denali_dt_is_legacy_binding(struct device_node *np)
135*d8e8fd0eSMasahiro Yamada {
136*d8e8fd0eSMasahiro Yamada 	u32 cells;
137*d8e8fd0eSMasahiro Yamada 	int ret;
138*d8e8fd0eSMasahiro Yamada 
139*d8e8fd0eSMasahiro Yamada 	ret = of_property_read_u32(np, "#size-cells", &cells);
140*d8e8fd0eSMasahiro Yamada 	if (ret)
141*d8e8fd0eSMasahiro Yamada 		return true;
142*d8e8fd0eSMasahiro Yamada 
143*d8e8fd0eSMasahiro Yamada 	return cells != 0;
144*d8e8fd0eSMasahiro Yamada }
145*d8e8fd0eSMasahiro Yamada 
14693db446aSBoris Brezillon static int denali_dt_probe(struct platform_device *pdev)
14793db446aSBoris Brezillon {
148cd1beffaSMasahiro Yamada 	struct device *dev = &pdev->dev;
14993db446aSBoris Brezillon 	struct resource *res;
15093db446aSBoris Brezillon 	struct denali_dt *dt;
15193db446aSBoris Brezillon 	const struct denali_dt_data *data;
152*d8e8fd0eSMasahiro Yamada 	struct denali_controller *denali;
153*d8e8fd0eSMasahiro Yamada 	struct device_node *np;
15493db446aSBoris Brezillon 	int ret;
15593db446aSBoris Brezillon 
156cd1beffaSMasahiro Yamada 	dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
15793db446aSBoris Brezillon 	if (!dt)
15893db446aSBoris Brezillon 		return -ENOMEM;
159*d8e8fd0eSMasahiro Yamada 	denali = &dt->controller;
16093db446aSBoris Brezillon 
161cd1beffaSMasahiro Yamada 	data = of_device_get_match_data(dev);
16293db446aSBoris Brezillon 	if (data) {
16393db446aSBoris Brezillon 		denali->revision = data->revision;
16493db446aSBoris Brezillon 		denali->caps = data->caps;
16593db446aSBoris Brezillon 		denali->ecc_caps = data->ecc_caps;
16693db446aSBoris Brezillon 	}
16793db446aSBoris Brezillon 
168cd1beffaSMasahiro Yamada 	denali->dev = dev;
16993db446aSBoris Brezillon 	denali->irq = platform_get_irq(pdev, 0);
17093db446aSBoris Brezillon 	if (denali->irq < 0) {
171cd1beffaSMasahiro Yamada 		dev_err(dev, "no irq defined\n");
17293db446aSBoris Brezillon 		return denali->irq;
17393db446aSBoris Brezillon 	}
17493db446aSBoris Brezillon 
17593db446aSBoris Brezillon 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg");
176cd1beffaSMasahiro Yamada 	denali->reg = devm_ioremap_resource(dev, res);
17793db446aSBoris Brezillon 	if (IS_ERR(denali->reg))
17893db446aSBoris Brezillon 		return PTR_ERR(denali->reg);
17993db446aSBoris Brezillon 
18093db446aSBoris Brezillon 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
181cd1beffaSMasahiro Yamada 	denali->host = devm_ioremap_resource(dev, res);
18293db446aSBoris Brezillon 	if (IS_ERR(denali->host))
18393db446aSBoris Brezillon 		return PTR_ERR(denali->host);
18493db446aSBoris Brezillon 
1856f1fe97bSMasahiro Yamada 	dt->clk = devm_clk_get(dev, "nand");
1866f1fe97bSMasahiro Yamada 	if (IS_ERR(dt->clk))
18793db446aSBoris Brezillon 		return PTR_ERR(dt->clk);
1886f1fe97bSMasahiro Yamada 
1896f1fe97bSMasahiro Yamada 	dt->clk_x = devm_clk_get(dev, "nand_x");
1906f1fe97bSMasahiro Yamada 	if (IS_ERR(dt->clk_x))
19153bcbb83SMasahiro Yamada 		return PTR_ERR(dt->clk_x);
1926f1fe97bSMasahiro Yamada 
1936f1fe97bSMasahiro Yamada 	dt->clk_ecc = devm_clk_get(dev, "ecc");
1946f1fe97bSMasahiro Yamada 	if (IS_ERR(dt->clk_ecc))
19553bcbb83SMasahiro Yamada 		return PTR_ERR(dt->clk_ecc);
1966f1fe97bSMasahiro Yamada 
19793db446aSBoris Brezillon 	ret = clk_prepare_enable(dt->clk);
19893db446aSBoris Brezillon 	if (ret)
19993db446aSBoris Brezillon 		return ret;
20093db446aSBoris Brezillon 
2016f1fe97bSMasahiro Yamada 	ret = clk_prepare_enable(dt->clk_x);
2026f1fe97bSMasahiro Yamada 	if (ret)
2036f1fe97bSMasahiro Yamada 		goto out_disable_clk;
2046f1fe97bSMasahiro Yamada 
2056f1fe97bSMasahiro Yamada 	ret = clk_prepare_enable(dt->clk_ecc);
2066f1fe97bSMasahiro Yamada 	if (ret)
2076f1fe97bSMasahiro Yamada 		goto out_disable_clk_x;
2086f1fe97bSMasahiro Yamada 
2091dfac31aSMasahiro Yamada 	denali->clk_rate = clk_get_rate(dt->clk);
2106f1fe97bSMasahiro Yamada 	denali->clk_x_rate = clk_get_rate(dt->clk_x);
21193db446aSBoris Brezillon 
21293db446aSBoris Brezillon 	ret = denali_init(denali);
21393db446aSBoris Brezillon 	if (ret)
2146f1fe97bSMasahiro Yamada 		goto out_disable_clk_ecc;
21593db446aSBoris Brezillon 
216*d8e8fd0eSMasahiro Yamada 	if (denali_dt_is_legacy_binding(dev->of_node)) {
217*d8e8fd0eSMasahiro Yamada 		ret = denali_dt_legacy_chip_init(denali);
218*d8e8fd0eSMasahiro Yamada 		if (ret)
219*d8e8fd0eSMasahiro Yamada 			goto out_remove_denali;
220*d8e8fd0eSMasahiro Yamada 	} else {
221*d8e8fd0eSMasahiro Yamada 		for_each_child_of_node(dev->of_node, np) {
222*d8e8fd0eSMasahiro Yamada 			ret = denali_dt_chip_init(denali, np);
223*d8e8fd0eSMasahiro Yamada 			if (ret) {
224*d8e8fd0eSMasahiro Yamada 				of_node_put(np);
225*d8e8fd0eSMasahiro Yamada 				goto out_remove_denali;
226*d8e8fd0eSMasahiro Yamada 			}
227*d8e8fd0eSMasahiro Yamada 		}
228*d8e8fd0eSMasahiro Yamada 	}
229*d8e8fd0eSMasahiro Yamada 
23093db446aSBoris Brezillon 	platform_set_drvdata(pdev, dt);
231*d8e8fd0eSMasahiro Yamada 
23293db446aSBoris Brezillon 	return 0;
23393db446aSBoris Brezillon 
234*d8e8fd0eSMasahiro Yamada out_remove_denali:
235*d8e8fd0eSMasahiro Yamada 	denali_remove(denali);
2366f1fe97bSMasahiro Yamada out_disable_clk_ecc:
2376f1fe97bSMasahiro Yamada 	clk_disable_unprepare(dt->clk_ecc);
2386f1fe97bSMasahiro Yamada out_disable_clk_x:
2396f1fe97bSMasahiro Yamada 	clk_disable_unprepare(dt->clk_x);
24093db446aSBoris Brezillon out_disable_clk:
24193db446aSBoris Brezillon 	clk_disable_unprepare(dt->clk);
24293db446aSBoris Brezillon 
24393db446aSBoris Brezillon 	return ret;
24493db446aSBoris Brezillon }
24593db446aSBoris Brezillon 
24693db446aSBoris Brezillon static int denali_dt_remove(struct platform_device *pdev)
24793db446aSBoris Brezillon {
24893db446aSBoris Brezillon 	struct denali_dt *dt = platform_get_drvdata(pdev);
24993db446aSBoris Brezillon 
250*d8e8fd0eSMasahiro Yamada 	denali_remove(&dt->controller);
2516f1fe97bSMasahiro Yamada 	clk_disable_unprepare(dt->clk_ecc);
2526f1fe97bSMasahiro Yamada 	clk_disable_unprepare(dt->clk_x);
25393db446aSBoris Brezillon 	clk_disable_unprepare(dt->clk);
25493db446aSBoris Brezillon 
25593db446aSBoris Brezillon 	return 0;
25693db446aSBoris Brezillon }
25793db446aSBoris Brezillon 
25893db446aSBoris Brezillon static struct platform_driver denali_dt_driver = {
25993db446aSBoris Brezillon 	.probe		= denali_dt_probe,
26093db446aSBoris Brezillon 	.remove		= denali_dt_remove,
26193db446aSBoris Brezillon 	.driver		= {
26293db446aSBoris Brezillon 		.name	= "denali-nand-dt",
26393db446aSBoris Brezillon 		.of_match_table	= denali_nand_dt_ids,
26493db446aSBoris Brezillon 	},
26593db446aSBoris Brezillon };
26693db446aSBoris Brezillon module_platform_driver(denali_dt_driver);
26793db446aSBoris Brezillon 
268f1bf52e8SMasahiro Yamada MODULE_LICENSE("GPL v2");
26993db446aSBoris Brezillon MODULE_AUTHOR("Jamie Iles");
27093db446aSBoris Brezillon MODULE_DESCRIPTION("DT driver for Denali NAND controller");
271