1f1bf52e8SMasahiro Yamada // SPDX-License-Identifier: GPL-2.0
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon * NAND Flash Controller Device Driver for DT
493db446aSBoris Brezillon *
593db446aSBoris Brezillon * Copyright © 2011, Picochip.
693db446aSBoris Brezillon */
793db446aSBoris Brezillon
893db446aSBoris Brezillon #include <linux/clk.h>
9711fafc2SMasahiro Yamada #include <linux/delay.h>
1093db446aSBoris Brezillon #include <linux/err.h>
1193db446aSBoris Brezillon #include <linux/io.h>
1293db446aSBoris Brezillon #include <linux/ioport.h>
1393db446aSBoris Brezillon #include <linux/kernel.h>
1493db446aSBoris Brezillon #include <linux/module.h>
1593db446aSBoris Brezillon #include <linux/of.h>
1693db446aSBoris Brezillon #include <linux/platform_device.h>
17711fafc2SMasahiro Yamada #include <linux/reset.h>
1893db446aSBoris Brezillon
1993db446aSBoris Brezillon #include "denali.h"
2093db446aSBoris Brezillon
2193db446aSBoris Brezillon struct denali_dt {
22d8e8fd0eSMasahiro Yamada struct denali_controller controller;
236f1fe97bSMasahiro Yamada struct clk *clk; /* core clock */
246f1fe97bSMasahiro Yamada struct clk *clk_x; /* bus interface clock */
256f1fe97bSMasahiro Yamada struct clk *clk_ecc; /* ECC circuit clock */
26711fafc2SMasahiro Yamada struct reset_control *rst; /* core reset */
27711fafc2SMasahiro Yamada struct reset_control *rst_reg; /* register reset */
2893db446aSBoris Brezillon };
2993db446aSBoris Brezillon
3093db446aSBoris Brezillon struct denali_dt_data {
3193db446aSBoris Brezillon unsigned int revision;
3293db446aSBoris Brezillon unsigned int caps;
33f5561a7cSMarek Vasut unsigned int oob_skip_bytes;
3493db446aSBoris Brezillon const struct nand_ecc_caps *ecc_caps;
3593db446aSBoris Brezillon };
3693db446aSBoris Brezillon
3793db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
3893db446aSBoris Brezillon 512, 8, 15);
3993db446aSBoris Brezillon static const struct denali_dt_data denali_socfpga_data = {
4093db446aSBoris Brezillon .caps = DENALI_CAP_HW_ECC_FIXUP,
41f5561a7cSMarek Vasut .oob_skip_bytes = 2,
4293db446aSBoris Brezillon .ecc_caps = &denali_socfpga_ecc_caps,
4393db446aSBoris Brezillon };
4493db446aSBoris Brezillon
4593db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
4693db446aSBoris Brezillon 1024, 8, 16, 24);
4793db446aSBoris Brezillon static const struct denali_dt_data denali_uniphier_v5a_data = {
4893db446aSBoris Brezillon .caps = DENALI_CAP_HW_ECC_FIXUP |
4993db446aSBoris Brezillon DENALI_CAP_DMA_64BIT,
50f5561a7cSMarek Vasut .oob_skip_bytes = 8,
5193db446aSBoris Brezillon .ecc_caps = &denali_uniphier_v5a_ecc_caps,
5293db446aSBoris Brezillon };
5393db446aSBoris Brezillon
5493db446aSBoris Brezillon NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
5593db446aSBoris Brezillon 1024, 8, 16);
5693db446aSBoris Brezillon static const struct denali_dt_data denali_uniphier_v5b_data = {
5793db446aSBoris Brezillon .revision = 0x0501,
5893db446aSBoris Brezillon .caps = DENALI_CAP_HW_ECC_FIXUP |
5993db446aSBoris Brezillon DENALI_CAP_DMA_64BIT,
60f5561a7cSMarek Vasut .oob_skip_bytes = 8,
6193db446aSBoris Brezillon .ecc_caps = &denali_uniphier_v5b_ecc_caps,
6293db446aSBoris Brezillon };
6393db446aSBoris Brezillon
6493db446aSBoris Brezillon static const struct of_device_id denali_nand_dt_ids[] = {
6593db446aSBoris Brezillon {
6693db446aSBoris Brezillon .compatible = "altr,socfpga-denali-nand",
6793db446aSBoris Brezillon .data = &denali_socfpga_data,
6893db446aSBoris Brezillon },
6993db446aSBoris Brezillon {
7093db446aSBoris Brezillon .compatible = "socionext,uniphier-denali-nand-v5a",
7193db446aSBoris Brezillon .data = &denali_uniphier_v5a_data,
7293db446aSBoris Brezillon },
7393db446aSBoris Brezillon {
7493db446aSBoris Brezillon .compatible = "socionext,uniphier-denali-nand-v5b",
7593db446aSBoris Brezillon .data = &denali_uniphier_v5b_data,
7693db446aSBoris Brezillon },
7793db446aSBoris Brezillon { /* sentinel */ }
7893db446aSBoris Brezillon };
7993db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
8093db446aSBoris Brezillon
denali_dt_chip_init(struct denali_controller * denali,struct device_node * chip_np)81d8e8fd0eSMasahiro Yamada static int denali_dt_chip_init(struct denali_controller *denali,
82d8e8fd0eSMasahiro Yamada struct device_node *chip_np)
83d8e8fd0eSMasahiro Yamada {
84d8e8fd0eSMasahiro Yamada struct denali_chip *dchip;
85d8e8fd0eSMasahiro Yamada u32 bank;
86d8e8fd0eSMasahiro Yamada int nsels, i, ret;
87d8e8fd0eSMasahiro Yamada
88d8e8fd0eSMasahiro Yamada nsels = of_property_count_u32_elems(chip_np, "reg");
89d8e8fd0eSMasahiro Yamada if (nsels < 0)
90d8e8fd0eSMasahiro Yamada return nsels;
91d8e8fd0eSMasahiro Yamada
92d8e8fd0eSMasahiro Yamada dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
93d8e8fd0eSMasahiro Yamada GFP_KERNEL);
94d8e8fd0eSMasahiro Yamada if (!dchip)
95d8e8fd0eSMasahiro Yamada return -ENOMEM;
96d8e8fd0eSMasahiro Yamada
97d8e8fd0eSMasahiro Yamada dchip->nsels = nsels;
98d8e8fd0eSMasahiro Yamada
99d8e8fd0eSMasahiro Yamada for (i = 0; i < nsels; i++) {
100d8e8fd0eSMasahiro Yamada ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
101d8e8fd0eSMasahiro Yamada if (ret)
102d8e8fd0eSMasahiro Yamada return ret;
103d8e8fd0eSMasahiro Yamada
104d8e8fd0eSMasahiro Yamada dchip->sels[i].bank = bank;
105d8e8fd0eSMasahiro Yamada
106d8e8fd0eSMasahiro Yamada nand_set_flash_node(&dchip->chip, chip_np);
107d8e8fd0eSMasahiro Yamada }
108d8e8fd0eSMasahiro Yamada
109d8e8fd0eSMasahiro Yamada return denali_chip_init(denali, dchip);
110d8e8fd0eSMasahiro Yamada }
111d8e8fd0eSMasahiro Yamada
denali_dt_probe(struct platform_device * pdev)11293db446aSBoris Brezillon static int denali_dt_probe(struct platform_device *pdev)
11393db446aSBoris Brezillon {
114cd1beffaSMasahiro Yamada struct device *dev = &pdev->dev;
11593db446aSBoris Brezillon struct denali_dt *dt;
11693db446aSBoris Brezillon const struct denali_dt_data *data;
117d8e8fd0eSMasahiro Yamada struct denali_controller *denali;
118d8e8fd0eSMasahiro Yamada struct device_node *np;
11993db446aSBoris Brezillon int ret;
12093db446aSBoris Brezillon
121cd1beffaSMasahiro Yamada dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
12293db446aSBoris Brezillon if (!dt)
12393db446aSBoris Brezillon return -ENOMEM;
124d8e8fd0eSMasahiro Yamada denali = &dt->controller;
12593db446aSBoris Brezillon
126cd1beffaSMasahiro Yamada data = of_device_get_match_data(dev);
12782348201SMasahiro Yamada if (WARN_ON(!data))
12882348201SMasahiro Yamada return -EINVAL;
12982348201SMasahiro Yamada
13093db446aSBoris Brezillon denali->revision = data->revision;
13193db446aSBoris Brezillon denali->caps = data->caps;
132f5561a7cSMarek Vasut denali->oob_skip_bytes = data->oob_skip_bytes;
13393db446aSBoris Brezillon denali->ecc_caps = data->ecc_caps;
13493db446aSBoris Brezillon
135cd1beffaSMasahiro Yamada denali->dev = dev;
13693db446aSBoris Brezillon denali->irq = platform_get_irq(pdev, 0);
137aab478caSStephen Boyd if (denali->irq < 0)
13893db446aSBoris Brezillon return denali->irq;
13993db446aSBoris Brezillon
1405f14a8caSCai Huoqing denali->reg = devm_platform_ioremap_resource_byname(pdev, "denali_reg");
14193db446aSBoris Brezillon if (IS_ERR(denali->reg))
14293db446aSBoris Brezillon return PTR_ERR(denali->reg);
14393db446aSBoris Brezillon
1445f14a8caSCai Huoqing denali->host = devm_platform_ioremap_resource_byname(pdev, "nand_data");
14593db446aSBoris Brezillon if (IS_ERR(denali->host))
14693db446aSBoris Brezillon return PTR_ERR(denali->host);
14793db446aSBoris Brezillon
1486f1fe97bSMasahiro Yamada dt->clk = devm_clk_get(dev, "nand");
1496f1fe97bSMasahiro Yamada if (IS_ERR(dt->clk))
15093db446aSBoris Brezillon return PTR_ERR(dt->clk);
1516f1fe97bSMasahiro Yamada
1526f1fe97bSMasahiro Yamada dt->clk_x = devm_clk_get(dev, "nand_x");
1536f1fe97bSMasahiro Yamada if (IS_ERR(dt->clk_x))
15453bcbb83SMasahiro Yamada return PTR_ERR(dt->clk_x);
1556f1fe97bSMasahiro Yamada
1566f1fe97bSMasahiro Yamada dt->clk_ecc = devm_clk_get(dev, "ecc");
1576f1fe97bSMasahiro Yamada if (IS_ERR(dt->clk_ecc))
15853bcbb83SMasahiro Yamada return PTR_ERR(dt->clk_ecc);
1596f1fe97bSMasahiro Yamada
160711fafc2SMasahiro Yamada dt->rst = devm_reset_control_get_optional_shared(dev, "nand");
161711fafc2SMasahiro Yamada if (IS_ERR(dt->rst))
162711fafc2SMasahiro Yamada return PTR_ERR(dt->rst);
163711fafc2SMasahiro Yamada
164711fafc2SMasahiro Yamada dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg");
165711fafc2SMasahiro Yamada if (IS_ERR(dt->rst_reg))
166711fafc2SMasahiro Yamada return PTR_ERR(dt->rst_reg);
167711fafc2SMasahiro Yamada
16893db446aSBoris Brezillon ret = clk_prepare_enable(dt->clk);
16993db446aSBoris Brezillon if (ret)
17093db446aSBoris Brezillon return ret;
17193db446aSBoris Brezillon
1726f1fe97bSMasahiro Yamada ret = clk_prepare_enable(dt->clk_x);
1736f1fe97bSMasahiro Yamada if (ret)
1746f1fe97bSMasahiro Yamada goto out_disable_clk;
1756f1fe97bSMasahiro Yamada
1766f1fe97bSMasahiro Yamada ret = clk_prepare_enable(dt->clk_ecc);
1776f1fe97bSMasahiro Yamada if (ret)
1786f1fe97bSMasahiro Yamada goto out_disable_clk_x;
1796f1fe97bSMasahiro Yamada
1801dfac31aSMasahiro Yamada denali->clk_rate = clk_get_rate(dt->clk);
1816f1fe97bSMasahiro Yamada denali->clk_x_rate = clk_get_rate(dt->clk_x);
18293db446aSBoris Brezillon
183711fafc2SMasahiro Yamada /*
184711fafc2SMasahiro Yamada * Deassert the register reset, and the core reset in this order.
185711fafc2SMasahiro Yamada * Deasserting the core reset while the register reset is asserted
186711fafc2SMasahiro Yamada * will cause unpredictable behavior in the controller.
187711fafc2SMasahiro Yamada */
188711fafc2SMasahiro Yamada ret = reset_control_deassert(dt->rst_reg);
18993db446aSBoris Brezillon if (ret)
1906f1fe97bSMasahiro Yamada goto out_disable_clk_ecc;
19193db446aSBoris Brezillon
192711fafc2SMasahiro Yamada ret = reset_control_deassert(dt->rst);
193711fafc2SMasahiro Yamada if (ret)
194711fafc2SMasahiro Yamada goto out_assert_rst_reg;
195711fafc2SMasahiro Yamada
196711fafc2SMasahiro Yamada /*
197711fafc2SMasahiro Yamada * When the reset is deasserted, the initialization sequence is kicked
198711fafc2SMasahiro Yamada * (bootstrap process). The driver must wait until it finished.
199711fafc2SMasahiro Yamada * Otherwise, it will result in unpredictable behavior.
200711fafc2SMasahiro Yamada */
201711fafc2SMasahiro Yamada usleep_range(200, 1000);
202711fafc2SMasahiro Yamada
203711fafc2SMasahiro Yamada ret = denali_init(denali);
204711fafc2SMasahiro Yamada if (ret)
205711fafc2SMasahiro Yamada goto out_assert_rst;
206711fafc2SMasahiro Yamada
207d8e8fd0eSMasahiro Yamada for_each_child_of_node(dev->of_node, np) {
208d8e8fd0eSMasahiro Yamada ret = denali_dt_chip_init(denali, np);
209d8e8fd0eSMasahiro Yamada if (ret) {
210d8e8fd0eSMasahiro Yamada of_node_put(np);
211d8e8fd0eSMasahiro Yamada goto out_remove_denali;
212d8e8fd0eSMasahiro Yamada }
213d8e8fd0eSMasahiro Yamada }
214d8e8fd0eSMasahiro Yamada
21593db446aSBoris Brezillon platform_set_drvdata(pdev, dt);
216d8e8fd0eSMasahiro Yamada
21793db446aSBoris Brezillon return 0;
21893db446aSBoris Brezillon
219d8e8fd0eSMasahiro Yamada out_remove_denali:
220d8e8fd0eSMasahiro Yamada denali_remove(denali);
221711fafc2SMasahiro Yamada out_assert_rst:
222711fafc2SMasahiro Yamada reset_control_assert(dt->rst);
223711fafc2SMasahiro Yamada out_assert_rst_reg:
224711fafc2SMasahiro Yamada reset_control_assert(dt->rst_reg);
2256f1fe97bSMasahiro Yamada out_disable_clk_ecc:
2266f1fe97bSMasahiro Yamada clk_disable_unprepare(dt->clk_ecc);
2276f1fe97bSMasahiro Yamada out_disable_clk_x:
2286f1fe97bSMasahiro Yamada clk_disable_unprepare(dt->clk_x);
22993db446aSBoris Brezillon out_disable_clk:
23093db446aSBoris Brezillon clk_disable_unprepare(dt->clk);
23193db446aSBoris Brezillon
23293db446aSBoris Brezillon return ret;
23393db446aSBoris Brezillon }
23493db446aSBoris Brezillon
denali_dt_remove(struct platform_device * pdev)235*ec185b18SUwe Kleine-König static void denali_dt_remove(struct platform_device *pdev)
23693db446aSBoris Brezillon {
23793db446aSBoris Brezillon struct denali_dt *dt = platform_get_drvdata(pdev);
23893db446aSBoris Brezillon
239d8e8fd0eSMasahiro Yamada denali_remove(&dt->controller);
240711fafc2SMasahiro Yamada reset_control_assert(dt->rst);
241711fafc2SMasahiro Yamada reset_control_assert(dt->rst_reg);
2426f1fe97bSMasahiro Yamada clk_disable_unprepare(dt->clk_ecc);
2436f1fe97bSMasahiro Yamada clk_disable_unprepare(dt->clk_x);
24493db446aSBoris Brezillon clk_disable_unprepare(dt->clk);
24593db446aSBoris Brezillon }
24693db446aSBoris Brezillon
24793db446aSBoris Brezillon static struct platform_driver denali_dt_driver = {
24893db446aSBoris Brezillon .probe = denali_dt_probe,
249*ec185b18SUwe Kleine-König .remove_new = denali_dt_remove,
25093db446aSBoris Brezillon .driver = {
25193db446aSBoris Brezillon .name = "denali-nand-dt",
25293db446aSBoris Brezillon .of_match_table = denali_nand_dt_ids,
25393db446aSBoris Brezillon },
25493db446aSBoris Brezillon };
25593db446aSBoris Brezillon module_platform_driver(denali_dt_driver);
25693db446aSBoris Brezillon
257f1bf52e8SMasahiro Yamada MODULE_LICENSE("GPL v2");
25893db446aSBoris Brezillon MODULE_AUTHOR("Jamie Iles");
25993db446aSBoris Brezillon MODULE_DESCRIPTION("DT driver for Denali NAND controller");
260