1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/leds.h> 21 #include <linux/interrupt.h> 22 23 #include <linux/mmc/host.h> 24 25 /* 26 * Controller registers 27 */ 28 29 #define SDHCI_DMA_ADDRESS 0x00 30 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 31 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 32 33 #define SDHCI_BLOCK_SIZE 0x04 34 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 35 36 #define SDHCI_BLOCK_COUNT 0x06 37 38 #define SDHCI_ARGUMENT 0x08 39 40 #define SDHCI_TRANSFER_MODE 0x0C 41 #define SDHCI_TRNS_DMA 0x01 42 #define SDHCI_TRNS_BLK_CNT_EN 0x02 43 #define SDHCI_TRNS_AUTO_CMD12 0x04 44 #define SDHCI_TRNS_AUTO_CMD23 0x08 45 #define SDHCI_TRNS_AUTO_SEL 0x0C 46 #define SDHCI_TRNS_READ 0x10 47 #define SDHCI_TRNS_MULTI 0x20 48 49 #define SDHCI_COMMAND 0x0E 50 #define SDHCI_CMD_RESP_MASK 0x03 51 #define SDHCI_CMD_CRC 0x08 52 #define SDHCI_CMD_INDEX 0x10 53 #define SDHCI_CMD_DATA 0x20 54 #define SDHCI_CMD_ABORTCMD 0xC0 55 56 #define SDHCI_CMD_RESP_NONE 0x00 57 #define SDHCI_CMD_RESP_LONG 0x01 58 #define SDHCI_CMD_RESP_SHORT 0x02 59 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 60 61 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 62 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 63 64 #define SDHCI_RESPONSE 0x10 65 66 #define SDHCI_BUFFER 0x20 67 68 #define SDHCI_PRESENT_STATE 0x24 69 #define SDHCI_CMD_INHIBIT 0x00000001 70 #define SDHCI_DATA_INHIBIT 0x00000002 71 #define SDHCI_DOING_WRITE 0x00000100 72 #define SDHCI_DOING_READ 0x00000200 73 #define SDHCI_SPACE_AVAILABLE 0x00000400 74 #define SDHCI_DATA_AVAILABLE 0x00000800 75 #define SDHCI_CARD_PRESENT 0x00010000 76 #define SDHCI_WRITE_PROTECT 0x00080000 77 #define SDHCI_DATA_LVL_MASK 0x00F00000 78 #define SDHCI_DATA_LVL_SHIFT 20 79 #define SDHCI_DATA_0_LVL_MASK 0x00100000 80 #define SDHCI_CMD_LVL 0x01000000 81 82 #define SDHCI_HOST_CONTROL 0x28 83 #define SDHCI_CTRL_LED 0x01 84 #define SDHCI_CTRL_4BITBUS 0x02 85 #define SDHCI_CTRL_HISPD 0x04 86 #define SDHCI_CTRL_DMA_MASK 0x18 87 #define SDHCI_CTRL_SDMA 0x00 88 #define SDHCI_CTRL_ADMA1 0x08 89 #define SDHCI_CTRL_ADMA32 0x10 90 #define SDHCI_CTRL_ADMA64 0x18 91 #define SDHCI_CTRL_8BITBUS 0x20 92 #define SDHCI_CTRL_CDTEST_INS 0x40 93 #define SDHCI_CTRL_CDTEST_EN 0x80 94 95 #define SDHCI_POWER_CONTROL 0x29 96 #define SDHCI_POWER_ON 0x01 97 #define SDHCI_POWER_180 0x0A 98 #define SDHCI_POWER_300 0x0C 99 #define SDHCI_POWER_330 0x0E 100 101 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 102 103 #define SDHCI_WAKE_UP_CONTROL 0x2B 104 #define SDHCI_WAKE_ON_INT 0x01 105 #define SDHCI_WAKE_ON_INSERT 0x02 106 #define SDHCI_WAKE_ON_REMOVE 0x04 107 108 #define SDHCI_CLOCK_CONTROL 0x2C 109 #define SDHCI_DIVIDER_SHIFT 8 110 #define SDHCI_DIVIDER_HI_SHIFT 6 111 #define SDHCI_DIV_MASK 0xFF 112 #define SDHCI_DIV_MASK_LEN 8 113 #define SDHCI_DIV_HI_MASK 0x300 114 #define SDHCI_PROG_CLOCK_MODE 0x0020 115 #define SDHCI_CLOCK_CARD_EN 0x0004 116 #define SDHCI_CLOCK_INT_STABLE 0x0002 117 #define SDHCI_CLOCK_INT_EN 0x0001 118 119 #define SDHCI_TIMEOUT_CONTROL 0x2E 120 121 #define SDHCI_SOFTWARE_RESET 0x2F 122 #define SDHCI_RESET_ALL 0x01 123 #define SDHCI_RESET_CMD 0x02 124 #define SDHCI_RESET_DATA 0x04 125 126 #define SDHCI_INT_STATUS 0x30 127 #define SDHCI_INT_ENABLE 0x34 128 #define SDHCI_SIGNAL_ENABLE 0x38 129 #define SDHCI_INT_RESPONSE 0x00000001 130 #define SDHCI_INT_DATA_END 0x00000002 131 #define SDHCI_INT_BLK_GAP 0x00000004 132 #define SDHCI_INT_DMA_END 0x00000008 133 #define SDHCI_INT_SPACE_AVAIL 0x00000010 134 #define SDHCI_INT_DATA_AVAIL 0x00000020 135 #define SDHCI_INT_CARD_INSERT 0x00000040 136 #define SDHCI_INT_CARD_REMOVE 0x00000080 137 #define SDHCI_INT_CARD_INT 0x00000100 138 #define SDHCI_INT_RETUNE 0x00001000 139 #define SDHCI_INT_CQE 0x00004000 140 #define SDHCI_INT_ERROR 0x00008000 141 #define SDHCI_INT_TIMEOUT 0x00010000 142 #define SDHCI_INT_CRC 0x00020000 143 #define SDHCI_INT_END_BIT 0x00040000 144 #define SDHCI_INT_INDEX 0x00080000 145 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 146 #define SDHCI_INT_DATA_CRC 0x00200000 147 #define SDHCI_INT_DATA_END_BIT 0x00400000 148 #define SDHCI_INT_BUS_POWER 0x00800000 149 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 150 #define SDHCI_INT_ADMA_ERROR 0x02000000 151 152 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 153 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 154 155 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 156 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 157 SDHCI_INT_AUTO_CMD_ERR) 158 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 159 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 160 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 161 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 162 SDHCI_INT_BLK_GAP) 163 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 164 165 #define SDHCI_CQE_INT_ERR_MASK ( \ 166 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 167 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 168 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 169 170 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 171 172 #define SDHCI_AUTO_CMD_STATUS 0x3C 173 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 174 #define SDHCI_AUTO_CMD_CRC 0x00000004 175 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 176 #define SDHCI_AUTO_CMD_INDEX 0x00000010 177 178 #define SDHCI_HOST_CONTROL2 0x3E 179 #define SDHCI_CTRL_UHS_MASK 0x0007 180 #define SDHCI_CTRL_UHS_SDR12 0x0000 181 #define SDHCI_CTRL_UHS_SDR25 0x0001 182 #define SDHCI_CTRL_UHS_SDR50 0x0002 183 #define SDHCI_CTRL_UHS_SDR104 0x0003 184 #define SDHCI_CTRL_UHS_DDR50 0x0004 185 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 186 #define SDHCI_CTRL_VDD_180 0x0008 187 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 188 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 189 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 190 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 191 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 192 #define SDHCI_CTRL_EXEC_TUNING 0x0040 193 #define SDHCI_CTRL_TUNED_CLK 0x0080 194 #define SDHCI_CMD23_ENABLE 0x0800 195 #define SDHCI_CTRL_V4_MODE 0x1000 196 #define SDHCI_CTRL_64BIT_ADDR 0x2000 197 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 198 199 #define SDHCI_CAPABILITIES 0x40 200 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 201 #define SDHCI_TIMEOUT_CLK_SHIFT 0 202 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 203 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 204 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 205 #define SDHCI_CLOCK_BASE_SHIFT 8 206 #define SDHCI_MAX_BLOCK_MASK 0x00030000 207 #define SDHCI_MAX_BLOCK_SHIFT 16 208 #define SDHCI_CAN_DO_8BIT 0x00040000 209 #define SDHCI_CAN_DO_ADMA2 0x00080000 210 #define SDHCI_CAN_DO_ADMA1 0x00100000 211 #define SDHCI_CAN_DO_HISPD 0x00200000 212 #define SDHCI_CAN_DO_SDMA 0x00400000 213 #define SDHCI_CAN_DO_SUSPEND 0x00800000 214 #define SDHCI_CAN_VDD_330 0x01000000 215 #define SDHCI_CAN_VDD_300 0x02000000 216 #define SDHCI_CAN_VDD_180 0x04000000 217 #define SDHCI_CAN_64BIT_V4 0x08000000 218 #define SDHCI_CAN_64BIT 0x10000000 219 220 #define SDHCI_SUPPORT_SDR50 0x00000001 221 #define SDHCI_SUPPORT_SDR104 0x00000002 222 #define SDHCI_SUPPORT_DDR50 0x00000004 223 #define SDHCI_DRIVER_TYPE_A 0x00000010 224 #define SDHCI_DRIVER_TYPE_C 0x00000020 225 #define SDHCI_DRIVER_TYPE_D 0x00000040 226 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 227 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 228 #define SDHCI_USE_SDR50_TUNING 0x00002000 229 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 230 #define SDHCI_RETUNING_MODE_SHIFT 14 231 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 232 #define SDHCI_CLOCK_MUL_SHIFT 16 233 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 234 235 #define SDHCI_CAPABILITIES_1 0x44 236 237 #define SDHCI_MAX_CURRENT 0x48 238 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 239 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 240 #define SDHCI_MAX_CURRENT_330_SHIFT 0 241 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 242 #define SDHCI_MAX_CURRENT_300_SHIFT 8 243 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 244 #define SDHCI_MAX_CURRENT_180_SHIFT 16 245 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 246 247 /* 4C-4F reserved for more max current */ 248 249 #define SDHCI_SET_ACMD12_ERROR 0x50 250 #define SDHCI_SET_INT_ERROR 0x52 251 252 #define SDHCI_ADMA_ERROR 0x54 253 254 /* 55-57 reserved */ 255 256 #define SDHCI_ADMA_ADDRESS 0x58 257 #define SDHCI_ADMA_ADDRESS_HI 0x5C 258 259 /* 60-FB reserved */ 260 261 #define SDHCI_PRESET_FOR_SDR12 0x66 262 #define SDHCI_PRESET_FOR_SDR25 0x68 263 #define SDHCI_PRESET_FOR_SDR50 0x6A 264 #define SDHCI_PRESET_FOR_SDR104 0x6C 265 #define SDHCI_PRESET_FOR_DDR50 0x6E 266 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 267 #define SDHCI_PRESET_DRV_MASK 0xC000 268 #define SDHCI_PRESET_DRV_SHIFT 14 269 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 270 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 271 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 272 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 273 274 #define SDHCI_SLOT_INT_STATUS 0xFC 275 276 #define SDHCI_HOST_VERSION 0xFE 277 #define SDHCI_VENDOR_VER_MASK 0xFF00 278 #define SDHCI_VENDOR_VER_SHIFT 8 279 #define SDHCI_SPEC_VER_MASK 0x00FF 280 #define SDHCI_SPEC_VER_SHIFT 0 281 #define SDHCI_SPEC_100 0 282 #define SDHCI_SPEC_200 1 283 #define SDHCI_SPEC_300 2 284 #define SDHCI_SPEC_400 3 285 #define SDHCI_SPEC_410 4 286 #define SDHCI_SPEC_420 5 287 288 /* 289 * End of controller registers. 290 */ 291 292 #define SDHCI_MAX_DIV_SPEC_200 256 293 #define SDHCI_MAX_DIV_SPEC_300 2046 294 295 /* 296 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 297 */ 298 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 299 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 300 301 /* ADMA2 32-bit DMA descriptor size */ 302 #define SDHCI_ADMA2_32_DESC_SZ 8 303 304 /* ADMA2 32-bit descriptor */ 305 struct sdhci_adma2_32_desc { 306 __le16 cmd; 307 __le16 len; 308 __le32 addr; 309 } __packed __aligned(4); 310 311 /* ADMA2 data alignment */ 312 #define SDHCI_ADMA2_ALIGN 4 313 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 314 315 /* 316 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 317 * alignment for the descriptor table even in 32-bit DMA mode. Memory 318 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 319 */ 320 #define SDHCI_ADMA2_DESC_ALIGN 8 321 322 /* 323 * ADMA2 64-bit DMA descriptor size 324 * According to SD Host Controller spec v4.10, there are two kinds of 325 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 326 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 327 * register, 128-bit Descriptor will be selected. 328 */ 329 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 330 331 /* 332 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 333 * aligned. 334 */ 335 struct sdhci_adma2_64_desc { 336 __le16 cmd; 337 __le16 len; 338 __le32 addr_lo; 339 __le32 addr_hi; 340 } __packed __aligned(4); 341 342 #define ADMA2_TRAN_VALID 0x21 343 #define ADMA2_NOP_END_VALID 0x3 344 #define ADMA2_END 0x2 345 346 /* 347 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 348 * 4KiB page size. 349 */ 350 #define SDHCI_MAX_SEGS 128 351 352 /* Allow for a a command request and a data request at the same time */ 353 #define SDHCI_MAX_MRQS 2 354 355 /* 356 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 357 * However since the start time of the command, the time between 358 * command and response, and the time between response and start of data is 359 * not known, set the command transfer time to 10ms. 360 */ 361 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 362 363 enum sdhci_cookie { 364 COOKIE_UNMAPPED, 365 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 366 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 367 }; 368 369 struct sdhci_host { 370 /* Data set by hardware interface driver */ 371 const char *hw_name; /* Hardware bus name */ 372 373 unsigned int quirks; /* Deviations from spec. */ 374 375 /* Controller doesn't honor resets unless we touch the clock register */ 376 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 377 /* Controller has bad caps bits, but really supports DMA */ 378 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 379 /* Controller doesn't like to be reset when there is no card inserted. */ 380 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 381 /* Controller doesn't like clearing the power reg before a change */ 382 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 383 /* Controller has flaky internal state so reset it on each ios change */ 384 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 385 /* Controller has an unusable DMA engine */ 386 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 387 /* Controller has an unusable ADMA engine */ 388 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 389 /* Controller can only DMA from 32-bit aligned addresses */ 390 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 391 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 392 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 393 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 394 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 395 /* Controller needs to be reset after each request to stay stable */ 396 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 397 /* Controller needs voltage and power writes to happen separately */ 398 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 399 /* Controller provides an incorrect timeout value for transfers */ 400 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 401 /* Controller has an issue with buffer bits for small transfers */ 402 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 403 /* Controller does not provide transfer-complete interrupt when not busy */ 404 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 405 /* Controller has unreliable card detection */ 406 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 407 /* Controller reports inverted write-protect state */ 408 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 409 /* Controller does not like fast PIO transfers */ 410 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 411 /* Controller does not have a LED */ 412 #define SDHCI_QUIRK_NO_LED (1<<19) 413 /* Controller has to be forced to use block size of 2048 bytes */ 414 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 415 /* Controller cannot do multi-block transfers */ 416 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 417 /* Controller can only handle 1-bit data transfers */ 418 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 419 /* Controller needs 10ms delay between applying power and clock */ 420 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 421 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 422 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 423 /* Controller reports wrong base clock capability */ 424 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 425 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 426 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 427 /* Controller is missing device caps. Use caps provided by host */ 428 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 429 /* Controller uses Auto CMD12 command to stop the transfer */ 430 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 431 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 432 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 433 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 434 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 435 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 436 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 437 438 unsigned int quirks2; /* More deviations from spec. */ 439 440 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 441 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 442 /* The system physically doesn't support 1.8v, even if the host does */ 443 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 444 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 445 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 446 /* Controller has a non-standard host control register */ 447 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 448 /* Controller does not support HS200 */ 449 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 450 /* Controller does not support DDR50 */ 451 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 452 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 453 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 454 /* Controller does not support 64-bit DMA */ 455 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 456 /* need clear transfer mode register before send cmd */ 457 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 458 /* Capability register bit-63 indicates HS400 support */ 459 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 460 /* forced tuned clock */ 461 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 462 /* disable the block count for single block transactions */ 463 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 464 /* Controller broken with using ACMD23 */ 465 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 466 /* Broken Clock divider zero in controller */ 467 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 468 /* Controller has CRC in 136 bit Command Response */ 469 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 470 /* 471 * Disable HW timeout if the requested timeout is more than the maximum 472 * obtainable timeout. 473 */ 474 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 475 /* 476 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 477 * for other purposes. Consequently we support 16-bit block count by default. 478 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 479 * block count. 480 */ 481 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 482 483 int irq; /* Device IRQ */ 484 void __iomem *ioaddr; /* Mapped address */ 485 char *bounce_buffer; /* For packing SDMA reads/writes */ 486 dma_addr_t bounce_addr; 487 unsigned int bounce_buffer_size; 488 489 const struct sdhci_ops *ops; /* Low level hw interface */ 490 491 /* Internal data */ 492 struct mmc_host *mmc; /* MMC structure */ 493 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 494 u64 dma_mask; /* custom DMA mask */ 495 496 #if IS_ENABLED(CONFIG_LEDS_CLASS) 497 struct led_classdev led; /* LED control */ 498 char led_name[32]; 499 #endif 500 501 spinlock_t lock; /* Mutex */ 502 503 int flags; /* Host attributes */ 504 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 505 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 506 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 507 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 508 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 509 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 510 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 511 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 512 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 513 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 514 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 515 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 516 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 517 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 518 519 unsigned int version; /* SDHCI spec. version */ 520 521 unsigned int max_clk; /* Max possible freq (MHz) */ 522 unsigned int timeout_clk; /* Timeout freq (KHz) */ 523 unsigned int clk_mul; /* Clock Muliplier value */ 524 525 unsigned int clock; /* Current clock (MHz) */ 526 u8 pwr; /* Current voltage */ 527 528 bool runtime_suspended; /* Host is runtime suspended */ 529 bool bus_on; /* Bus power prevents runtime suspend */ 530 bool preset_enabled; /* Preset is enabled */ 531 bool pending_reset; /* Cmd/data reset is pending */ 532 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 533 bool v4_mode; /* Host Version 4 Enable */ 534 535 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 536 struct mmc_command *cmd; /* Current command */ 537 struct mmc_command *data_cmd; /* Current data command */ 538 struct mmc_data *data; /* Current data request */ 539 unsigned int data_early:1; /* Data finished before cmd */ 540 541 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 542 unsigned int blocks; /* remaining PIO blocks */ 543 544 int sg_count; /* Mapped sg entries */ 545 546 void *adma_table; /* ADMA descriptor table */ 547 void *align_buffer; /* Bounce buffer */ 548 549 size_t adma_table_sz; /* ADMA descriptor table size */ 550 size_t align_buffer_sz; /* Bounce buffer size */ 551 552 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 553 dma_addr_t align_addr; /* Mapped bounce buffer */ 554 555 unsigned int desc_sz; /* ADMA descriptor size */ 556 557 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 558 559 struct timer_list timer; /* Timer for timeouts */ 560 struct timer_list data_timer; /* Timer for data timeouts */ 561 562 u32 caps; /* CAPABILITY_0 */ 563 u32 caps1; /* CAPABILITY_1 */ 564 bool read_caps; /* Capability flags have been read */ 565 566 unsigned int ocr_avail_sdio; /* OCR bit masks */ 567 unsigned int ocr_avail_sd; 568 unsigned int ocr_avail_mmc; 569 u32 ocr_mask; /* available voltages */ 570 571 unsigned timing; /* Current timing */ 572 573 u32 thread_isr; 574 575 /* cached registers */ 576 u32 ier; 577 578 bool cqe_on; /* CQE is operating */ 579 u32 cqe_ier; /* CQE interrupt mask */ 580 u32 cqe_err_ier; /* CQE error interrupt mask */ 581 582 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 583 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 584 585 unsigned int tuning_count; /* Timer count for re-tuning */ 586 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 587 unsigned int tuning_err; /* Error code for re-tuning */ 588 #define SDHCI_TUNING_MODE_1 0 589 #define SDHCI_TUNING_MODE_2 1 590 #define SDHCI_TUNING_MODE_3 2 591 /* Delay (ms) between tuning commands */ 592 int tuning_delay; 593 594 /* Host SDMA buffer boundary. */ 595 u32 sdma_boundary; 596 597 /* Host ADMA table count */ 598 u32 adma_table_cnt; 599 600 u64 data_timeout; 601 602 unsigned long private[0] ____cacheline_aligned; 603 }; 604 605 struct sdhci_ops { 606 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 607 u32 (*read_l)(struct sdhci_host *host, int reg); 608 u16 (*read_w)(struct sdhci_host *host, int reg); 609 u8 (*read_b)(struct sdhci_host *host, int reg); 610 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 611 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 612 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 613 #endif 614 615 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 616 void (*set_power)(struct sdhci_host *host, unsigned char mode, 617 unsigned short vdd); 618 619 u32 (*irq)(struct sdhci_host *host, u32 intmask); 620 621 int (*enable_dma)(struct sdhci_host *host); 622 unsigned int (*get_max_clock)(struct sdhci_host *host); 623 unsigned int (*get_min_clock)(struct sdhci_host *host); 624 /* get_timeout_clock should return clk rate in unit of Hz */ 625 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 626 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 627 void (*set_timeout)(struct sdhci_host *host, 628 struct mmc_command *cmd); 629 void (*set_bus_width)(struct sdhci_host *host, int width); 630 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 631 u8 power_mode); 632 unsigned int (*get_ro)(struct sdhci_host *host); 633 void (*reset)(struct sdhci_host *host, u8 mask); 634 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 635 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 636 void (*hw_reset)(struct sdhci_host *host); 637 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 638 void (*card_event)(struct sdhci_host *host); 639 void (*voltage_switch)(struct sdhci_host *host); 640 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 641 dma_addr_t addr, int len, unsigned int cmd); 642 }; 643 644 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 645 646 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 647 { 648 if (unlikely(host->ops->write_l)) 649 host->ops->write_l(host, val, reg); 650 else 651 writel(val, host->ioaddr + reg); 652 } 653 654 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 655 { 656 if (unlikely(host->ops->write_w)) 657 host->ops->write_w(host, val, reg); 658 else 659 writew(val, host->ioaddr + reg); 660 } 661 662 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 663 { 664 if (unlikely(host->ops->write_b)) 665 host->ops->write_b(host, val, reg); 666 else 667 writeb(val, host->ioaddr + reg); 668 } 669 670 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 671 { 672 if (unlikely(host->ops->read_l)) 673 return host->ops->read_l(host, reg); 674 else 675 return readl(host->ioaddr + reg); 676 } 677 678 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 679 { 680 if (unlikely(host->ops->read_w)) 681 return host->ops->read_w(host, reg); 682 else 683 return readw(host->ioaddr + reg); 684 } 685 686 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 687 { 688 if (unlikely(host->ops->read_b)) 689 return host->ops->read_b(host, reg); 690 else 691 return readb(host->ioaddr + reg); 692 } 693 694 #else 695 696 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 697 { 698 writel(val, host->ioaddr + reg); 699 } 700 701 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 702 { 703 writew(val, host->ioaddr + reg); 704 } 705 706 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 707 { 708 writeb(val, host->ioaddr + reg); 709 } 710 711 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 712 { 713 return readl(host->ioaddr + reg); 714 } 715 716 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 717 { 718 return readw(host->ioaddr + reg); 719 } 720 721 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 722 { 723 return readb(host->ioaddr + reg); 724 } 725 726 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 727 728 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 729 void sdhci_free_host(struct sdhci_host *host); 730 731 static inline void *sdhci_priv(struct sdhci_host *host) 732 { 733 return host->private; 734 } 735 736 void sdhci_card_detect(struct sdhci_host *host); 737 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 738 u32 *caps1); 739 int sdhci_setup_host(struct sdhci_host *host); 740 void sdhci_cleanup_host(struct sdhci_host *host); 741 int __sdhci_add_host(struct sdhci_host *host); 742 int sdhci_add_host(struct sdhci_host *host); 743 void sdhci_remove_host(struct sdhci_host *host, int dead); 744 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 745 746 static inline void sdhci_read_caps(struct sdhci_host *host) 747 { 748 __sdhci_read_caps(host, NULL, NULL, NULL); 749 } 750 751 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 752 { 753 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 754 } 755 756 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 757 unsigned int *actual_clock); 758 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 759 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 760 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 761 unsigned short vdd); 762 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 763 unsigned short vdd); 764 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 765 void sdhci_set_bus_width(struct sdhci_host *host, int width); 766 void sdhci_reset(struct sdhci_host *host, u8 mask); 767 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 768 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 769 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 770 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 771 struct mmc_ios *ios); 772 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 773 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 774 dma_addr_t addr, int len, unsigned int cmd); 775 776 #ifdef CONFIG_PM 777 int sdhci_suspend_host(struct sdhci_host *host); 778 int sdhci_resume_host(struct sdhci_host *host); 779 int sdhci_runtime_suspend_host(struct sdhci_host *host); 780 int sdhci_runtime_resume_host(struct sdhci_host *host); 781 #endif 782 783 void sdhci_cqe_enable(struct mmc_host *mmc); 784 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 785 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 786 int *data_error); 787 788 void sdhci_dumpregs(struct sdhci_host *host); 789 void sdhci_enable_v4_mode(struct sdhci_host *host); 790 791 void sdhci_start_tuning(struct sdhci_host *host); 792 void sdhci_end_tuning(struct sdhci_host *host); 793 void sdhci_reset_tuning(struct sdhci_host *host); 794 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 795 796 #endif /* __SDHCI_HW_H */ 797