1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/highmem.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 17 #include <linux/mmc/host.h> 18 19 #include <asm/scatterlist.h> 20 21 #include "sdhci.h" 22 23 #define DRIVER_NAME "sdhci" 24 25 #define DBG(f, x...) \ 26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 27 28 static unsigned int debug_quirks = 0; 29 30 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 31 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 32 /* Controller doesn't like some resets when there is no card inserted. */ 33 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 34 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 35 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 36 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 37 38 static const struct pci_device_id pci_ids[] __devinitdata = { 39 { 40 .vendor = PCI_VENDOR_ID_RICOH, 41 .device = PCI_DEVICE_ID_RICOH_R5C822, 42 .subvendor = PCI_VENDOR_ID_IBM, 43 .subdevice = PCI_ANY_ID, 44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | 45 SDHCI_QUIRK_FORCE_DMA, 46 }, 47 48 { 49 .vendor = PCI_VENDOR_ID_RICOH, 50 .device = PCI_DEVICE_ID_RICOH_R5C822, 51 .subvendor = PCI_ANY_ID, 52 .subdevice = PCI_ANY_ID, 53 .driver_data = SDHCI_QUIRK_FORCE_DMA | 54 SDHCI_QUIRK_NO_CARD_NO_RESET, 55 }, 56 57 { 58 .vendor = PCI_VENDOR_ID_TI, 59 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, 60 .subvendor = PCI_ANY_ID, 61 .subdevice = PCI_ANY_ID, 62 .driver_data = SDHCI_QUIRK_FORCE_DMA, 63 }, 64 65 { 66 .vendor = PCI_VENDOR_ID_ENE, 67 .device = PCI_DEVICE_ID_ENE_CB712_SD, 68 .subvendor = PCI_ANY_ID, 69 .subdevice = PCI_ANY_ID, 70 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 71 SDHCI_QUIRK_BROKEN_DMA, 72 }, 73 74 { 75 .vendor = PCI_VENDOR_ID_ENE, 76 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 77 .subvendor = PCI_ANY_ID, 78 .subdevice = PCI_ANY_ID, 79 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 80 SDHCI_QUIRK_BROKEN_DMA, 81 }, 82 83 { 84 .vendor = PCI_VENDOR_ID_ENE, 85 .device = PCI_DEVICE_ID_ENE_CB714_SD, 86 .subvendor = PCI_ANY_ID, 87 .subdevice = PCI_ANY_ID, 88 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 89 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS, 90 }, 91 92 { 93 .vendor = PCI_VENDOR_ID_ENE, 94 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 95 .subvendor = PCI_ANY_ID, 96 .subdevice = PCI_ANY_ID, 97 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE | 98 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS, 99 }, 100 101 { /* Generic SD host controller */ 102 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 103 }, 104 105 { /* end: all zeroes */ }, 106 }; 107 108 MODULE_DEVICE_TABLE(pci, pci_ids); 109 110 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); 111 static void sdhci_finish_data(struct sdhci_host *); 112 113 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 114 static void sdhci_finish_command(struct sdhci_host *); 115 116 static void sdhci_dumpregs(struct sdhci_host *host) 117 { 118 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); 119 120 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 121 readl(host->ioaddr + SDHCI_DMA_ADDRESS), 122 readw(host->ioaddr + SDHCI_HOST_VERSION)); 123 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 124 readw(host->ioaddr + SDHCI_BLOCK_SIZE), 125 readw(host->ioaddr + SDHCI_BLOCK_COUNT)); 126 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 127 readl(host->ioaddr + SDHCI_ARGUMENT), 128 readw(host->ioaddr + SDHCI_TRANSFER_MODE)); 129 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 130 readl(host->ioaddr + SDHCI_PRESENT_STATE), 131 readb(host->ioaddr + SDHCI_HOST_CONTROL)); 132 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 133 readb(host->ioaddr + SDHCI_POWER_CONTROL), 134 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); 135 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 136 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL), 137 readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); 138 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 139 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), 140 readl(host->ioaddr + SDHCI_INT_STATUS)); 141 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 142 readl(host->ioaddr + SDHCI_INT_ENABLE), 143 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); 144 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 145 readw(host->ioaddr + SDHCI_ACMD12_ERR), 146 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); 147 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", 148 readl(host->ioaddr + SDHCI_CAPABILITIES), 149 readl(host->ioaddr + SDHCI_MAX_CURRENT)); 150 151 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); 152 } 153 154 /*****************************************************************************\ 155 * * 156 * Low level functions * 157 * * 158 \*****************************************************************************/ 159 160 static void sdhci_reset(struct sdhci_host *host, u8 mask) 161 { 162 unsigned long timeout; 163 164 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 165 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 166 SDHCI_CARD_PRESENT)) 167 return; 168 } 169 170 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); 171 172 if (mask & SDHCI_RESET_ALL) 173 host->clock = 0; 174 175 /* Wait max 100 ms */ 176 timeout = 100; 177 178 /* hw clears the bit when it's done */ 179 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { 180 if (timeout == 0) { 181 printk(KERN_ERR "%s: Reset 0x%x never completed.\n", 182 mmc_hostname(host->mmc), (int)mask); 183 sdhci_dumpregs(host); 184 return; 185 } 186 timeout--; 187 mdelay(1); 188 } 189 } 190 191 static void sdhci_init(struct sdhci_host *host) 192 { 193 u32 intmask; 194 195 sdhci_reset(host, SDHCI_RESET_ALL); 196 197 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 198 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 199 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 200 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 201 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 202 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; 203 204 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); 205 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); 206 } 207 208 static void sdhci_activate_led(struct sdhci_host *host) 209 { 210 u8 ctrl; 211 212 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 213 ctrl |= SDHCI_CTRL_LED; 214 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 215 } 216 217 static void sdhci_deactivate_led(struct sdhci_host *host) 218 { 219 u8 ctrl; 220 221 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 222 ctrl &= ~SDHCI_CTRL_LED; 223 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 224 } 225 226 /*****************************************************************************\ 227 * * 228 * Core functions * 229 * * 230 \*****************************************************************************/ 231 232 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host) 233 { 234 return page_address(host->cur_sg->page) + host->cur_sg->offset; 235 } 236 237 static inline int sdhci_next_sg(struct sdhci_host* host) 238 { 239 /* 240 * Skip to next SG entry. 241 */ 242 host->cur_sg++; 243 host->num_sg--; 244 245 /* 246 * Any entries left? 247 */ 248 if (host->num_sg > 0) { 249 host->offset = 0; 250 host->remain = host->cur_sg->length; 251 } 252 253 return host->num_sg; 254 } 255 256 static void sdhci_read_block_pio(struct sdhci_host *host) 257 { 258 int blksize, chunk_remain; 259 u32 data; 260 char *buffer; 261 int size; 262 263 DBG("PIO reading\n"); 264 265 blksize = host->data->blksz; 266 chunk_remain = 0; 267 data = 0; 268 269 buffer = sdhci_sg_to_buffer(host) + host->offset; 270 271 while (blksize) { 272 if (chunk_remain == 0) { 273 data = readl(host->ioaddr + SDHCI_BUFFER); 274 chunk_remain = min(blksize, 4); 275 } 276 277 size = min(host->remain, chunk_remain); 278 279 chunk_remain -= size; 280 blksize -= size; 281 host->offset += size; 282 host->remain -= size; 283 284 while (size) { 285 *buffer = data & 0xFF; 286 buffer++; 287 data >>= 8; 288 size--; 289 } 290 291 if (host->remain == 0) { 292 if (sdhci_next_sg(host) == 0) { 293 BUG_ON(blksize != 0); 294 return; 295 } 296 buffer = sdhci_sg_to_buffer(host); 297 } 298 } 299 } 300 301 static void sdhci_write_block_pio(struct sdhci_host *host) 302 { 303 int blksize, chunk_remain; 304 u32 data; 305 char *buffer; 306 int bytes, size; 307 308 DBG("PIO writing\n"); 309 310 blksize = host->data->blksz; 311 chunk_remain = 4; 312 data = 0; 313 314 bytes = 0; 315 buffer = sdhci_sg_to_buffer(host) + host->offset; 316 317 while (blksize) { 318 size = min(host->remain, chunk_remain); 319 320 chunk_remain -= size; 321 blksize -= size; 322 host->offset += size; 323 host->remain -= size; 324 325 while (size) { 326 data >>= 8; 327 data |= (u32)*buffer << 24; 328 buffer++; 329 size--; 330 } 331 332 if (chunk_remain == 0) { 333 writel(data, host->ioaddr + SDHCI_BUFFER); 334 chunk_remain = min(blksize, 4); 335 } 336 337 if (host->remain == 0) { 338 if (sdhci_next_sg(host) == 0) { 339 BUG_ON(blksize != 0); 340 return; 341 } 342 buffer = sdhci_sg_to_buffer(host); 343 } 344 } 345 } 346 347 static void sdhci_transfer_pio(struct sdhci_host *host) 348 { 349 u32 mask; 350 351 BUG_ON(!host->data); 352 353 if (host->num_sg == 0) 354 return; 355 356 if (host->data->flags & MMC_DATA_READ) 357 mask = SDHCI_DATA_AVAILABLE; 358 else 359 mask = SDHCI_SPACE_AVAILABLE; 360 361 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { 362 if (host->data->flags & MMC_DATA_READ) 363 sdhci_read_block_pio(host); 364 else 365 sdhci_write_block_pio(host); 366 367 if (host->num_sg == 0) 368 break; 369 } 370 371 DBG("PIO transfer complete.\n"); 372 } 373 374 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) 375 { 376 u8 count; 377 unsigned target_timeout, current_timeout; 378 379 WARN_ON(host->data); 380 381 if (data == NULL) 382 return; 383 384 /* Sanity checks */ 385 BUG_ON(data->blksz * data->blocks > 524288); 386 BUG_ON(data->blksz > host->mmc->max_blk_size); 387 BUG_ON(data->blocks > 65535); 388 389 host->data = data; 390 host->data_early = 0; 391 392 /* timeout in us */ 393 target_timeout = data->timeout_ns / 1000 + 394 data->timeout_clks / host->clock; 395 396 /* 397 * Figure out needed cycles. 398 * We do this in steps in order to fit inside a 32 bit int. 399 * The first step is the minimum timeout, which will have a 400 * minimum resolution of 6 bits: 401 * (1) 2^13*1000 > 2^22, 402 * (2) host->timeout_clk < 2^16 403 * => 404 * (1) / (2) > 2^6 405 */ 406 count = 0; 407 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 408 while (current_timeout < target_timeout) { 409 count++; 410 current_timeout <<= 1; 411 if (count >= 0xF) 412 break; 413 } 414 415 if (count >= 0xF) { 416 printk(KERN_WARNING "%s: Too large timeout requested!\n", 417 mmc_hostname(host->mmc)); 418 count = 0xE; 419 } 420 421 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); 422 423 if (host->flags & SDHCI_USE_DMA) { 424 int count; 425 426 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, 427 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); 428 BUG_ON(count != 1); 429 430 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); 431 } else { 432 host->cur_sg = data->sg; 433 host->num_sg = data->sg_len; 434 435 host->offset = 0; 436 host->remain = host->cur_sg->length; 437 } 438 439 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 440 writew(SDHCI_MAKE_BLKSZ(7, data->blksz), 441 host->ioaddr + SDHCI_BLOCK_SIZE); 442 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); 443 } 444 445 static void sdhci_set_transfer_mode(struct sdhci_host *host, 446 struct mmc_data *data) 447 { 448 u16 mode; 449 450 if (data == NULL) 451 return; 452 453 WARN_ON(!host->data); 454 455 mode = SDHCI_TRNS_BLK_CNT_EN; 456 if (data->blocks > 1) 457 mode |= SDHCI_TRNS_MULTI; 458 if (data->flags & MMC_DATA_READ) 459 mode |= SDHCI_TRNS_READ; 460 if (host->flags & SDHCI_USE_DMA) 461 mode |= SDHCI_TRNS_DMA; 462 463 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); 464 } 465 466 static void sdhci_finish_data(struct sdhci_host *host) 467 { 468 struct mmc_data *data; 469 u16 blocks; 470 471 BUG_ON(!host->data); 472 473 data = host->data; 474 host->data = NULL; 475 476 if (host->flags & SDHCI_USE_DMA) { 477 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, 478 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); 479 } 480 481 /* 482 * Controller doesn't count down when in single block mode. 483 */ 484 if (data->blocks == 1) 485 blocks = (data->error == 0) ? 0 : 1; 486 else 487 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); 488 data->bytes_xfered = data->blksz * (data->blocks - blocks); 489 490 if (!data->error && blocks) { 491 printk(KERN_ERR "%s: Controller signalled completion even " 492 "though there were blocks left.\n", 493 mmc_hostname(host->mmc)); 494 data->error = -EIO; 495 } 496 497 if (data->stop) { 498 /* 499 * The controller needs a reset of internal state machines 500 * upon error conditions. 501 */ 502 if (data->error) { 503 sdhci_reset(host, SDHCI_RESET_CMD); 504 sdhci_reset(host, SDHCI_RESET_DATA); 505 } 506 507 sdhci_send_command(host, data->stop); 508 } else 509 tasklet_schedule(&host->finish_tasklet); 510 } 511 512 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 513 { 514 int flags; 515 u32 mask; 516 unsigned long timeout; 517 518 WARN_ON(host->cmd); 519 520 /* Wait max 10 ms */ 521 timeout = 10; 522 523 mask = SDHCI_CMD_INHIBIT; 524 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 525 mask |= SDHCI_DATA_INHIBIT; 526 527 /* We shouldn't wait for data inihibit for stop commands, even 528 though they might use busy signaling */ 529 if (host->mrq->data && (cmd == host->mrq->data->stop)) 530 mask &= ~SDHCI_DATA_INHIBIT; 531 532 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { 533 if (timeout == 0) { 534 printk(KERN_ERR "%s: Controller never released " 535 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 536 sdhci_dumpregs(host); 537 cmd->error = -EIO; 538 tasklet_schedule(&host->finish_tasklet); 539 return; 540 } 541 timeout--; 542 mdelay(1); 543 } 544 545 mod_timer(&host->timer, jiffies + 10 * HZ); 546 547 host->cmd = cmd; 548 549 sdhci_prepare_data(host, cmd->data); 550 551 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); 552 553 sdhci_set_transfer_mode(host, cmd->data); 554 555 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 556 printk(KERN_ERR "%s: Unsupported response type!\n", 557 mmc_hostname(host->mmc)); 558 cmd->error = -EINVAL; 559 tasklet_schedule(&host->finish_tasklet); 560 return; 561 } 562 563 if (!(cmd->flags & MMC_RSP_PRESENT)) 564 flags = SDHCI_CMD_RESP_NONE; 565 else if (cmd->flags & MMC_RSP_136) 566 flags = SDHCI_CMD_RESP_LONG; 567 else if (cmd->flags & MMC_RSP_BUSY) 568 flags = SDHCI_CMD_RESP_SHORT_BUSY; 569 else 570 flags = SDHCI_CMD_RESP_SHORT; 571 572 if (cmd->flags & MMC_RSP_CRC) 573 flags |= SDHCI_CMD_CRC; 574 if (cmd->flags & MMC_RSP_OPCODE) 575 flags |= SDHCI_CMD_INDEX; 576 if (cmd->data) 577 flags |= SDHCI_CMD_DATA; 578 579 writew(SDHCI_MAKE_CMD(cmd->opcode, flags), 580 host->ioaddr + SDHCI_COMMAND); 581 } 582 583 static void sdhci_finish_command(struct sdhci_host *host) 584 { 585 int i; 586 587 BUG_ON(host->cmd == NULL); 588 589 if (host->cmd->flags & MMC_RSP_PRESENT) { 590 if (host->cmd->flags & MMC_RSP_136) { 591 /* CRC is stripped so we need to do some shifting. */ 592 for (i = 0;i < 4;i++) { 593 host->cmd->resp[i] = readl(host->ioaddr + 594 SDHCI_RESPONSE + (3-i)*4) << 8; 595 if (i != 3) 596 host->cmd->resp[i] |= 597 readb(host->ioaddr + 598 SDHCI_RESPONSE + (3-i)*4-1); 599 } 600 } else { 601 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); 602 } 603 } 604 605 host->cmd->error = 0; 606 607 if (host->data && host->data_early) 608 sdhci_finish_data(host); 609 610 if (!host->cmd->data) 611 tasklet_schedule(&host->finish_tasklet); 612 613 host->cmd = NULL; 614 } 615 616 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 617 { 618 int div; 619 u16 clk; 620 unsigned long timeout; 621 622 if (clock == host->clock) 623 return; 624 625 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 626 627 if (clock == 0) 628 goto out; 629 630 for (div = 1;div < 256;div *= 2) { 631 if ((host->max_clk / div) <= clock) 632 break; 633 } 634 div >>= 1; 635 636 clk = div << SDHCI_DIVIDER_SHIFT; 637 clk |= SDHCI_CLOCK_INT_EN; 638 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); 639 640 /* Wait max 10 ms */ 641 timeout = 10; 642 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) 643 & SDHCI_CLOCK_INT_STABLE)) { 644 if (timeout == 0) { 645 printk(KERN_ERR "%s: Internal clock never " 646 "stabilised.\n", mmc_hostname(host->mmc)); 647 sdhci_dumpregs(host); 648 return; 649 } 650 timeout--; 651 mdelay(1); 652 } 653 654 clk |= SDHCI_CLOCK_CARD_EN; 655 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); 656 657 out: 658 host->clock = clock; 659 } 660 661 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 662 { 663 u8 pwr; 664 665 if (host->power == power) 666 return; 667 668 if (power == (unsigned short)-1) { 669 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); 670 goto out; 671 } 672 673 /* 674 * Spec says that we should clear the power reg before setting 675 * a new value. Some controllers don't seem to like this though. 676 */ 677 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 678 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); 679 680 pwr = SDHCI_POWER_ON; 681 682 switch (1 << power) { 683 case MMC_VDD_165_195: 684 pwr |= SDHCI_POWER_180; 685 break; 686 case MMC_VDD_29_30: 687 case MMC_VDD_30_31: 688 pwr |= SDHCI_POWER_300; 689 break; 690 case MMC_VDD_32_33: 691 case MMC_VDD_33_34: 692 pwr |= SDHCI_POWER_330; 693 break; 694 default: 695 BUG(); 696 } 697 698 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); 699 700 out: 701 host->power = power; 702 } 703 704 /*****************************************************************************\ 705 * * 706 * MMC callbacks * 707 * * 708 \*****************************************************************************/ 709 710 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 711 { 712 struct sdhci_host *host; 713 unsigned long flags; 714 715 host = mmc_priv(mmc); 716 717 spin_lock_irqsave(&host->lock, flags); 718 719 WARN_ON(host->mrq != NULL); 720 721 sdhci_activate_led(host); 722 723 host->mrq = mrq; 724 725 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 726 host->mrq->cmd->error = -ENOMEDIUM; 727 tasklet_schedule(&host->finish_tasklet); 728 } else 729 sdhci_send_command(host, mrq->cmd); 730 731 mmiowb(); 732 spin_unlock_irqrestore(&host->lock, flags); 733 } 734 735 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 736 { 737 struct sdhci_host *host; 738 unsigned long flags; 739 u8 ctrl; 740 741 host = mmc_priv(mmc); 742 743 spin_lock_irqsave(&host->lock, flags); 744 745 /* 746 * Reset the chip on each power off. 747 * Should clear out any weird states. 748 */ 749 if (ios->power_mode == MMC_POWER_OFF) { 750 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); 751 sdhci_init(host); 752 } 753 754 sdhci_set_clock(host, ios->clock); 755 756 if (ios->power_mode == MMC_POWER_OFF) 757 sdhci_set_power(host, -1); 758 else 759 sdhci_set_power(host, ios->vdd); 760 761 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 762 763 if (ios->bus_width == MMC_BUS_WIDTH_4) 764 ctrl |= SDHCI_CTRL_4BITBUS; 765 else 766 ctrl &= ~SDHCI_CTRL_4BITBUS; 767 768 if (ios->timing == MMC_TIMING_SD_HS) 769 ctrl |= SDHCI_CTRL_HISPD; 770 else 771 ctrl &= ~SDHCI_CTRL_HISPD; 772 773 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 774 775 /* 776 * Some (ENE) controllers go apeshit on some ios operation, 777 * signalling timeout and CRC errors even on CMD0. Resetting 778 * it on each ios seems to solve the problem. 779 */ 780 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 781 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 782 783 mmiowb(); 784 spin_unlock_irqrestore(&host->lock, flags); 785 } 786 787 static int sdhci_get_ro(struct mmc_host *mmc) 788 { 789 struct sdhci_host *host; 790 unsigned long flags; 791 int present; 792 793 host = mmc_priv(mmc); 794 795 spin_lock_irqsave(&host->lock, flags); 796 797 present = readl(host->ioaddr + SDHCI_PRESENT_STATE); 798 799 spin_unlock_irqrestore(&host->lock, flags); 800 801 return !(present & SDHCI_WRITE_PROTECT); 802 } 803 804 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 805 { 806 struct sdhci_host *host; 807 unsigned long flags; 808 u32 ier; 809 810 host = mmc_priv(mmc); 811 812 spin_lock_irqsave(&host->lock, flags); 813 814 ier = readl(host->ioaddr + SDHCI_INT_ENABLE); 815 816 ier &= ~SDHCI_INT_CARD_INT; 817 if (enable) 818 ier |= SDHCI_INT_CARD_INT; 819 820 writel(ier, host->ioaddr + SDHCI_INT_ENABLE); 821 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); 822 823 mmiowb(); 824 825 spin_unlock_irqrestore(&host->lock, flags); 826 } 827 828 static const struct mmc_host_ops sdhci_ops = { 829 .request = sdhci_request, 830 .set_ios = sdhci_set_ios, 831 .get_ro = sdhci_get_ro, 832 .enable_sdio_irq = sdhci_enable_sdio_irq, 833 }; 834 835 /*****************************************************************************\ 836 * * 837 * Tasklets * 838 * * 839 \*****************************************************************************/ 840 841 static void sdhci_tasklet_card(unsigned long param) 842 { 843 struct sdhci_host *host; 844 unsigned long flags; 845 846 host = (struct sdhci_host*)param; 847 848 spin_lock_irqsave(&host->lock, flags); 849 850 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 851 if (host->mrq) { 852 printk(KERN_ERR "%s: Card removed during transfer!\n", 853 mmc_hostname(host->mmc)); 854 printk(KERN_ERR "%s: Resetting controller.\n", 855 mmc_hostname(host->mmc)); 856 857 sdhci_reset(host, SDHCI_RESET_CMD); 858 sdhci_reset(host, SDHCI_RESET_DATA); 859 860 host->mrq->cmd->error = -ENOMEDIUM; 861 tasklet_schedule(&host->finish_tasklet); 862 } 863 } 864 865 spin_unlock_irqrestore(&host->lock, flags); 866 867 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 868 } 869 870 static void sdhci_tasklet_finish(unsigned long param) 871 { 872 struct sdhci_host *host; 873 unsigned long flags; 874 struct mmc_request *mrq; 875 876 host = (struct sdhci_host*)param; 877 878 spin_lock_irqsave(&host->lock, flags); 879 880 del_timer(&host->timer); 881 882 mrq = host->mrq; 883 884 /* 885 * The controller needs a reset of internal state machines 886 * upon error conditions. 887 */ 888 if (mrq->cmd->error || 889 (mrq->data && (mrq->data->error || 890 (mrq->data->stop && mrq->data->stop->error)))) { 891 892 /* Some controllers need this kick or reset won't work here */ 893 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { 894 unsigned int clock; 895 896 /* This is to force an update */ 897 clock = host->clock; 898 host->clock = 0; 899 sdhci_set_clock(host, clock); 900 } 901 902 /* Spec says we should do both at the same time, but Ricoh 903 controllers do not like that. */ 904 sdhci_reset(host, SDHCI_RESET_CMD); 905 sdhci_reset(host, SDHCI_RESET_DATA); 906 } 907 908 host->mrq = NULL; 909 host->cmd = NULL; 910 host->data = NULL; 911 912 sdhci_deactivate_led(host); 913 914 mmiowb(); 915 spin_unlock_irqrestore(&host->lock, flags); 916 917 mmc_request_done(host->mmc, mrq); 918 } 919 920 static void sdhci_timeout_timer(unsigned long data) 921 { 922 struct sdhci_host *host; 923 unsigned long flags; 924 925 host = (struct sdhci_host*)data; 926 927 spin_lock_irqsave(&host->lock, flags); 928 929 if (host->mrq) { 930 printk(KERN_ERR "%s: Timeout waiting for hardware " 931 "interrupt.\n", mmc_hostname(host->mmc)); 932 sdhci_dumpregs(host); 933 934 if (host->data) { 935 host->data->error = -ETIMEDOUT; 936 sdhci_finish_data(host); 937 } else { 938 if (host->cmd) 939 host->cmd->error = -ETIMEDOUT; 940 else 941 host->mrq->cmd->error = -ETIMEDOUT; 942 943 tasklet_schedule(&host->finish_tasklet); 944 } 945 } 946 947 mmiowb(); 948 spin_unlock_irqrestore(&host->lock, flags); 949 } 950 951 /*****************************************************************************\ 952 * * 953 * Interrupt handling * 954 * * 955 \*****************************************************************************/ 956 957 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 958 { 959 BUG_ON(intmask == 0); 960 961 if (!host->cmd) { 962 printk(KERN_ERR "%s: Got command interrupt 0x%08x even " 963 "though no command operation was in progress.\n", 964 mmc_hostname(host->mmc), (unsigned)intmask); 965 sdhci_dumpregs(host); 966 return; 967 } 968 969 if (intmask & SDHCI_INT_TIMEOUT) 970 host->cmd->error = -ETIMEDOUT; 971 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 972 SDHCI_INT_INDEX)) 973 host->cmd->error = -EILSEQ; 974 975 if (host->cmd->error) 976 tasklet_schedule(&host->finish_tasklet); 977 else if (intmask & SDHCI_INT_RESPONSE) 978 sdhci_finish_command(host); 979 } 980 981 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 982 { 983 BUG_ON(intmask == 0); 984 985 if (!host->data) { 986 /* 987 * A data end interrupt is sent together with the response 988 * for the stop command. 989 */ 990 if (intmask & SDHCI_INT_DATA_END) 991 return; 992 993 printk(KERN_ERR "%s: Got data interrupt 0x%08x even " 994 "though no data operation was in progress.\n", 995 mmc_hostname(host->mmc), (unsigned)intmask); 996 sdhci_dumpregs(host); 997 998 return; 999 } 1000 1001 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1002 host->data->error = -ETIMEDOUT; 1003 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1004 host->data->error = -EILSEQ; 1005 1006 if (host->data->error) 1007 sdhci_finish_data(host); 1008 else { 1009 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1010 sdhci_transfer_pio(host); 1011 1012 /* 1013 * We currently don't do anything fancy with DMA 1014 * boundaries, but as we can't disable the feature 1015 * we need to at least restart the transfer. 1016 */ 1017 if (intmask & SDHCI_INT_DMA_END) 1018 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), 1019 host->ioaddr + SDHCI_DMA_ADDRESS); 1020 1021 if (intmask & SDHCI_INT_DATA_END) { 1022 if (host->cmd) { 1023 /* 1024 * Data managed to finish before the 1025 * command completed. Make sure we do 1026 * things in the proper order. 1027 */ 1028 host->data_early = 1; 1029 } else { 1030 sdhci_finish_data(host); 1031 } 1032 } 1033 } 1034 } 1035 1036 static irqreturn_t sdhci_irq(int irq, void *dev_id) 1037 { 1038 irqreturn_t result; 1039 struct sdhci_host* host = dev_id; 1040 u32 intmask; 1041 int cardint = 0; 1042 1043 spin_lock(&host->lock); 1044 1045 intmask = readl(host->ioaddr + SDHCI_INT_STATUS); 1046 1047 if (!intmask || intmask == 0xffffffff) { 1048 result = IRQ_NONE; 1049 goto out; 1050 } 1051 1052 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); 1053 1054 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1055 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), 1056 host->ioaddr + SDHCI_INT_STATUS); 1057 tasklet_schedule(&host->card_tasklet); 1058 } 1059 1060 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1061 1062 if (intmask & SDHCI_INT_CMD_MASK) { 1063 writel(intmask & SDHCI_INT_CMD_MASK, 1064 host->ioaddr + SDHCI_INT_STATUS); 1065 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 1066 } 1067 1068 if (intmask & SDHCI_INT_DATA_MASK) { 1069 writel(intmask & SDHCI_INT_DATA_MASK, 1070 host->ioaddr + SDHCI_INT_STATUS); 1071 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 1072 } 1073 1074 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1075 1076 intmask &= ~SDHCI_INT_ERROR; 1077 1078 if (intmask & SDHCI_INT_BUS_POWER) { 1079 printk(KERN_ERR "%s: Card is consuming too much power!\n", 1080 mmc_hostname(host->mmc)); 1081 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); 1082 } 1083 1084 intmask &= ~SDHCI_INT_BUS_POWER; 1085 1086 if (intmask & SDHCI_INT_CARD_INT) 1087 cardint = 1; 1088 1089 intmask &= ~SDHCI_INT_CARD_INT; 1090 1091 if (intmask) { 1092 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", 1093 mmc_hostname(host->mmc), intmask); 1094 sdhci_dumpregs(host); 1095 1096 writel(intmask, host->ioaddr + SDHCI_INT_STATUS); 1097 } 1098 1099 result = IRQ_HANDLED; 1100 1101 mmiowb(); 1102 out: 1103 spin_unlock(&host->lock); 1104 1105 /* 1106 * We have to delay this as it calls back into the driver. 1107 */ 1108 if (cardint) 1109 mmc_signal_sdio_irq(host->mmc); 1110 1111 return result; 1112 } 1113 1114 /*****************************************************************************\ 1115 * * 1116 * Suspend/resume * 1117 * * 1118 \*****************************************************************************/ 1119 1120 #ifdef CONFIG_PM 1121 1122 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) 1123 { 1124 struct sdhci_chip *chip; 1125 int i, ret; 1126 1127 chip = pci_get_drvdata(pdev); 1128 if (!chip) 1129 return 0; 1130 1131 DBG("Suspending...\n"); 1132 1133 for (i = 0;i < chip->num_slots;i++) { 1134 if (!chip->hosts[i]) 1135 continue; 1136 ret = mmc_suspend_host(chip->hosts[i]->mmc, state); 1137 if (ret) { 1138 for (i--;i >= 0;i--) 1139 mmc_resume_host(chip->hosts[i]->mmc); 1140 return ret; 1141 } 1142 } 1143 1144 pci_save_state(pdev); 1145 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1146 1147 for (i = 0;i < chip->num_slots;i++) { 1148 if (!chip->hosts[i]) 1149 continue; 1150 free_irq(chip->hosts[i]->irq, chip->hosts[i]); 1151 } 1152 1153 pci_disable_device(pdev); 1154 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1155 1156 return 0; 1157 } 1158 1159 static int sdhci_resume (struct pci_dev *pdev) 1160 { 1161 struct sdhci_chip *chip; 1162 int i, ret; 1163 1164 chip = pci_get_drvdata(pdev); 1165 if (!chip) 1166 return 0; 1167 1168 DBG("Resuming...\n"); 1169 1170 pci_set_power_state(pdev, PCI_D0); 1171 pci_restore_state(pdev); 1172 ret = pci_enable_device(pdev); 1173 if (ret) 1174 return ret; 1175 1176 for (i = 0;i < chip->num_slots;i++) { 1177 if (!chip->hosts[i]) 1178 continue; 1179 if (chip->hosts[i]->flags & SDHCI_USE_DMA) 1180 pci_set_master(pdev); 1181 ret = request_irq(chip->hosts[i]->irq, sdhci_irq, 1182 IRQF_SHARED, chip->hosts[i]->slot_descr, 1183 chip->hosts[i]); 1184 if (ret) 1185 return ret; 1186 sdhci_init(chip->hosts[i]); 1187 mmiowb(); 1188 ret = mmc_resume_host(chip->hosts[i]->mmc); 1189 if (ret) 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 1196 #else /* CONFIG_PM */ 1197 1198 #define sdhci_suspend NULL 1199 #define sdhci_resume NULL 1200 1201 #endif /* CONFIG_PM */ 1202 1203 /*****************************************************************************\ 1204 * * 1205 * Device probing/removal * 1206 * * 1207 \*****************************************************************************/ 1208 1209 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) 1210 { 1211 int ret; 1212 unsigned int version; 1213 struct sdhci_chip *chip; 1214 struct mmc_host *mmc; 1215 struct sdhci_host *host; 1216 1217 u8 first_bar; 1218 unsigned int caps; 1219 1220 chip = pci_get_drvdata(pdev); 1221 BUG_ON(!chip); 1222 1223 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1224 if (ret) 1225 return ret; 1226 1227 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1228 1229 if (first_bar > 5) { 1230 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); 1231 return -ENODEV; 1232 } 1233 1234 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { 1235 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); 1236 return -ENODEV; 1237 } 1238 1239 if (pci_resource_len(pdev, first_bar + slot) != 0x100) { 1240 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. " 1241 "You may experience problems.\n"); 1242 } 1243 1244 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1245 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); 1246 return -ENODEV; 1247 } 1248 1249 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1250 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); 1251 return -ENODEV; 1252 } 1253 1254 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); 1255 if (!mmc) 1256 return -ENOMEM; 1257 1258 host = mmc_priv(mmc); 1259 host->mmc = mmc; 1260 1261 host->chip = chip; 1262 chip->hosts[slot] = host; 1263 1264 host->bar = first_bar + slot; 1265 1266 host->addr = pci_resource_start(pdev, host->bar); 1267 host->irq = pdev->irq; 1268 1269 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); 1270 1271 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot); 1272 1273 ret = pci_request_region(pdev, host->bar, host->slot_descr); 1274 if (ret) 1275 goto free; 1276 1277 host->ioaddr = ioremap_nocache(host->addr, 1278 pci_resource_len(pdev, host->bar)); 1279 if (!host->ioaddr) { 1280 ret = -ENOMEM; 1281 goto release; 1282 } 1283 1284 sdhci_reset(host, SDHCI_RESET_ALL); 1285 1286 version = readw(host->ioaddr + SDHCI_HOST_VERSION); 1287 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 1288 if (version != 0) { 1289 printk(KERN_ERR "%s: Unknown controller version (%d). " 1290 "You may experience problems.\n", host->slot_descr, 1291 version); 1292 } 1293 1294 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); 1295 1296 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) 1297 host->flags |= SDHCI_USE_DMA; 1298 else if (!(caps & SDHCI_CAN_DO_DMA)) 1299 DBG("Controller doesn't have DMA capability\n"); 1300 else 1301 host->flags |= SDHCI_USE_DMA; 1302 1303 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) && 1304 (host->flags & SDHCI_USE_DMA)) { 1305 DBG("Disabling DMA as it is marked broken"); 1306 host->flags &= ~SDHCI_USE_DMA; 1307 } 1308 1309 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1310 (host->flags & SDHCI_USE_DMA)) { 1311 printk(KERN_WARNING "%s: Will use DMA " 1312 "mode even though HW doesn't fully " 1313 "claim to support it.\n", host->slot_descr); 1314 } 1315 1316 if (host->flags & SDHCI_USE_DMA) { 1317 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { 1318 printk(KERN_WARNING "%s: No suitable DMA available. " 1319 "Falling back to PIO.\n", host->slot_descr); 1320 host->flags &= ~SDHCI_USE_DMA; 1321 } 1322 } 1323 1324 if (host->flags & SDHCI_USE_DMA) 1325 pci_set_master(pdev); 1326 else /* XXX: Hack to get MMC layer to avoid highmem */ 1327 pdev->dma_mask = 0; 1328 1329 host->max_clk = 1330 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 1331 if (host->max_clk == 0) { 1332 printk(KERN_ERR "%s: Hardware doesn't specify base clock " 1333 "frequency.\n", host->slot_descr); 1334 ret = -ENODEV; 1335 goto unmap; 1336 } 1337 host->max_clk *= 1000000; 1338 1339 host->timeout_clk = 1340 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 1341 if (host->timeout_clk == 0) { 1342 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " 1343 "frequency.\n", host->slot_descr); 1344 ret = -ENODEV; 1345 goto unmap; 1346 } 1347 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 1348 host->timeout_clk *= 1000; 1349 1350 /* 1351 * Set host parameters. 1352 */ 1353 mmc->ops = &sdhci_ops; 1354 mmc->f_min = host->max_clk / 256; 1355 mmc->f_max = host->max_clk; 1356 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ; 1357 1358 if (caps & SDHCI_CAN_DO_HISPD) 1359 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1360 1361 mmc->ocr_avail = 0; 1362 if (caps & SDHCI_CAN_VDD_330) 1363 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; 1364 if (caps & SDHCI_CAN_VDD_300) 1365 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; 1366 if (caps & SDHCI_CAN_VDD_180) 1367 mmc->ocr_avail |= MMC_VDD_165_195; 1368 1369 if (mmc->ocr_avail == 0) { 1370 printk(KERN_ERR "%s: Hardware doesn't report any " 1371 "support voltages.\n", host->slot_descr); 1372 ret = -ENODEV; 1373 goto unmap; 1374 } 1375 1376 spin_lock_init(&host->lock); 1377 1378 /* 1379 * Maximum number of segments. Hardware cannot do scatter lists. 1380 */ 1381 if (host->flags & SDHCI_USE_DMA) 1382 mmc->max_hw_segs = 1; 1383 else 1384 mmc->max_hw_segs = 16; 1385 mmc->max_phys_segs = 16; 1386 1387 /* 1388 * Maximum number of sectors in one transfer. Limited by DMA boundary 1389 * size (512KiB). 1390 */ 1391 mmc->max_req_size = 524288; 1392 1393 /* 1394 * Maximum segment size. Could be one segment with the maximum number 1395 * of bytes. 1396 */ 1397 mmc->max_seg_size = mmc->max_req_size; 1398 1399 /* 1400 * Maximum block size. This varies from controller to controller and 1401 * is specified in the capabilities register. 1402 */ 1403 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; 1404 if (mmc->max_blk_size >= 3) { 1405 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n", 1406 host->slot_descr); 1407 mmc->max_blk_size = 512; 1408 } else 1409 mmc->max_blk_size = 512 << mmc->max_blk_size; 1410 1411 /* 1412 * Maximum block count. 1413 */ 1414 mmc->max_blk_count = 65535; 1415 1416 /* 1417 * Init tasklets. 1418 */ 1419 tasklet_init(&host->card_tasklet, 1420 sdhci_tasklet_card, (unsigned long)host); 1421 tasklet_init(&host->finish_tasklet, 1422 sdhci_tasklet_finish, (unsigned long)host); 1423 1424 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 1425 1426 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 1427 host->slot_descr, host); 1428 if (ret) 1429 goto untasklet; 1430 1431 sdhci_init(host); 1432 1433 #ifdef CONFIG_MMC_DEBUG 1434 sdhci_dumpregs(host); 1435 #endif 1436 1437 mmiowb(); 1438 1439 mmc_add_host(mmc); 1440 1441 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc), 1442 host->addr, host->irq, 1443 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); 1444 1445 return 0; 1446 1447 untasklet: 1448 tasklet_kill(&host->card_tasklet); 1449 tasklet_kill(&host->finish_tasklet); 1450 unmap: 1451 iounmap(host->ioaddr); 1452 release: 1453 pci_release_region(pdev, host->bar); 1454 free: 1455 mmc_free_host(mmc); 1456 1457 return ret; 1458 } 1459 1460 static void sdhci_remove_slot(struct pci_dev *pdev, int slot) 1461 { 1462 struct sdhci_chip *chip; 1463 struct mmc_host *mmc; 1464 struct sdhci_host *host; 1465 1466 chip = pci_get_drvdata(pdev); 1467 host = chip->hosts[slot]; 1468 mmc = host->mmc; 1469 1470 chip->hosts[slot] = NULL; 1471 1472 mmc_remove_host(mmc); 1473 1474 sdhci_reset(host, SDHCI_RESET_ALL); 1475 1476 free_irq(host->irq, host); 1477 1478 del_timer_sync(&host->timer); 1479 1480 tasklet_kill(&host->card_tasklet); 1481 tasklet_kill(&host->finish_tasklet); 1482 1483 iounmap(host->ioaddr); 1484 1485 pci_release_region(pdev, host->bar); 1486 1487 mmc_free_host(mmc); 1488 } 1489 1490 static int __devinit sdhci_probe(struct pci_dev *pdev, 1491 const struct pci_device_id *ent) 1492 { 1493 int ret, i; 1494 u8 slots, rev; 1495 struct sdhci_chip *chip; 1496 1497 BUG_ON(pdev == NULL); 1498 BUG_ON(ent == NULL); 1499 1500 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); 1501 1502 printk(KERN_INFO DRIVER_NAME 1503 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", 1504 pci_name(pdev), (int)pdev->vendor, (int)pdev->device, 1505 (int)rev); 1506 1507 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1508 if (ret) 1509 return ret; 1510 1511 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1512 DBG("found %d slot(s)\n", slots); 1513 if (slots == 0) 1514 return -ENODEV; 1515 1516 ret = pci_enable_device(pdev); 1517 if (ret) 1518 return ret; 1519 1520 chip = kzalloc(sizeof(struct sdhci_chip) + 1521 sizeof(struct sdhci_host*) * slots, GFP_KERNEL); 1522 if (!chip) { 1523 ret = -ENOMEM; 1524 goto err; 1525 } 1526 1527 chip->pdev = pdev; 1528 chip->quirks = ent->driver_data; 1529 1530 if (debug_quirks) 1531 chip->quirks = debug_quirks; 1532 1533 chip->num_slots = slots; 1534 pci_set_drvdata(pdev, chip); 1535 1536 for (i = 0;i < slots;i++) { 1537 ret = sdhci_probe_slot(pdev, i); 1538 if (ret) { 1539 for (i--;i >= 0;i--) 1540 sdhci_remove_slot(pdev, i); 1541 goto free; 1542 } 1543 } 1544 1545 return 0; 1546 1547 free: 1548 pci_set_drvdata(pdev, NULL); 1549 kfree(chip); 1550 1551 err: 1552 pci_disable_device(pdev); 1553 return ret; 1554 } 1555 1556 static void __devexit sdhci_remove(struct pci_dev *pdev) 1557 { 1558 int i; 1559 struct sdhci_chip *chip; 1560 1561 chip = pci_get_drvdata(pdev); 1562 1563 if (chip) { 1564 for (i = 0;i < chip->num_slots;i++) 1565 sdhci_remove_slot(pdev, i); 1566 1567 pci_set_drvdata(pdev, NULL); 1568 1569 kfree(chip); 1570 } 1571 1572 pci_disable_device(pdev); 1573 } 1574 1575 static struct pci_driver sdhci_driver = { 1576 .name = DRIVER_NAME, 1577 .id_table = pci_ids, 1578 .probe = sdhci_probe, 1579 .remove = __devexit_p(sdhci_remove), 1580 .suspend = sdhci_suspend, 1581 .resume = sdhci_resume, 1582 }; 1583 1584 /*****************************************************************************\ 1585 * * 1586 * Driver init/exit * 1587 * * 1588 \*****************************************************************************/ 1589 1590 static int __init sdhci_drv_init(void) 1591 { 1592 printk(KERN_INFO DRIVER_NAME 1593 ": Secure Digital Host Controller Interface driver\n"); 1594 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 1595 1596 return pci_register_driver(&sdhci_driver); 1597 } 1598 1599 static void __exit sdhci_drv_exit(void) 1600 { 1601 DBG("Exiting\n"); 1602 1603 pci_unregister_driver(&sdhci_driver); 1604 } 1605 1606 module_init(sdhci_drv_init); 1607 module_exit(sdhci_drv_exit); 1608 1609 module_param(debug_quirks, uint, 0444); 1610 1611 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); 1612 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); 1613 MODULE_LICENSE("GPL"); 1614 1615 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 1616