1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 31 #include "sdhci.h" 32 33 #define DRIVER_NAME "sdhci" 34 35 #define DBG(f, x...) \ 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 37 38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 39 defined(CONFIG_MMC_SDHCI_MODULE)) 40 #define SDHCI_USE_LEDS_CLASS 41 #endif 42 43 #define MAX_TUNING_LOOP 40 44 45 static unsigned int debug_quirks = 0; 46 static unsigned int debug_quirks2; 47 48 static void sdhci_finish_data(struct sdhci_host *); 49 50 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 51 static void sdhci_finish_command(struct sdhci_host *); 52 static int sdhci_execute_tuning(struct mmc_host *mmc); 53 static void sdhci_tuning_timer(unsigned long data); 54 55 #ifdef CONFIG_PM_RUNTIME 56 static int sdhci_runtime_pm_get(struct sdhci_host *host); 57 static int sdhci_runtime_pm_put(struct sdhci_host *host); 58 #else 59 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 60 { 61 return 0; 62 } 63 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 64 { 65 return 0; 66 } 67 #endif 68 69 static void sdhci_dumpregs(struct sdhci_host *host) 70 { 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 72 mmc_hostname(host->mmc)); 73 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 75 sdhci_readl(host, SDHCI_DMA_ADDRESS), 76 sdhci_readw(host, SDHCI_HOST_VERSION)); 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 78 sdhci_readw(host, SDHCI_BLOCK_SIZE), 79 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 81 sdhci_readl(host, SDHCI_ARGUMENT), 82 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 84 sdhci_readl(host, SDHCI_PRESENT_STATE), 85 sdhci_readb(host, SDHCI_HOST_CONTROL)); 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 87 sdhci_readb(host, SDHCI_POWER_CONTROL), 88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 91 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 94 sdhci_readl(host, SDHCI_INT_STATUS)); 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 96 sdhci_readl(host, SDHCI_INT_ENABLE), 97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 99 sdhci_readw(host, SDHCI_ACMD12_ERR), 100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 102 sdhci_readl(host, SDHCI_CAPABILITIES), 103 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 105 sdhci_readw(host, SDHCI_COMMAND), 106 sdhci_readl(host, SDHCI_MAX_CURRENT)); 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 108 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 109 110 if (host->flags & SDHCI_USE_ADMA) 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 112 readl(host->ioaddr + SDHCI_ADMA_ERROR), 113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 114 115 pr_debug(DRIVER_NAME ": ===========================================\n"); 116 } 117 118 /*****************************************************************************\ 119 * * 120 * Low level functions * 121 * * 122 \*****************************************************************************/ 123 124 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 125 { 126 u32 ier; 127 128 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 129 ier &= ~clear; 130 ier |= set; 131 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 133 } 134 135 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 136 { 137 sdhci_clear_set_irqs(host, 0, irqs); 138 } 139 140 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 141 { 142 sdhci_clear_set_irqs(host, irqs, 0); 143 } 144 145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 146 { 147 u32 present, irqs; 148 149 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 150 return; 151 152 if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION) 153 return; 154 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 156 SDHCI_CARD_PRESENT; 157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 158 159 if (enable) 160 sdhci_unmask_irqs(host, irqs); 161 else 162 sdhci_mask_irqs(host, irqs); 163 } 164 165 static void sdhci_enable_card_detection(struct sdhci_host *host) 166 { 167 sdhci_set_card_detection(host, true); 168 } 169 170 static void sdhci_disable_card_detection(struct sdhci_host *host) 171 { 172 sdhci_set_card_detection(host, false); 173 } 174 175 static void sdhci_reset(struct sdhci_host *host, u8 mask) 176 { 177 unsigned long timeout; 178 u32 uninitialized_var(ier); 179 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 182 SDHCI_CARD_PRESENT)) 183 return; 184 } 185 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 187 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 188 189 if (host->ops->platform_reset_enter) 190 host->ops->platform_reset_enter(host, mask); 191 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 193 194 if (mask & SDHCI_RESET_ALL) 195 host->clock = 0; 196 197 /* Wait max 100 ms */ 198 timeout = 100; 199 200 /* hw clears the bit when it's done */ 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 202 if (timeout == 0) { 203 pr_err("%s: Reset 0x%x never completed.\n", 204 mmc_hostname(host->mmc), (int)mask); 205 sdhci_dumpregs(host); 206 return; 207 } 208 timeout--; 209 mdelay(1); 210 } 211 212 if (host->ops->platform_reset_exit) 213 host->ops->platform_reset_exit(host, mask); 214 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 217 } 218 219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 220 221 static void sdhci_init(struct sdhci_host *host, int soft) 222 { 223 if (soft) 224 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 225 else 226 sdhci_reset(host, SDHCI_RESET_ALL); 227 228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 229 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 230 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 231 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 232 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 233 234 if (soft) { 235 /* force clock reconfiguration */ 236 host->clock = 0; 237 sdhci_set_ios(host->mmc, &host->mmc->ios); 238 } 239 } 240 241 static void sdhci_reinit(struct sdhci_host *host) 242 { 243 sdhci_init(host, 0); 244 sdhci_enable_card_detection(host); 245 } 246 247 static void sdhci_activate_led(struct sdhci_host *host) 248 { 249 u8 ctrl; 250 251 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 252 ctrl |= SDHCI_CTRL_LED; 253 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 254 } 255 256 static void sdhci_deactivate_led(struct sdhci_host *host) 257 { 258 u8 ctrl; 259 260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 261 ctrl &= ~SDHCI_CTRL_LED; 262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 263 } 264 265 #ifdef SDHCI_USE_LEDS_CLASS 266 static void sdhci_led_control(struct led_classdev *led, 267 enum led_brightness brightness) 268 { 269 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 270 unsigned long flags; 271 272 spin_lock_irqsave(&host->lock, flags); 273 274 if (host->runtime_suspended) 275 goto out; 276 277 if (brightness == LED_OFF) 278 sdhci_deactivate_led(host); 279 else 280 sdhci_activate_led(host); 281 out: 282 spin_unlock_irqrestore(&host->lock, flags); 283 } 284 #endif 285 286 /*****************************************************************************\ 287 * * 288 * Core functions * 289 * * 290 \*****************************************************************************/ 291 292 static void sdhci_read_block_pio(struct sdhci_host *host) 293 { 294 unsigned long flags; 295 size_t blksize, len, chunk; 296 u32 uninitialized_var(scratch); 297 u8 *buf; 298 299 DBG("PIO reading\n"); 300 301 blksize = host->data->blksz; 302 chunk = 0; 303 304 local_irq_save(flags); 305 306 while (blksize) { 307 if (!sg_miter_next(&host->sg_miter)) 308 BUG(); 309 310 len = min(host->sg_miter.length, blksize); 311 312 blksize -= len; 313 host->sg_miter.consumed = len; 314 315 buf = host->sg_miter.addr; 316 317 while (len) { 318 if (chunk == 0) { 319 scratch = sdhci_readl(host, SDHCI_BUFFER); 320 chunk = 4; 321 } 322 323 *buf = scratch & 0xFF; 324 325 buf++; 326 scratch >>= 8; 327 chunk--; 328 len--; 329 } 330 } 331 332 sg_miter_stop(&host->sg_miter); 333 334 local_irq_restore(flags); 335 } 336 337 static void sdhci_write_block_pio(struct sdhci_host *host) 338 { 339 unsigned long flags; 340 size_t blksize, len, chunk; 341 u32 scratch; 342 u8 *buf; 343 344 DBG("PIO writing\n"); 345 346 blksize = host->data->blksz; 347 chunk = 0; 348 scratch = 0; 349 350 local_irq_save(flags); 351 352 while (blksize) { 353 if (!sg_miter_next(&host->sg_miter)) 354 BUG(); 355 356 len = min(host->sg_miter.length, blksize); 357 358 blksize -= len; 359 host->sg_miter.consumed = len; 360 361 buf = host->sg_miter.addr; 362 363 while (len) { 364 scratch |= (u32)*buf << (chunk * 8); 365 366 buf++; 367 chunk++; 368 len--; 369 370 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 371 sdhci_writel(host, scratch, SDHCI_BUFFER); 372 chunk = 0; 373 scratch = 0; 374 } 375 } 376 } 377 378 sg_miter_stop(&host->sg_miter); 379 380 local_irq_restore(flags); 381 } 382 383 static void sdhci_transfer_pio(struct sdhci_host *host) 384 { 385 u32 mask; 386 387 BUG_ON(!host->data); 388 389 if (host->blocks == 0) 390 return; 391 392 if (host->data->flags & MMC_DATA_READ) 393 mask = SDHCI_DATA_AVAILABLE; 394 else 395 mask = SDHCI_SPACE_AVAILABLE; 396 397 /* 398 * Some controllers (JMicron JMB38x) mess up the buffer bits 399 * for transfers < 4 bytes. As long as it is just one block, 400 * we can ignore the bits. 401 */ 402 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 403 (host->data->blocks == 1)) 404 mask = ~0; 405 406 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 407 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 408 udelay(100); 409 410 if (host->data->flags & MMC_DATA_READ) 411 sdhci_read_block_pio(host); 412 else 413 sdhci_write_block_pio(host); 414 415 host->blocks--; 416 if (host->blocks == 0) 417 break; 418 } 419 420 DBG("PIO transfer complete.\n"); 421 } 422 423 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 424 { 425 local_irq_save(*flags); 426 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 427 } 428 429 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 430 { 431 kunmap_atomic(buffer, KM_BIO_SRC_IRQ); 432 local_irq_restore(*flags); 433 } 434 435 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 436 { 437 __le32 *dataddr = (__le32 __force *)(desc + 4); 438 __le16 *cmdlen = (__le16 __force *)desc; 439 440 /* SDHCI specification says ADMA descriptors should be 4 byte 441 * aligned, so using 16 or 32bit operations should be safe. */ 442 443 cmdlen[0] = cpu_to_le16(cmd); 444 cmdlen[1] = cpu_to_le16(len); 445 446 dataddr[0] = cpu_to_le32(addr); 447 } 448 449 static int sdhci_adma_table_pre(struct sdhci_host *host, 450 struct mmc_data *data) 451 { 452 int direction; 453 454 u8 *desc; 455 u8 *align; 456 dma_addr_t addr; 457 dma_addr_t align_addr; 458 int len, offset; 459 460 struct scatterlist *sg; 461 int i; 462 char *buffer; 463 unsigned long flags; 464 465 /* 466 * The spec does not specify endianness of descriptor table. 467 * We currently guess that it is LE. 468 */ 469 470 if (data->flags & MMC_DATA_READ) 471 direction = DMA_FROM_DEVICE; 472 else 473 direction = DMA_TO_DEVICE; 474 475 /* 476 * The ADMA descriptor table is mapped further down as we 477 * need to fill it with data first. 478 */ 479 480 host->align_addr = dma_map_single(mmc_dev(host->mmc), 481 host->align_buffer, 128 * 4, direction); 482 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 483 goto fail; 484 BUG_ON(host->align_addr & 0x3); 485 486 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 487 data->sg, data->sg_len, direction); 488 if (host->sg_count == 0) 489 goto unmap_align; 490 491 desc = host->adma_desc; 492 align = host->align_buffer; 493 494 align_addr = host->align_addr; 495 496 for_each_sg(data->sg, sg, host->sg_count, i) { 497 addr = sg_dma_address(sg); 498 len = sg_dma_len(sg); 499 500 /* 501 * The SDHCI specification states that ADMA 502 * addresses must be 32-bit aligned. If they 503 * aren't, then we use a bounce buffer for 504 * the (up to three) bytes that screw up the 505 * alignment. 506 */ 507 offset = (4 - (addr & 0x3)) & 0x3; 508 if (offset) { 509 if (data->flags & MMC_DATA_WRITE) { 510 buffer = sdhci_kmap_atomic(sg, &flags); 511 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 512 memcpy(align, buffer, offset); 513 sdhci_kunmap_atomic(buffer, &flags); 514 } 515 516 /* tran, valid */ 517 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 518 519 BUG_ON(offset > 65536); 520 521 align += 4; 522 align_addr += 4; 523 524 desc += 8; 525 526 addr += offset; 527 len -= offset; 528 } 529 530 BUG_ON(len > 65536); 531 532 /* tran, valid */ 533 sdhci_set_adma_desc(desc, addr, len, 0x21); 534 desc += 8; 535 536 /* 537 * If this triggers then we have a calculation bug 538 * somewhere. :/ 539 */ 540 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 541 } 542 543 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 544 /* 545 * Mark the last descriptor as the terminating descriptor 546 */ 547 if (desc != host->adma_desc) { 548 desc -= 8; 549 desc[0] |= 0x2; /* end */ 550 } 551 } else { 552 /* 553 * Add a terminating entry. 554 */ 555 556 /* nop, end, valid */ 557 sdhci_set_adma_desc(desc, 0, 0, 0x3); 558 } 559 560 /* 561 * Resync align buffer as we might have changed it. 562 */ 563 if (data->flags & MMC_DATA_WRITE) { 564 dma_sync_single_for_device(mmc_dev(host->mmc), 565 host->align_addr, 128 * 4, direction); 566 } 567 568 host->adma_addr = dma_map_single(mmc_dev(host->mmc), 569 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 570 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 571 goto unmap_entries; 572 BUG_ON(host->adma_addr & 0x3); 573 574 return 0; 575 576 unmap_entries: 577 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 578 data->sg_len, direction); 579 unmap_align: 580 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 581 128 * 4, direction); 582 fail: 583 return -EINVAL; 584 } 585 586 static void sdhci_adma_table_post(struct sdhci_host *host, 587 struct mmc_data *data) 588 { 589 int direction; 590 591 struct scatterlist *sg; 592 int i, size; 593 u8 *align; 594 char *buffer; 595 unsigned long flags; 596 597 if (data->flags & MMC_DATA_READ) 598 direction = DMA_FROM_DEVICE; 599 else 600 direction = DMA_TO_DEVICE; 601 602 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 603 (128 * 2 + 1) * 4, DMA_TO_DEVICE); 604 605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 606 128 * 4, direction); 607 608 if (data->flags & MMC_DATA_READ) { 609 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 610 data->sg_len, direction); 611 612 align = host->align_buffer; 613 614 for_each_sg(data->sg, sg, host->sg_count, i) { 615 if (sg_dma_address(sg) & 0x3) { 616 size = 4 - (sg_dma_address(sg) & 0x3); 617 618 buffer = sdhci_kmap_atomic(sg, &flags); 619 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 620 memcpy(buffer, align, size); 621 sdhci_kunmap_atomic(buffer, &flags); 622 623 align += 4; 624 } 625 } 626 } 627 628 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 629 data->sg_len, direction); 630 } 631 632 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 633 { 634 u8 count; 635 struct mmc_data *data = cmd->data; 636 unsigned target_timeout, current_timeout; 637 638 /* 639 * If the host controller provides us with an incorrect timeout 640 * value, just skip the check and use 0xE. The hardware may take 641 * longer to time out, but that's much better than having a too-short 642 * timeout value. 643 */ 644 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 645 return 0xE; 646 647 /* Unspecified timeout, assume max */ 648 if (!data && !cmd->cmd_timeout_ms) 649 return 0xE; 650 651 /* timeout in us */ 652 if (!data) 653 target_timeout = cmd->cmd_timeout_ms * 1000; 654 else { 655 target_timeout = data->timeout_ns / 1000; 656 if (host->clock) 657 target_timeout += data->timeout_clks / host->clock; 658 } 659 660 /* 661 * Figure out needed cycles. 662 * We do this in steps in order to fit inside a 32 bit int. 663 * The first step is the minimum timeout, which will have a 664 * minimum resolution of 6 bits: 665 * (1) 2^13*1000 > 2^22, 666 * (2) host->timeout_clk < 2^16 667 * => 668 * (1) / (2) > 2^6 669 */ 670 count = 0; 671 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 672 while (current_timeout < target_timeout) { 673 count++; 674 current_timeout <<= 1; 675 if (count >= 0xF) 676 break; 677 } 678 679 if (count >= 0xF) { 680 pr_warning("%s: Too large timeout requested for CMD%d!\n", 681 mmc_hostname(host->mmc), cmd->opcode); 682 count = 0xE; 683 } 684 685 return count; 686 } 687 688 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 689 { 690 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 691 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 692 693 if (host->flags & SDHCI_REQ_USE_DMA) 694 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 695 else 696 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 697 } 698 699 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 700 { 701 u8 count; 702 u8 ctrl; 703 struct mmc_data *data = cmd->data; 704 int ret; 705 706 WARN_ON(host->data); 707 708 if (data || (cmd->flags & MMC_RSP_BUSY)) { 709 count = sdhci_calc_timeout(host, cmd); 710 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 711 } 712 713 if (!data) 714 return; 715 716 /* Sanity checks */ 717 BUG_ON(data->blksz * data->blocks > 524288); 718 BUG_ON(data->blksz > host->mmc->max_blk_size); 719 BUG_ON(data->blocks > 65535); 720 721 host->data = data; 722 host->data_early = 0; 723 host->data->bytes_xfered = 0; 724 725 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 726 host->flags |= SDHCI_REQ_USE_DMA; 727 728 /* 729 * FIXME: This doesn't account for merging when mapping the 730 * scatterlist. 731 */ 732 if (host->flags & SDHCI_REQ_USE_DMA) { 733 int broken, i; 734 struct scatterlist *sg; 735 736 broken = 0; 737 if (host->flags & SDHCI_USE_ADMA) { 738 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 739 broken = 1; 740 } else { 741 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 742 broken = 1; 743 } 744 745 if (unlikely(broken)) { 746 for_each_sg(data->sg, sg, data->sg_len, i) { 747 if (sg->length & 0x3) { 748 DBG("Reverting to PIO because of " 749 "transfer size (%d)\n", 750 sg->length); 751 host->flags &= ~SDHCI_REQ_USE_DMA; 752 break; 753 } 754 } 755 } 756 } 757 758 /* 759 * The assumption here being that alignment is the same after 760 * translation to device address space. 761 */ 762 if (host->flags & SDHCI_REQ_USE_DMA) { 763 int broken, i; 764 struct scatterlist *sg; 765 766 broken = 0; 767 if (host->flags & SDHCI_USE_ADMA) { 768 /* 769 * As we use 3 byte chunks to work around 770 * alignment problems, we need to check this 771 * quirk. 772 */ 773 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 774 broken = 1; 775 } else { 776 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 777 broken = 1; 778 } 779 780 if (unlikely(broken)) { 781 for_each_sg(data->sg, sg, data->sg_len, i) { 782 if (sg->offset & 0x3) { 783 DBG("Reverting to PIO because of " 784 "bad alignment\n"); 785 host->flags &= ~SDHCI_REQ_USE_DMA; 786 break; 787 } 788 } 789 } 790 } 791 792 if (host->flags & SDHCI_REQ_USE_DMA) { 793 if (host->flags & SDHCI_USE_ADMA) { 794 ret = sdhci_adma_table_pre(host, data); 795 if (ret) { 796 /* 797 * This only happens when someone fed 798 * us an invalid request. 799 */ 800 WARN_ON(1); 801 host->flags &= ~SDHCI_REQ_USE_DMA; 802 } else { 803 sdhci_writel(host, host->adma_addr, 804 SDHCI_ADMA_ADDRESS); 805 } 806 } else { 807 int sg_cnt; 808 809 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 810 data->sg, data->sg_len, 811 (data->flags & MMC_DATA_READ) ? 812 DMA_FROM_DEVICE : 813 DMA_TO_DEVICE); 814 if (sg_cnt == 0) { 815 /* 816 * This only happens when someone fed 817 * us an invalid request. 818 */ 819 WARN_ON(1); 820 host->flags &= ~SDHCI_REQ_USE_DMA; 821 } else { 822 WARN_ON(sg_cnt != 1); 823 sdhci_writel(host, sg_dma_address(data->sg), 824 SDHCI_DMA_ADDRESS); 825 } 826 } 827 } 828 829 /* 830 * Always adjust the DMA selection as some controllers 831 * (e.g. JMicron) can't do PIO properly when the selection 832 * is ADMA. 833 */ 834 if (host->version >= SDHCI_SPEC_200) { 835 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 836 ctrl &= ~SDHCI_CTRL_DMA_MASK; 837 if ((host->flags & SDHCI_REQ_USE_DMA) && 838 (host->flags & SDHCI_USE_ADMA)) 839 ctrl |= SDHCI_CTRL_ADMA32; 840 else 841 ctrl |= SDHCI_CTRL_SDMA; 842 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 843 } 844 845 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 846 int flags; 847 848 flags = SG_MITER_ATOMIC; 849 if (host->data->flags & MMC_DATA_READ) 850 flags |= SG_MITER_TO_SG; 851 else 852 flags |= SG_MITER_FROM_SG; 853 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 854 host->blocks = data->blocks; 855 } 856 857 sdhci_set_transfer_irqs(host); 858 859 /* Set the DMA boundary value and block size */ 860 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 861 data->blksz), SDHCI_BLOCK_SIZE); 862 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 863 } 864 865 static void sdhci_set_transfer_mode(struct sdhci_host *host, 866 struct mmc_command *cmd) 867 { 868 u16 mode; 869 struct mmc_data *data = cmd->data; 870 871 if (data == NULL) 872 return; 873 874 WARN_ON(!host->data); 875 876 mode = SDHCI_TRNS_BLK_CNT_EN; 877 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 878 mode |= SDHCI_TRNS_MULTI; 879 /* 880 * If we are sending CMD23, CMD12 never gets sent 881 * on successful completion (so no Auto-CMD12). 882 */ 883 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 884 mode |= SDHCI_TRNS_AUTO_CMD12; 885 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 886 mode |= SDHCI_TRNS_AUTO_CMD23; 887 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 888 } 889 } 890 891 if (data->flags & MMC_DATA_READ) 892 mode |= SDHCI_TRNS_READ; 893 if (host->flags & SDHCI_REQ_USE_DMA) 894 mode |= SDHCI_TRNS_DMA; 895 896 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 897 } 898 899 static void sdhci_finish_data(struct sdhci_host *host) 900 { 901 struct mmc_data *data; 902 903 BUG_ON(!host->data); 904 905 data = host->data; 906 host->data = NULL; 907 908 if (host->flags & SDHCI_REQ_USE_DMA) { 909 if (host->flags & SDHCI_USE_ADMA) 910 sdhci_adma_table_post(host, data); 911 else { 912 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 913 data->sg_len, (data->flags & MMC_DATA_READ) ? 914 DMA_FROM_DEVICE : DMA_TO_DEVICE); 915 } 916 } 917 918 /* 919 * The specification states that the block count register must 920 * be updated, but it does not specify at what point in the 921 * data flow. That makes the register entirely useless to read 922 * back so we have to assume that nothing made it to the card 923 * in the event of an error. 924 */ 925 if (data->error) 926 data->bytes_xfered = 0; 927 else 928 data->bytes_xfered = data->blksz * data->blocks; 929 930 /* 931 * Need to send CMD12 if - 932 * a) open-ended multiblock transfer (no CMD23) 933 * b) error in multiblock transfer 934 */ 935 if (data->stop && 936 (data->error || 937 !host->mrq->sbc)) { 938 939 /* 940 * The controller needs a reset of internal state machines 941 * upon error conditions. 942 */ 943 if (data->error) { 944 sdhci_reset(host, SDHCI_RESET_CMD); 945 sdhci_reset(host, SDHCI_RESET_DATA); 946 } 947 948 sdhci_send_command(host, data->stop); 949 } else 950 tasklet_schedule(&host->finish_tasklet); 951 } 952 953 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 954 { 955 int flags; 956 u32 mask; 957 unsigned long timeout; 958 959 WARN_ON(host->cmd); 960 961 /* Wait max 10 ms */ 962 timeout = 10; 963 964 mask = SDHCI_CMD_INHIBIT; 965 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 966 mask |= SDHCI_DATA_INHIBIT; 967 968 /* We shouldn't wait for data inihibit for stop commands, even 969 though they might use busy signaling */ 970 if (host->mrq->data && (cmd == host->mrq->data->stop)) 971 mask &= ~SDHCI_DATA_INHIBIT; 972 973 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 974 if (timeout == 0) { 975 pr_err("%s: Controller never released " 976 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 977 sdhci_dumpregs(host); 978 cmd->error = -EIO; 979 tasklet_schedule(&host->finish_tasklet); 980 return; 981 } 982 timeout--; 983 mdelay(1); 984 } 985 986 mod_timer(&host->timer, jiffies + 10 * HZ); 987 988 host->cmd = cmd; 989 990 sdhci_prepare_data(host, cmd); 991 992 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 993 994 sdhci_set_transfer_mode(host, cmd); 995 996 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 997 pr_err("%s: Unsupported response type!\n", 998 mmc_hostname(host->mmc)); 999 cmd->error = -EINVAL; 1000 tasklet_schedule(&host->finish_tasklet); 1001 return; 1002 } 1003 1004 if (!(cmd->flags & MMC_RSP_PRESENT)) 1005 flags = SDHCI_CMD_RESP_NONE; 1006 else if (cmd->flags & MMC_RSP_136) 1007 flags = SDHCI_CMD_RESP_LONG; 1008 else if (cmd->flags & MMC_RSP_BUSY) 1009 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1010 else 1011 flags = SDHCI_CMD_RESP_SHORT; 1012 1013 if (cmd->flags & MMC_RSP_CRC) 1014 flags |= SDHCI_CMD_CRC; 1015 if (cmd->flags & MMC_RSP_OPCODE) 1016 flags |= SDHCI_CMD_INDEX; 1017 1018 /* CMD19 is special in that the Data Present Select should be set */ 1019 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK)) 1020 flags |= SDHCI_CMD_DATA; 1021 1022 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1023 } 1024 1025 static void sdhci_finish_command(struct sdhci_host *host) 1026 { 1027 int i; 1028 1029 BUG_ON(host->cmd == NULL); 1030 1031 if (host->cmd->flags & MMC_RSP_PRESENT) { 1032 if (host->cmd->flags & MMC_RSP_136) { 1033 /* CRC is stripped so we need to do some shifting. */ 1034 for (i = 0;i < 4;i++) { 1035 host->cmd->resp[i] = sdhci_readl(host, 1036 SDHCI_RESPONSE + (3-i)*4) << 8; 1037 if (i != 3) 1038 host->cmd->resp[i] |= 1039 sdhci_readb(host, 1040 SDHCI_RESPONSE + (3-i)*4-1); 1041 } 1042 } else { 1043 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1044 } 1045 } 1046 1047 host->cmd->error = 0; 1048 1049 /* Finished CMD23, now send actual command. */ 1050 if (host->cmd == host->mrq->sbc) { 1051 host->cmd = NULL; 1052 sdhci_send_command(host, host->mrq->cmd); 1053 } else { 1054 1055 /* Processed actual command. */ 1056 if (host->data && host->data_early) 1057 sdhci_finish_data(host); 1058 1059 if (!host->cmd->data) 1060 tasklet_schedule(&host->finish_tasklet); 1061 1062 host->cmd = NULL; 1063 } 1064 } 1065 1066 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1067 { 1068 int div = 0; /* Initialized for compiler warning */ 1069 u16 clk = 0; 1070 unsigned long timeout; 1071 1072 if (clock == host->clock) 1073 return; 1074 1075 if (host->ops->set_clock) { 1076 host->ops->set_clock(host, clock); 1077 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1078 return; 1079 } 1080 1081 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1082 1083 if (clock == 0) 1084 goto out; 1085 1086 if (host->version >= SDHCI_SPEC_300) { 1087 /* 1088 * Check if the Host Controller supports Programmable Clock 1089 * Mode. 1090 */ 1091 if (host->clk_mul) { 1092 u16 ctrl; 1093 1094 /* 1095 * We need to figure out whether the Host Driver needs 1096 * to select Programmable Clock Mode, or the value can 1097 * be set automatically by the Host Controller based on 1098 * the Preset Value registers. 1099 */ 1100 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1101 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1102 for (div = 1; div <= 1024; div++) { 1103 if (((host->max_clk * host->clk_mul) / 1104 div) <= clock) 1105 break; 1106 } 1107 /* 1108 * Set Programmable Clock Mode in the Clock 1109 * Control register. 1110 */ 1111 clk = SDHCI_PROG_CLOCK_MODE; 1112 div--; 1113 } 1114 } else { 1115 /* Version 3.00 divisors must be a multiple of 2. */ 1116 if (host->max_clk <= clock) 1117 div = 1; 1118 else { 1119 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1120 div += 2) { 1121 if ((host->max_clk / div) <= clock) 1122 break; 1123 } 1124 } 1125 div >>= 1; 1126 } 1127 } else { 1128 /* Version 2.00 divisors must be a power of 2. */ 1129 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1130 if ((host->max_clk / div) <= clock) 1131 break; 1132 } 1133 div >>= 1; 1134 } 1135 1136 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1137 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1138 << SDHCI_DIVIDER_HI_SHIFT; 1139 clk |= SDHCI_CLOCK_INT_EN; 1140 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1141 1142 /* Wait max 20 ms */ 1143 timeout = 20; 1144 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1145 & SDHCI_CLOCK_INT_STABLE)) { 1146 if (timeout == 0) { 1147 pr_err("%s: Internal clock never " 1148 "stabilised.\n", mmc_hostname(host->mmc)); 1149 sdhci_dumpregs(host); 1150 return; 1151 } 1152 timeout--; 1153 mdelay(1); 1154 } 1155 1156 clk |= SDHCI_CLOCK_CARD_EN; 1157 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1158 1159 out: 1160 host->clock = clock; 1161 } 1162 1163 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 1164 { 1165 u8 pwr = 0; 1166 1167 if (power != (unsigned short)-1) { 1168 switch (1 << power) { 1169 case MMC_VDD_165_195: 1170 pwr = SDHCI_POWER_180; 1171 break; 1172 case MMC_VDD_29_30: 1173 case MMC_VDD_30_31: 1174 pwr = SDHCI_POWER_300; 1175 break; 1176 case MMC_VDD_32_33: 1177 case MMC_VDD_33_34: 1178 pwr = SDHCI_POWER_330; 1179 break; 1180 default: 1181 BUG(); 1182 } 1183 } 1184 1185 if (host->pwr == pwr) 1186 return; 1187 1188 host->pwr = pwr; 1189 1190 if (pwr == 0) { 1191 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1192 return; 1193 } 1194 1195 /* 1196 * Spec says that we should clear the power reg before setting 1197 * a new value. Some controllers don't seem to like this though. 1198 */ 1199 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1200 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1201 1202 /* 1203 * At least the Marvell CaFe chip gets confused if we set the voltage 1204 * and set turn on power at the same time, so set the voltage first. 1205 */ 1206 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1207 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1208 1209 pwr |= SDHCI_POWER_ON; 1210 1211 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1212 1213 /* 1214 * Some controllers need an extra 10ms delay of 10ms before they 1215 * can apply clock after applying power 1216 */ 1217 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1218 mdelay(10); 1219 } 1220 1221 /*****************************************************************************\ 1222 * * 1223 * MMC callbacks * 1224 * * 1225 \*****************************************************************************/ 1226 1227 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1228 { 1229 struct sdhci_host *host; 1230 bool present; 1231 unsigned long flags; 1232 1233 host = mmc_priv(mmc); 1234 1235 sdhci_runtime_pm_get(host); 1236 1237 spin_lock_irqsave(&host->lock, flags); 1238 1239 WARN_ON(host->mrq != NULL); 1240 1241 #ifndef SDHCI_USE_LEDS_CLASS 1242 sdhci_activate_led(host); 1243 #endif 1244 1245 /* 1246 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1247 * requests if Auto-CMD12 is enabled. 1248 */ 1249 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1250 if (mrq->stop) { 1251 mrq->data->stop = NULL; 1252 mrq->stop = NULL; 1253 } 1254 } 1255 1256 host->mrq = mrq; 1257 1258 /* If polling, assume that the card is always present. */ 1259 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1260 present = true; 1261 else 1262 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1263 SDHCI_CARD_PRESENT; 1264 1265 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1266 host->mrq->cmd->error = -ENOMEDIUM; 1267 tasklet_schedule(&host->finish_tasklet); 1268 } else { 1269 u32 present_state; 1270 1271 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1272 /* 1273 * Check if the re-tuning timer has already expired and there 1274 * is no on-going data transfer. If so, we need to execute 1275 * tuning procedure before sending command. 1276 */ 1277 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1278 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1279 spin_unlock_irqrestore(&host->lock, flags); 1280 sdhci_execute_tuning(mmc); 1281 spin_lock_irqsave(&host->lock, flags); 1282 1283 /* Restore original mmc_request structure */ 1284 host->mrq = mrq; 1285 } 1286 1287 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1288 sdhci_send_command(host, mrq->sbc); 1289 else 1290 sdhci_send_command(host, mrq->cmd); 1291 } 1292 1293 mmiowb(); 1294 spin_unlock_irqrestore(&host->lock, flags); 1295 } 1296 1297 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1298 { 1299 unsigned long flags; 1300 u8 ctrl; 1301 1302 spin_lock_irqsave(&host->lock, flags); 1303 1304 if (host->flags & SDHCI_DEVICE_DEAD) 1305 goto out; 1306 1307 /* 1308 * Reset the chip on each power off. 1309 * Should clear out any weird states. 1310 */ 1311 if (ios->power_mode == MMC_POWER_OFF) { 1312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1313 sdhci_reinit(host); 1314 } 1315 1316 sdhci_set_clock(host, ios->clock); 1317 1318 if (ios->power_mode == MMC_POWER_OFF) 1319 sdhci_set_power(host, -1); 1320 else 1321 sdhci_set_power(host, ios->vdd); 1322 1323 if (host->ops->platform_send_init_74_clocks) 1324 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1325 1326 /* 1327 * If your platform has 8-bit width support but is not a v3 controller, 1328 * or if it requires special setup code, you should implement that in 1329 * platform_8bit_width(). 1330 */ 1331 if (host->ops->platform_8bit_width) 1332 host->ops->platform_8bit_width(host, ios->bus_width); 1333 else { 1334 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1335 if (ios->bus_width == MMC_BUS_WIDTH_8) { 1336 ctrl &= ~SDHCI_CTRL_4BITBUS; 1337 if (host->version >= SDHCI_SPEC_300) 1338 ctrl |= SDHCI_CTRL_8BITBUS; 1339 } else { 1340 if (host->version >= SDHCI_SPEC_300) 1341 ctrl &= ~SDHCI_CTRL_8BITBUS; 1342 if (ios->bus_width == MMC_BUS_WIDTH_4) 1343 ctrl |= SDHCI_CTRL_4BITBUS; 1344 else 1345 ctrl &= ~SDHCI_CTRL_4BITBUS; 1346 } 1347 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1348 } 1349 1350 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1351 1352 if ((ios->timing == MMC_TIMING_SD_HS || 1353 ios->timing == MMC_TIMING_MMC_HS) 1354 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1355 ctrl |= SDHCI_CTRL_HISPD; 1356 else 1357 ctrl &= ~SDHCI_CTRL_HISPD; 1358 1359 if (host->version >= SDHCI_SPEC_300) { 1360 u16 clk, ctrl_2; 1361 unsigned int clock; 1362 1363 /* In case of UHS-I modes, set High Speed Enable */ 1364 if ((ios->timing == MMC_TIMING_UHS_SDR50) || 1365 (ios->timing == MMC_TIMING_UHS_SDR104) || 1366 (ios->timing == MMC_TIMING_UHS_DDR50) || 1367 (ios->timing == MMC_TIMING_UHS_SDR25) || 1368 (ios->timing == MMC_TIMING_UHS_SDR12)) 1369 ctrl |= SDHCI_CTRL_HISPD; 1370 1371 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1372 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1373 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1374 /* 1375 * We only need to set Driver Strength if the 1376 * preset value enable is not set. 1377 */ 1378 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1379 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1380 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1381 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1382 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1383 1384 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1385 } else { 1386 /* 1387 * According to SDHC Spec v3.00, if the Preset Value 1388 * Enable in the Host Control 2 register is set, we 1389 * need to reset SD Clock Enable before changing High 1390 * Speed Enable to avoid generating clock gliches. 1391 */ 1392 1393 /* Reset SD Clock Enable */ 1394 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1395 clk &= ~SDHCI_CLOCK_CARD_EN; 1396 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1397 1398 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1399 1400 /* Re-enable SD Clock */ 1401 clock = host->clock; 1402 host->clock = 0; 1403 sdhci_set_clock(host, clock); 1404 } 1405 1406 1407 /* Reset SD Clock Enable */ 1408 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1409 clk &= ~SDHCI_CLOCK_CARD_EN; 1410 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1411 1412 if (host->ops->set_uhs_signaling) 1413 host->ops->set_uhs_signaling(host, ios->timing); 1414 else { 1415 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1416 /* Select Bus Speed Mode for host */ 1417 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1418 if (ios->timing == MMC_TIMING_UHS_SDR12) 1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1420 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1422 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1423 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1424 else if (ios->timing == MMC_TIMING_UHS_SDR104) 1425 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1426 else if (ios->timing == MMC_TIMING_UHS_DDR50) 1427 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1428 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1429 } 1430 1431 /* Re-enable SD Clock */ 1432 clock = host->clock; 1433 host->clock = 0; 1434 sdhci_set_clock(host, clock); 1435 } else 1436 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1437 1438 /* 1439 * Some (ENE) controllers go apeshit on some ios operation, 1440 * signalling timeout and CRC errors even on CMD0. Resetting 1441 * it on each ios seems to solve the problem. 1442 */ 1443 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1444 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1445 1446 out: 1447 mmiowb(); 1448 spin_unlock_irqrestore(&host->lock, flags); 1449 } 1450 1451 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1452 { 1453 struct sdhci_host *host = mmc_priv(mmc); 1454 1455 sdhci_runtime_pm_get(host); 1456 sdhci_do_set_ios(host, ios); 1457 sdhci_runtime_pm_put(host); 1458 } 1459 1460 static int sdhci_check_ro(struct sdhci_host *host) 1461 { 1462 unsigned long flags; 1463 int is_readonly; 1464 1465 spin_lock_irqsave(&host->lock, flags); 1466 1467 if (host->flags & SDHCI_DEVICE_DEAD) 1468 is_readonly = 0; 1469 else if (host->ops->get_ro) 1470 is_readonly = host->ops->get_ro(host); 1471 else 1472 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1473 & SDHCI_WRITE_PROTECT); 1474 1475 spin_unlock_irqrestore(&host->lock, flags); 1476 1477 /* This quirk needs to be replaced by a callback-function later */ 1478 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1479 !is_readonly : is_readonly; 1480 } 1481 1482 #define SAMPLE_COUNT 5 1483 1484 static int sdhci_do_get_ro(struct sdhci_host *host) 1485 { 1486 int i, ro_count; 1487 1488 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1489 return sdhci_check_ro(host); 1490 1491 ro_count = 0; 1492 for (i = 0; i < SAMPLE_COUNT; i++) { 1493 if (sdhci_check_ro(host)) { 1494 if (++ro_count > SAMPLE_COUNT / 2) 1495 return 1; 1496 } 1497 msleep(30); 1498 } 1499 return 0; 1500 } 1501 1502 static void sdhci_hw_reset(struct mmc_host *mmc) 1503 { 1504 struct sdhci_host *host = mmc_priv(mmc); 1505 1506 if (host->ops && host->ops->hw_reset) 1507 host->ops->hw_reset(host); 1508 } 1509 1510 static int sdhci_get_ro(struct mmc_host *mmc) 1511 { 1512 struct sdhci_host *host = mmc_priv(mmc); 1513 int ret; 1514 1515 sdhci_runtime_pm_get(host); 1516 ret = sdhci_do_get_ro(host); 1517 sdhci_runtime_pm_put(host); 1518 return ret; 1519 } 1520 1521 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1522 { 1523 if (host->flags & SDHCI_DEVICE_DEAD) 1524 goto out; 1525 1526 if (enable) 1527 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1528 else 1529 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1530 1531 /* SDIO IRQ will be enabled as appropriate in runtime resume */ 1532 if (host->runtime_suspended) 1533 goto out; 1534 1535 if (enable) 1536 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 1537 else 1538 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1539 out: 1540 mmiowb(); 1541 } 1542 1543 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1544 { 1545 struct sdhci_host *host = mmc_priv(mmc); 1546 unsigned long flags; 1547 1548 spin_lock_irqsave(&host->lock, flags); 1549 sdhci_enable_sdio_irq_nolock(host, enable); 1550 spin_unlock_irqrestore(&host->lock, flags); 1551 } 1552 1553 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1554 struct mmc_ios *ios) 1555 { 1556 u8 pwr; 1557 u16 clk, ctrl; 1558 u32 present_state; 1559 1560 /* 1561 * Signal Voltage Switching is only applicable for Host Controllers 1562 * v3.00 and above. 1563 */ 1564 if (host->version < SDHCI_SPEC_300) 1565 return 0; 1566 1567 /* 1568 * We first check whether the request is to set signalling voltage 1569 * to 3.3V. If so, we change the voltage to 3.3V and return quickly. 1570 */ 1571 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1572 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1573 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1574 ctrl &= ~SDHCI_CTRL_VDD_180; 1575 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1576 1577 /* Wait for 5ms */ 1578 usleep_range(5000, 5500); 1579 1580 /* 3.3V regulator output should be stable within 5 ms */ 1581 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1582 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1583 return 0; 1584 else { 1585 pr_info(DRIVER_NAME ": Switching to 3.3V " 1586 "signalling voltage failed\n"); 1587 return -EIO; 1588 } 1589 } else if (!(ctrl & SDHCI_CTRL_VDD_180) && 1590 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) { 1591 /* Stop SDCLK */ 1592 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1593 clk &= ~SDHCI_CLOCK_CARD_EN; 1594 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1595 1596 /* Check whether DAT[3:0] is 0000 */ 1597 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1598 if (!((present_state & SDHCI_DATA_LVL_MASK) >> 1599 SDHCI_DATA_LVL_SHIFT)) { 1600 /* 1601 * Enable 1.8V Signal Enable in the Host Control2 1602 * register 1603 */ 1604 ctrl |= SDHCI_CTRL_VDD_180; 1605 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1606 1607 /* Wait for 5ms */ 1608 usleep_range(5000, 5500); 1609 1610 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1611 if (ctrl & SDHCI_CTRL_VDD_180) { 1612 /* Provide SDCLK again and wait for 1ms*/ 1613 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1614 clk |= SDHCI_CLOCK_CARD_EN; 1615 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1616 usleep_range(1000, 1500); 1617 1618 /* 1619 * If DAT[3:0] level is 1111b, then the card 1620 * was successfully switched to 1.8V signaling. 1621 */ 1622 present_state = sdhci_readl(host, 1623 SDHCI_PRESENT_STATE); 1624 if ((present_state & SDHCI_DATA_LVL_MASK) == 1625 SDHCI_DATA_LVL_MASK) 1626 return 0; 1627 } 1628 } 1629 1630 /* 1631 * If we are here, that means the switch to 1.8V signaling 1632 * failed. We power cycle the card, and retry initialization 1633 * sequence by setting S18R to 0. 1634 */ 1635 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL); 1636 pwr &= ~SDHCI_POWER_ON; 1637 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1638 1639 /* Wait for 1ms as per the spec */ 1640 usleep_range(1000, 1500); 1641 pwr |= SDHCI_POWER_ON; 1642 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1643 1644 pr_info(DRIVER_NAME ": Switching to 1.8V signalling " 1645 "voltage failed, retrying with S18R set to 0\n"); 1646 return -EAGAIN; 1647 } else 1648 /* No signal voltage switch required */ 1649 return 0; 1650 } 1651 1652 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1653 struct mmc_ios *ios) 1654 { 1655 struct sdhci_host *host = mmc_priv(mmc); 1656 int err; 1657 1658 if (host->version < SDHCI_SPEC_300) 1659 return 0; 1660 sdhci_runtime_pm_get(host); 1661 err = sdhci_do_start_signal_voltage_switch(host, ios); 1662 sdhci_runtime_pm_put(host); 1663 return err; 1664 } 1665 1666 static int sdhci_execute_tuning(struct mmc_host *mmc) 1667 { 1668 struct sdhci_host *host; 1669 u16 ctrl; 1670 u32 ier; 1671 int tuning_loop_counter = MAX_TUNING_LOOP; 1672 unsigned long timeout; 1673 int err = 0; 1674 1675 host = mmc_priv(mmc); 1676 1677 sdhci_runtime_pm_get(host); 1678 disable_irq(host->irq); 1679 spin_lock(&host->lock); 1680 1681 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1682 1683 /* 1684 * Host Controller needs tuning only in case of SDR104 mode 1685 * and for SDR50 mode when Use Tuning for SDR50 is set in 1686 * Capabilities register. 1687 */ 1688 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1689 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1690 (host->flags & SDHCI_SDR50_NEEDS_TUNING))) 1691 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1692 else { 1693 spin_unlock(&host->lock); 1694 enable_irq(host->irq); 1695 sdhci_runtime_pm_put(host); 1696 return 0; 1697 } 1698 1699 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1700 1701 /* 1702 * As per the Host Controller spec v3.00, tuning command 1703 * generates Buffer Read Ready interrupt, so enable that. 1704 * 1705 * Note: The spec clearly says that when tuning sequence 1706 * is being performed, the controller does not generate 1707 * interrupts other than Buffer Read Ready interrupt. But 1708 * to make sure we don't hit a controller bug, we _only_ 1709 * enable Buffer Read Ready interrupt here. 1710 */ 1711 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1712 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1713 1714 /* 1715 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1716 * of loops reaches 40 times or a timeout of 150ms occurs. 1717 */ 1718 timeout = 150; 1719 do { 1720 struct mmc_command cmd = {0}; 1721 struct mmc_request mrq = {NULL}; 1722 1723 if (!tuning_loop_counter && !timeout) 1724 break; 1725 1726 cmd.opcode = MMC_SEND_TUNING_BLOCK; 1727 cmd.arg = 0; 1728 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1729 cmd.retries = 0; 1730 cmd.data = NULL; 1731 cmd.error = 0; 1732 1733 mrq.cmd = &cmd; 1734 host->mrq = &mrq; 1735 1736 /* 1737 * In response to CMD19, the card sends 64 bytes of tuning 1738 * block to the Host Controller. So we set the block size 1739 * to 64 here. 1740 */ 1741 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 1742 1743 /* 1744 * The tuning block is sent by the card to the host controller. 1745 * So we set the TRNS_READ bit in the Transfer Mode register. 1746 * This also takes care of setting DMA Enable and Multi Block 1747 * Select in the same register to 0. 1748 */ 1749 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1750 1751 sdhci_send_command(host, &cmd); 1752 1753 host->cmd = NULL; 1754 host->mrq = NULL; 1755 1756 spin_unlock(&host->lock); 1757 enable_irq(host->irq); 1758 1759 /* Wait for Buffer Read Ready interrupt */ 1760 wait_event_interruptible_timeout(host->buf_ready_int, 1761 (host->tuning_done == 1), 1762 msecs_to_jiffies(50)); 1763 disable_irq(host->irq); 1764 spin_lock(&host->lock); 1765 1766 if (!host->tuning_done) { 1767 pr_info(DRIVER_NAME ": Timeout waiting for " 1768 "Buffer Read Ready interrupt during tuning " 1769 "procedure, falling back to fixed sampling " 1770 "clock\n"); 1771 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1772 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1773 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1774 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1775 1776 err = -EIO; 1777 goto out; 1778 } 1779 1780 host->tuning_done = 0; 1781 1782 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1783 tuning_loop_counter--; 1784 timeout--; 1785 mdelay(1); 1786 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1787 1788 /* 1789 * The Host Driver has exhausted the maximum number of loops allowed, 1790 * so use fixed sampling frequency. 1791 */ 1792 if (!tuning_loop_counter || !timeout) { 1793 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1794 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1795 } else { 1796 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1797 pr_info(DRIVER_NAME ": Tuning procedure" 1798 " failed, falling back to fixed sampling" 1799 " clock\n"); 1800 err = -EIO; 1801 } 1802 } 1803 1804 out: 1805 /* 1806 * If this is the very first time we are here, we start the retuning 1807 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1808 * flag won't be set, we check this condition before actually starting 1809 * the timer. 1810 */ 1811 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1812 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1813 mod_timer(&host->tuning_timer, jiffies + 1814 host->tuning_count * HZ); 1815 /* Tuning mode 1 limits the maximum data length to 4MB */ 1816 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1817 } else { 1818 host->flags &= ~SDHCI_NEEDS_RETUNING; 1819 /* Reload the new initial value for timer */ 1820 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1821 mod_timer(&host->tuning_timer, jiffies + 1822 host->tuning_count * HZ); 1823 } 1824 1825 /* 1826 * In case tuning fails, host controllers which support re-tuning can 1827 * try tuning again at a later time, when the re-tuning timer expires. 1828 * So for these controllers, we return 0. Since there might be other 1829 * controllers who do not have this capability, we return error for 1830 * them. 1831 */ 1832 if (err && host->tuning_count && 1833 host->tuning_mode == SDHCI_TUNING_MODE_1) 1834 err = 0; 1835 1836 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 1837 spin_unlock(&host->lock); 1838 enable_irq(host->irq); 1839 sdhci_runtime_pm_put(host); 1840 1841 return err; 1842 } 1843 1844 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable) 1845 { 1846 u16 ctrl; 1847 unsigned long flags; 1848 1849 /* Host Controller v3.00 defines preset value registers */ 1850 if (host->version < SDHCI_SPEC_300) 1851 return; 1852 1853 spin_lock_irqsave(&host->lock, flags); 1854 1855 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1856 1857 /* 1858 * We only enable or disable Preset Value if they are not already 1859 * enabled or disabled respectively. Otherwise, we bail out. 1860 */ 1861 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1862 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 1863 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1864 host->flags |= SDHCI_PV_ENABLED; 1865 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1866 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 1867 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1868 host->flags &= ~SDHCI_PV_ENABLED; 1869 } 1870 1871 spin_unlock_irqrestore(&host->lock, flags); 1872 } 1873 1874 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) 1875 { 1876 struct sdhci_host *host = mmc_priv(mmc); 1877 1878 sdhci_runtime_pm_get(host); 1879 sdhci_do_enable_preset_value(host, enable); 1880 sdhci_runtime_pm_put(host); 1881 } 1882 1883 static const struct mmc_host_ops sdhci_ops = { 1884 .request = sdhci_request, 1885 .set_ios = sdhci_set_ios, 1886 .get_ro = sdhci_get_ro, 1887 .hw_reset = sdhci_hw_reset, 1888 .enable_sdio_irq = sdhci_enable_sdio_irq, 1889 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 1890 .execute_tuning = sdhci_execute_tuning, 1891 .enable_preset_value = sdhci_enable_preset_value, 1892 }; 1893 1894 /*****************************************************************************\ 1895 * * 1896 * Tasklets * 1897 * * 1898 \*****************************************************************************/ 1899 1900 static void sdhci_tasklet_card(unsigned long param) 1901 { 1902 struct sdhci_host *host; 1903 unsigned long flags; 1904 1905 host = (struct sdhci_host*)param; 1906 1907 spin_lock_irqsave(&host->lock, flags); 1908 1909 /* Check host->mrq first in case we are runtime suspended */ 1910 if (host->mrq && 1911 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 1912 pr_err("%s: Card removed during transfer!\n", 1913 mmc_hostname(host->mmc)); 1914 pr_err("%s: Resetting controller.\n", 1915 mmc_hostname(host->mmc)); 1916 1917 sdhci_reset(host, SDHCI_RESET_CMD); 1918 sdhci_reset(host, SDHCI_RESET_DATA); 1919 1920 host->mrq->cmd->error = -ENOMEDIUM; 1921 tasklet_schedule(&host->finish_tasklet); 1922 } 1923 1924 spin_unlock_irqrestore(&host->lock, flags); 1925 1926 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 1927 } 1928 1929 static void sdhci_tasklet_finish(unsigned long param) 1930 { 1931 struct sdhci_host *host; 1932 unsigned long flags; 1933 struct mmc_request *mrq; 1934 1935 host = (struct sdhci_host*)param; 1936 1937 spin_lock_irqsave(&host->lock, flags); 1938 1939 /* 1940 * If this tasklet gets rescheduled while running, it will 1941 * be run again afterwards but without any active request. 1942 */ 1943 if (!host->mrq) { 1944 spin_unlock_irqrestore(&host->lock, flags); 1945 return; 1946 } 1947 1948 del_timer(&host->timer); 1949 1950 mrq = host->mrq; 1951 1952 /* 1953 * The controller needs a reset of internal state machines 1954 * upon error conditions. 1955 */ 1956 if (!(host->flags & SDHCI_DEVICE_DEAD) && 1957 ((mrq->cmd && mrq->cmd->error) || 1958 (mrq->data && (mrq->data->error || 1959 (mrq->data->stop && mrq->data->stop->error))) || 1960 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1961 1962 /* Some controllers need this kick or reset won't work here */ 1963 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { 1964 unsigned int clock; 1965 1966 /* This is to force an update */ 1967 clock = host->clock; 1968 host->clock = 0; 1969 sdhci_set_clock(host, clock); 1970 } 1971 1972 /* Spec says we should do both at the same time, but Ricoh 1973 controllers do not like that. */ 1974 sdhci_reset(host, SDHCI_RESET_CMD); 1975 sdhci_reset(host, SDHCI_RESET_DATA); 1976 } 1977 1978 host->mrq = NULL; 1979 host->cmd = NULL; 1980 host->data = NULL; 1981 1982 #ifndef SDHCI_USE_LEDS_CLASS 1983 sdhci_deactivate_led(host); 1984 #endif 1985 1986 mmiowb(); 1987 spin_unlock_irqrestore(&host->lock, flags); 1988 1989 mmc_request_done(host->mmc, mrq); 1990 sdhci_runtime_pm_put(host); 1991 } 1992 1993 static void sdhci_timeout_timer(unsigned long data) 1994 { 1995 struct sdhci_host *host; 1996 unsigned long flags; 1997 1998 host = (struct sdhci_host*)data; 1999 2000 spin_lock_irqsave(&host->lock, flags); 2001 2002 if (host->mrq) { 2003 pr_err("%s: Timeout waiting for hardware " 2004 "interrupt.\n", mmc_hostname(host->mmc)); 2005 sdhci_dumpregs(host); 2006 2007 if (host->data) { 2008 host->data->error = -ETIMEDOUT; 2009 sdhci_finish_data(host); 2010 } else { 2011 if (host->cmd) 2012 host->cmd->error = -ETIMEDOUT; 2013 else 2014 host->mrq->cmd->error = -ETIMEDOUT; 2015 2016 tasklet_schedule(&host->finish_tasklet); 2017 } 2018 } 2019 2020 mmiowb(); 2021 spin_unlock_irqrestore(&host->lock, flags); 2022 } 2023 2024 static void sdhci_tuning_timer(unsigned long data) 2025 { 2026 struct sdhci_host *host; 2027 unsigned long flags; 2028 2029 host = (struct sdhci_host *)data; 2030 2031 spin_lock_irqsave(&host->lock, flags); 2032 2033 host->flags |= SDHCI_NEEDS_RETUNING; 2034 2035 spin_unlock_irqrestore(&host->lock, flags); 2036 } 2037 2038 /*****************************************************************************\ 2039 * * 2040 * Interrupt handling * 2041 * * 2042 \*****************************************************************************/ 2043 2044 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2045 { 2046 BUG_ON(intmask == 0); 2047 2048 if (!host->cmd) { 2049 pr_err("%s: Got command interrupt 0x%08x even " 2050 "though no command operation was in progress.\n", 2051 mmc_hostname(host->mmc), (unsigned)intmask); 2052 sdhci_dumpregs(host); 2053 return; 2054 } 2055 2056 if (intmask & SDHCI_INT_TIMEOUT) 2057 host->cmd->error = -ETIMEDOUT; 2058 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2059 SDHCI_INT_INDEX)) 2060 host->cmd->error = -EILSEQ; 2061 2062 if (host->cmd->error) { 2063 tasklet_schedule(&host->finish_tasklet); 2064 return; 2065 } 2066 2067 /* 2068 * The host can send and interrupt when the busy state has 2069 * ended, allowing us to wait without wasting CPU cycles. 2070 * Unfortunately this is overloaded on the "data complete" 2071 * interrupt, so we need to take some care when handling 2072 * it. 2073 * 2074 * Note: The 1.0 specification is a bit ambiguous about this 2075 * feature so there might be some problems with older 2076 * controllers. 2077 */ 2078 if (host->cmd->flags & MMC_RSP_BUSY) { 2079 if (host->cmd->data) 2080 DBG("Cannot wait for busy signal when also " 2081 "doing a data transfer"); 2082 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2083 return; 2084 2085 /* The controller does not support the end-of-busy IRQ, 2086 * fall through and take the SDHCI_INT_RESPONSE */ 2087 } 2088 2089 if (intmask & SDHCI_INT_RESPONSE) 2090 sdhci_finish_command(host); 2091 } 2092 2093 #ifdef CONFIG_MMC_DEBUG 2094 static void sdhci_show_adma_error(struct sdhci_host *host) 2095 { 2096 const char *name = mmc_hostname(host->mmc); 2097 u8 *desc = host->adma_desc; 2098 __le32 *dma; 2099 __le16 *len; 2100 u8 attr; 2101 2102 sdhci_dumpregs(host); 2103 2104 while (true) { 2105 dma = (__le32 *)(desc + 4); 2106 len = (__le16 *)(desc + 2); 2107 attr = *desc; 2108 2109 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2110 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2111 2112 desc += 8; 2113 2114 if (attr & 2) 2115 break; 2116 } 2117 } 2118 #else 2119 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2120 #endif 2121 2122 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2123 { 2124 BUG_ON(intmask == 0); 2125 2126 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2127 if (intmask & SDHCI_INT_DATA_AVAIL) { 2128 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) == 2129 MMC_SEND_TUNING_BLOCK) { 2130 host->tuning_done = 1; 2131 wake_up(&host->buf_ready_int); 2132 return; 2133 } 2134 } 2135 2136 if (!host->data) { 2137 /* 2138 * The "data complete" interrupt is also used to 2139 * indicate that a busy state has ended. See comment 2140 * above in sdhci_cmd_irq(). 2141 */ 2142 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2143 if (intmask & SDHCI_INT_DATA_END) { 2144 sdhci_finish_command(host); 2145 return; 2146 } 2147 } 2148 2149 pr_err("%s: Got data interrupt 0x%08x even " 2150 "though no data operation was in progress.\n", 2151 mmc_hostname(host->mmc), (unsigned)intmask); 2152 sdhci_dumpregs(host); 2153 2154 return; 2155 } 2156 2157 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2158 host->data->error = -ETIMEDOUT; 2159 else if (intmask & SDHCI_INT_DATA_END_BIT) 2160 host->data->error = -EILSEQ; 2161 else if ((intmask & SDHCI_INT_DATA_CRC) && 2162 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2163 != MMC_BUS_TEST_R) 2164 host->data->error = -EILSEQ; 2165 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2166 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2167 sdhci_show_adma_error(host); 2168 host->data->error = -EIO; 2169 } 2170 2171 if (host->data->error) 2172 sdhci_finish_data(host); 2173 else { 2174 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2175 sdhci_transfer_pio(host); 2176 2177 /* 2178 * We currently don't do anything fancy with DMA 2179 * boundaries, but as we can't disable the feature 2180 * we need to at least restart the transfer. 2181 * 2182 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2183 * should return a valid address to continue from, but as 2184 * some controllers are faulty, don't trust them. 2185 */ 2186 if (intmask & SDHCI_INT_DMA_END) { 2187 u32 dmastart, dmanow; 2188 dmastart = sg_dma_address(host->data->sg); 2189 dmanow = dmastart + host->data->bytes_xfered; 2190 /* 2191 * Force update to the next DMA block boundary. 2192 */ 2193 dmanow = (dmanow & 2194 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2195 SDHCI_DEFAULT_BOUNDARY_SIZE; 2196 host->data->bytes_xfered = dmanow - dmastart; 2197 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2198 " next 0x%08x\n", 2199 mmc_hostname(host->mmc), dmastart, 2200 host->data->bytes_xfered, dmanow); 2201 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2202 } 2203 2204 if (intmask & SDHCI_INT_DATA_END) { 2205 if (host->cmd) { 2206 /* 2207 * Data managed to finish before the 2208 * command completed. Make sure we do 2209 * things in the proper order. 2210 */ 2211 host->data_early = 1; 2212 } else { 2213 sdhci_finish_data(host); 2214 } 2215 } 2216 } 2217 } 2218 2219 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2220 { 2221 irqreturn_t result; 2222 struct sdhci_host *host = dev_id; 2223 u32 intmask; 2224 int cardint = 0; 2225 2226 spin_lock(&host->lock); 2227 2228 if (host->runtime_suspended) { 2229 spin_unlock(&host->lock); 2230 pr_warning("%s: got irq while runtime suspended\n", 2231 mmc_hostname(host->mmc)); 2232 return IRQ_HANDLED; 2233 } 2234 2235 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2236 2237 if (!intmask || intmask == 0xffffffff) { 2238 result = IRQ_NONE; 2239 goto out; 2240 } 2241 2242 DBG("*** %s got interrupt: 0x%08x\n", 2243 mmc_hostname(host->mmc), intmask); 2244 2245 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2246 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2247 SDHCI_CARD_PRESENT; 2248 2249 /* 2250 * There is a observation on i.mx esdhc. INSERT bit will be 2251 * immediately set again when it gets cleared, if a card is 2252 * inserted. We have to mask the irq to prevent interrupt 2253 * storm which will freeze the system. And the REMOVE gets 2254 * the same situation. 2255 * 2256 * More testing are needed here to ensure it works for other 2257 * platforms though. 2258 */ 2259 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2260 SDHCI_INT_CARD_REMOVE); 2261 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2262 SDHCI_INT_CARD_INSERT); 2263 2264 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2265 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2266 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2267 tasklet_schedule(&host->card_tasklet); 2268 } 2269 2270 if (intmask & SDHCI_INT_CMD_MASK) { 2271 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 2272 SDHCI_INT_STATUS); 2273 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2274 } 2275 2276 if (intmask & SDHCI_INT_DATA_MASK) { 2277 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 2278 SDHCI_INT_STATUS); 2279 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2280 } 2281 2282 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 2283 2284 intmask &= ~SDHCI_INT_ERROR; 2285 2286 if (intmask & SDHCI_INT_BUS_POWER) { 2287 pr_err("%s: Card is consuming too much power!\n", 2288 mmc_hostname(host->mmc)); 2289 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 2290 } 2291 2292 intmask &= ~SDHCI_INT_BUS_POWER; 2293 2294 if (intmask & SDHCI_INT_CARD_INT) 2295 cardint = 1; 2296 2297 intmask &= ~SDHCI_INT_CARD_INT; 2298 2299 if (intmask) { 2300 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2301 mmc_hostname(host->mmc), intmask); 2302 sdhci_dumpregs(host); 2303 2304 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2305 } 2306 2307 result = IRQ_HANDLED; 2308 2309 mmiowb(); 2310 out: 2311 spin_unlock(&host->lock); 2312 2313 /* 2314 * We have to delay this as it calls back into the driver. 2315 */ 2316 if (cardint) 2317 mmc_signal_sdio_irq(host->mmc); 2318 2319 return result; 2320 } 2321 2322 /*****************************************************************************\ 2323 * * 2324 * Suspend/resume * 2325 * * 2326 \*****************************************************************************/ 2327 2328 #ifdef CONFIG_PM 2329 2330 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) 2331 { 2332 int ret; 2333 2334 sdhci_disable_card_detection(host); 2335 2336 /* Disable tuning since we are suspending */ 2337 if (host->version >= SDHCI_SPEC_300 && host->tuning_count && 2338 host->tuning_mode == SDHCI_TUNING_MODE_1) { 2339 host->flags &= ~SDHCI_NEEDS_RETUNING; 2340 mod_timer(&host->tuning_timer, jiffies + 2341 host->tuning_count * HZ); 2342 } 2343 2344 ret = mmc_suspend_host(host->mmc); 2345 if (ret) 2346 return ret; 2347 2348 free_irq(host->irq, host); 2349 2350 if (host->vmmc) 2351 ret = regulator_disable(host->vmmc); 2352 2353 return ret; 2354 } 2355 2356 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2357 2358 int sdhci_resume_host(struct sdhci_host *host) 2359 { 2360 int ret; 2361 2362 if (host->vmmc) { 2363 int ret = regulator_enable(host->vmmc); 2364 if (ret) 2365 return ret; 2366 } 2367 2368 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2369 if (host->ops->enable_dma) 2370 host->ops->enable_dma(host); 2371 } 2372 2373 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2374 mmc_hostname(host->mmc), host); 2375 if (ret) 2376 return ret; 2377 2378 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2379 mmiowb(); 2380 2381 ret = mmc_resume_host(host->mmc); 2382 sdhci_enable_card_detection(host); 2383 2384 /* Set the re-tuning expiration flag */ 2385 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count && 2386 (host->tuning_mode == SDHCI_TUNING_MODE_1)) 2387 host->flags |= SDHCI_NEEDS_RETUNING; 2388 2389 return ret; 2390 } 2391 2392 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2393 2394 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2395 { 2396 u8 val; 2397 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2398 val |= SDHCI_WAKE_ON_INT; 2399 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2400 } 2401 2402 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2403 2404 #endif /* CONFIG_PM */ 2405 2406 #ifdef CONFIG_PM_RUNTIME 2407 2408 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2409 { 2410 return pm_runtime_get_sync(host->mmc->parent); 2411 } 2412 2413 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2414 { 2415 pm_runtime_mark_last_busy(host->mmc->parent); 2416 return pm_runtime_put_autosuspend(host->mmc->parent); 2417 } 2418 2419 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2420 { 2421 unsigned long flags; 2422 int ret = 0; 2423 2424 /* Disable tuning since we are suspending */ 2425 if (host->version >= SDHCI_SPEC_300 && 2426 host->tuning_mode == SDHCI_TUNING_MODE_1) { 2427 del_timer_sync(&host->tuning_timer); 2428 host->flags &= ~SDHCI_NEEDS_RETUNING; 2429 } 2430 2431 spin_lock_irqsave(&host->lock, flags); 2432 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2433 spin_unlock_irqrestore(&host->lock, flags); 2434 2435 synchronize_irq(host->irq); 2436 2437 spin_lock_irqsave(&host->lock, flags); 2438 host->runtime_suspended = true; 2439 spin_unlock_irqrestore(&host->lock, flags); 2440 2441 return ret; 2442 } 2443 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2444 2445 int sdhci_runtime_resume_host(struct sdhci_host *host) 2446 { 2447 unsigned long flags; 2448 int ret = 0, host_flags = host->flags; 2449 2450 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2451 if (host->ops->enable_dma) 2452 host->ops->enable_dma(host); 2453 } 2454 2455 sdhci_init(host, 0); 2456 2457 /* Force clock and power re-program */ 2458 host->pwr = 0; 2459 host->clock = 0; 2460 sdhci_do_set_ios(host, &host->mmc->ios); 2461 2462 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2463 if (host_flags & SDHCI_PV_ENABLED) 2464 sdhci_do_enable_preset_value(host, true); 2465 2466 /* Set the re-tuning expiration flag */ 2467 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count && 2468 (host->tuning_mode == SDHCI_TUNING_MODE_1)) 2469 host->flags |= SDHCI_NEEDS_RETUNING; 2470 2471 spin_lock_irqsave(&host->lock, flags); 2472 2473 host->runtime_suspended = false; 2474 2475 /* Enable SDIO IRQ */ 2476 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) 2477 sdhci_enable_sdio_irq_nolock(host, true); 2478 2479 /* Enable Card Detection */ 2480 sdhci_enable_card_detection(host); 2481 2482 spin_unlock_irqrestore(&host->lock, flags); 2483 2484 return ret; 2485 } 2486 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2487 2488 #endif 2489 2490 /*****************************************************************************\ 2491 * * 2492 * Device allocation/registration * 2493 * * 2494 \*****************************************************************************/ 2495 2496 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2497 size_t priv_size) 2498 { 2499 struct mmc_host *mmc; 2500 struct sdhci_host *host; 2501 2502 WARN_ON(dev == NULL); 2503 2504 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2505 if (!mmc) 2506 return ERR_PTR(-ENOMEM); 2507 2508 host = mmc_priv(mmc); 2509 host->mmc = mmc; 2510 2511 return host; 2512 } 2513 2514 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2515 2516 int sdhci_add_host(struct sdhci_host *host) 2517 { 2518 struct mmc_host *mmc; 2519 u32 caps[2]; 2520 u32 max_current_caps; 2521 unsigned int ocr_avail; 2522 int ret; 2523 2524 WARN_ON(host == NULL); 2525 if (host == NULL) 2526 return -EINVAL; 2527 2528 mmc = host->mmc; 2529 2530 if (debug_quirks) 2531 host->quirks = debug_quirks; 2532 if (debug_quirks2) 2533 host->quirks2 = debug_quirks2; 2534 2535 sdhci_reset(host, SDHCI_RESET_ALL); 2536 2537 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2538 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2539 >> SDHCI_SPEC_VER_SHIFT; 2540 if (host->version > SDHCI_SPEC_300) { 2541 pr_err("%s: Unknown controller version (%d). " 2542 "You may experience problems.\n", mmc_hostname(mmc), 2543 host->version); 2544 } 2545 2546 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2547 sdhci_readl(host, SDHCI_CAPABILITIES); 2548 2549 caps[1] = (host->version >= SDHCI_SPEC_300) ? 2550 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0; 2551 2552 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2553 host->flags |= SDHCI_USE_SDMA; 2554 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2555 DBG("Controller doesn't have SDMA capability\n"); 2556 else 2557 host->flags |= SDHCI_USE_SDMA; 2558 2559 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2560 (host->flags & SDHCI_USE_SDMA)) { 2561 DBG("Disabling DMA as it is marked broken\n"); 2562 host->flags &= ~SDHCI_USE_SDMA; 2563 } 2564 2565 if ((host->version >= SDHCI_SPEC_200) && 2566 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2567 host->flags |= SDHCI_USE_ADMA; 2568 2569 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2570 (host->flags & SDHCI_USE_ADMA)) { 2571 DBG("Disabling ADMA as it is marked broken\n"); 2572 host->flags &= ~SDHCI_USE_ADMA; 2573 } 2574 2575 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2576 if (host->ops->enable_dma) { 2577 if (host->ops->enable_dma(host)) { 2578 pr_warning("%s: No suitable DMA " 2579 "available. Falling back to PIO.\n", 2580 mmc_hostname(mmc)); 2581 host->flags &= 2582 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2583 } 2584 } 2585 } 2586 2587 if (host->flags & SDHCI_USE_ADMA) { 2588 /* 2589 * We need to allocate descriptors for all sg entries 2590 * (128) and potentially one alignment transfer for 2591 * each of those entries. 2592 */ 2593 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 2594 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2595 if (!host->adma_desc || !host->align_buffer) { 2596 kfree(host->adma_desc); 2597 kfree(host->align_buffer); 2598 pr_warning("%s: Unable to allocate ADMA " 2599 "buffers. Falling back to standard DMA.\n", 2600 mmc_hostname(mmc)); 2601 host->flags &= ~SDHCI_USE_ADMA; 2602 } 2603 } 2604 2605 /* 2606 * If we use DMA, then it's up to the caller to set the DMA 2607 * mask, but PIO does not need the hw shim so we set a new 2608 * mask here in that case. 2609 */ 2610 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2611 host->dma_mask = DMA_BIT_MASK(64); 2612 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2613 } 2614 2615 if (host->version >= SDHCI_SPEC_300) 2616 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2617 >> SDHCI_CLOCK_BASE_SHIFT; 2618 else 2619 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2620 >> SDHCI_CLOCK_BASE_SHIFT; 2621 2622 host->max_clk *= 1000000; 2623 if (host->max_clk == 0 || host->quirks & 2624 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2625 if (!host->ops->get_max_clock) { 2626 pr_err("%s: Hardware doesn't specify base clock " 2627 "frequency.\n", mmc_hostname(mmc)); 2628 return -ENODEV; 2629 } 2630 host->max_clk = host->ops->get_max_clock(host); 2631 } 2632 2633 /* 2634 * In case of Host Controller v3.00, find out whether clock 2635 * multiplier is supported. 2636 */ 2637 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2638 SDHCI_CLOCK_MUL_SHIFT; 2639 2640 /* 2641 * In case the value in Clock Multiplier is 0, then programmable 2642 * clock mode is not supported, otherwise the actual clock 2643 * multiplier is one more than the value of Clock Multiplier 2644 * in the Capabilities Register. 2645 */ 2646 if (host->clk_mul) 2647 host->clk_mul += 1; 2648 2649 /* 2650 * Set host parameters. 2651 */ 2652 mmc->ops = &sdhci_ops; 2653 mmc->f_max = host->max_clk; 2654 if (host->ops->get_min_clock) 2655 mmc->f_min = host->ops->get_min_clock(host); 2656 else if (host->version >= SDHCI_SPEC_300) { 2657 if (host->clk_mul) { 2658 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2659 mmc->f_max = host->max_clk * host->clk_mul; 2660 } else 2661 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2662 } else 2663 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2664 2665 host->timeout_clk = 2666 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2667 if (host->timeout_clk == 0) { 2668 if (host->ops->get_timeout_clock) { 2669 host->timeout_clk = host->ops->get_timeout_clock(host); 2670 } else if (!(host->quirks & 2671 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2672 pr_err("%s: Hardware doesn't specify timeout clock " 2673 "frequency.\n", mmc_hostname(mmc)); 2674 return -ENODEV; 2675 } 2676 } 2677 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2678 host->timeout_clk *= 1000; 2679 2680 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2681 host->timeout_clk = mmc->f_max / 1000; 2682 2683 mmc->max_discard_to = (1 << 27) / host->timeout_clk; 2684 2685 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2686 2687 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2688 host->flags |= SDHCI_AUTO_CMD12; 2689 2690 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2691 if ((host->version >= SDHCI_SPEC_300) && 2692 ((host->flags & SDHCI_USE_ADMA) || 2693 !(host->flags & SDHCI_USE_SDMA))) { 2694 host->flags |= SDHCI_AUTO_CMD23; 2695 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2696 } else { 2697 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2698 } 2699 2700 /* 2701 * A controller may support 8-bit width, but the board itself 2702 * might not have the pins brought out. Boards that support 2703 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2704 * their platform code before calling sdhci_add_host(), and we 2705 * won't assume 8-bit width for hosts without that CAP. 2706 */ 2707 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2708 mmc->caps |= MMC_CAP_4_BIT_DATA; 2709 2710 if (caps[0] & SDHCI_CAN_DO_HISPD) 2711 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2712 2713 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2714 mmc_card_is_removable(mmc)) 2715 mmc->caps |= MMC_CAP_NEEDS_POLL; 2716 2717 /* UHS-I mode(s) supported by the host controller. */ 2718 if (host->version >= SDHCI_SPEC_300) 2719 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2720 2721 /* SDR104 supports also implies SDR50 support */ 2722 if (caps[1] & SDHCI_SUPPORT_SDR104) 2723 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2724 else if (caps[1] & SDHCI_SUPPORT_SDR50) 2725 mmc->caps |= MMC_CAP_UHS_SDR50; 2726 2727 if (caps[1] & SDHCI_SUPPORT_DDR50) 2728 mmc->caps |= MMC_CAP_UHS_DDR50; 2729 2730 /* Does the host needs tuning for SDR50? */ 2731 if (caps[1] & SDHCI_USE_SDR50_TUNING) 2732 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 2733 2734 /* Driver Type(s) (A, C, D) supported by the host */ 2735 if (caps[1] & SDHCI_DRIVER_TYPE_A) 2736 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 2737 if (caps[1] & SDHCI_DRIVER_TYPE_C) 2738 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 2739 if (caps[1] & SDHCI_DRIVER_TYPE_D) 2740 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 2741 2742 /* 2743 * If Power Off Notify capability is enabled by the host, 2744 * set notify to short power off notify timeout value. 2745 */ 2746 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY) 2747 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT; 2748 else 2749 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE; 2750 2751 /* Initial value for re-tuning timer count */ 2752 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 2753 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 2754 2755 /* 2756 * In case Re-tuning Timer is not disabled, the actual value of 2757 * re-tuning timer will be 2 ^ (n - 1). 2758 */ 2759 if (host->tuning_count) 2760 host->tuning_count = 1 << (host->tuning_count - 1); 2761 2762 /* Re-tuning mode supported by the Host Controller */ 2763 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 2764 SDHCI_RETUNING_MODE_SHIFT; 2765 2766 ocr_avail = 0; 2767 /* 2768 * According to SD Host Controller spec v3.00, if the Host System 2769 * can afford more than 150mA, Host Driver should set XPC to 1. Also 2770 * the value is meaningful only if Voltage Support in the Capabilities 2771 * register is set. The actual current value is 4 times the register 2772 * value. 2773 */ 2774 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 2775 2776 if (caps[0] & SDHCI_CAN_VDD_330) { 2777 int max_current_330; 2778 2779 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 2780 2781 max_current_330 = ((max_current_caps & 2782 SDHCI_MAX_CURRENT_330_MASK) >> 2783 SDHCI_MAX_CURRENT_330_SHIFT) * 2784 SDHCI_MAX_CURRENT_MULTIPLIER; 2785 2786 if (max_current_330 > 150) 2787 mmc->caps |= MMC_CAP_SET_XPC_330; 2788 } 2789 if (caps[0] & SDHCI_CAN_VDD_300) { 2790 int max_current_300; 2791 2792 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 2793 2794 max_current_300 = ((max_current_caps & 2795 SDHCI_MAX_CURRENT_300_MASK) >> 2796 SDHCI_MAX_CURRENT_300_SHIFT) * 2797 SDHCI_MAX_CURRENT_MULTIPLIER; 2798 2799 if (max_current_300 > 150) 2800 mmc->caps |= MMC_CAP_SET_XPC_300; 2801 } 2802 if (caps[0] & SDHCI_CAN_VDD_180) { 2803 int max_current_180; 2804 2805 ocr_avail |= MMC_VDD_165_195; 2806 2807 max_current_180 = ((max_current_caps & 2808 SDHCI_MAX_CURRENT_180_MASK) >> 2809 SDHCI_MAX_CURRENT_180_SHIFT) * 2810 SDHCI_MAX_CURRENT_MULTIPLIER; 2811 2812 if (max_current_180 > 150) 2813 mmc->caps |= MMC_CAP_SET_XPC_180; 2814 2815 /* Maximum current capabilities of the host at 1.8V */ 2816 if (max_current_180 >= 800) 2817 mmc->caps |= MMC_CAP_MAX_CURRENT_800; 2818 else if (max_current_180 >= 600) 2819 mmc->caps |= MMC_CAP_MAX_CURRENT_600; 2820 else if (max_current_180 >= 400) 2821 mmc->caps |= MMC_CAP_MAX_CURRENT_400; 2822 else 2823 mmc->caps |= MMC_CAP_MAX_CURRENT_200; 2824 } 2825 2826 mmc->ocr_avail = ocr_avail; 2827 mmc->ocr_avail_sdio = ocr_avail; 2828 if (host->ocr_avail_sdio) 2829 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 2830 mmc->ocr_avail_sd = ocr_avail; 2831 if (host->ocr_avail_sd) 2832 mmc->ocr_avail_sd &= host->ocr_avail_sd; 2833 else /* normal SD controllers don't support 1.8V */ 2834 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 2835 mmc->ocr_avail_mmc = ocr_avail; 2836 if (host->ocr_avail_mmc) 2837 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 2838 2839 if (mmc->ocr_avail == 0) { 2840 pr_err("%s: Hardware doesn't report any " 2841 "support voltages.\n", mmc_hostname(mmc)); 2842 return -ENODEV; 2843 } 2844 2845 spin_lock_init(&host->lock); 2846 2847 /* 2848 * Maximum number of segments. Depends on if the hardware 2849 * can do scatter/gather or not. 2850 */ 2851 if (host->flags & SDHCI_USE_ADMA) 2852 mmc->max_segs = 128; 2853 else if (host->flags & SDHCI_USE_SDMA) 2854 mmc->max_segs = 1; 2855 else /* PIO */ 2856 mmc->max_segs = 128; 2857 2858 /* 2859 * Maximum number of sectors in one transfer. Limited by DMA boundary 2860 * size (512KiB). 2861 */ 2862 mmc->max_req_size = 524288; 2863 2864 /* 2865 * Maximum segment size. Could be one segment with the maximum number 2866 * of bytes. When doing hardware scatter/gather, each entry cannot 2867 * be larger than 64 KiB though. 2868 */ 2869 if (host->flags & SDHCI_USE_ADMA) { 2870 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 2871 mmc->max_seg_size = 65535; 2872 else 2873 mmc->max_seg_size = 65536; 2874 } else { 2875 mmc->max_seg_size = mmc->max_req_size; 2876 } 2877 2878 /* 2879 * Maximum block size. This varies from controller to controller and 2880 * is specified in the capabilities register. 2881 */ 2882 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 2883 mmc->max_blk_size = 2; 2884 } else { 2885 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 2886 SDHCI_MAX_BLOCK_SHIFT; 2887 if (mmc->max_blk_size >= 3) { 2888 pr_warning("%s: Invalid maximum block size, " 2889 "assuming 512 bytes\n", mmc_hostname(mmc)); 2890 mmc->max_blk_size = 0; 2891 } 2892 } 2893 2894 mmc->max_blk_size = 512 << mmc->max_blk_size; 2895 2896 /* 2897 * Maximum block count. 2898 */ 2899 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 2900 2901 /* 2902 * Init tasklets. 2903 */ 2904 tasklet_init(&host->card_tasklet, 2905 sdhci_tasklet_card, (unsigned long)host); 2906 tasklet_init(&host->finish_tasklet, 2907 sdhci_tasklet_finish, (unsigned long)host); 2908 2909 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 2910 2911 if (host->version >= SDHCI_SPEC_300) { 2912 init_waitqueue_head(&host->buf_ready_int); 2913 2914 /* Initialize re-tuning timer */ 2915 init_timer(&host->tuning_timer); 2916 host->tuning_timer.data = (unsigned long)host; 2917 host->tuning_timer.function = sdhci_tuning_timer; 2918 } 2919 2920 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2921 mmc_hostname(mmc), host); 2922 if (ret) 2923 goto untasklet; 2924 2925 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 2926 if (IS_ERR(host->vmmc)) { 2927 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); 2928 host->vmmc = NULL; 2929 } else { 2930 regulator_enable(host->vmmc); 2931 } 2932 2933 sdhci_init(host, 0); 2934 2935 #ifdef CONFIG_MMC_DEBUG 2936 sdhci_dumpregs(host); 2937 #endif 2938 2939 #ifdef SDHCI_USE_LEDS_CLASS 2940 snprintf(host->led_name, sizeof(host->led_name), 2941 "%s::", mmc_hostname(mmc)); 2942 host->led.name = host->led_name; 2943 host->led.brightness = LED_OFF; 2944 host->led.default_trigger = mmc_hostname(mmc); 2945 host->led.brightness_set = sdhci_led_control; 2946 2947 ret = led_classdev_register(mmc_dev(mmc), &host->led); 2948 if (ret) 2949 goto reset; 2950 #endif 2951 2952 mmiowb(); 2953 2954 mmc_add_host(mmc); 2955 2956 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 2957 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 2958 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 2959 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 2960 2961 sdhci_enable_card_detection(host); 2962 2963 return 0; 2964 2965 #ifdef SDHCI_USE_LEDS_CLASS 2966 reset: 2967 sdhci_reset(host, SDHCI_RESET_ALL); 2968 free_irq(host->irq, host); 2969 #endif 2970 untasklet: 2971 tasklet_kill(&host->card_tasklet); 2972 tasklet_kill(&host->finish_tasklet); 2973 2974 return ret; 2975 } 2976 2977 EXPORT_SYMBOL_GPL(sdhci_add_host); 2978 2979 void sdhci_remove_host(struct sdhci_host *host, int dead) 2980 { 2981 unsigned long flags; 2982 2983 if (dead) { 2984 spin_lock_irqsave(&host->lock, flags); 2985 2986 host->flags |= SDHCI_DEVICE_DEAD; 2987 2988 if (host->mrq) { 2989 pr_err("%s: Controller removed during " 2990 " transfer!\n", mmc_hostname(host->mmc)); 2991 2992 host->mrq->cmd->error = -ENOMEDIUM; 2993 tasklet_schedule(&host->finish_tasklet); 2994 } 2995 2996 spin_unlock_irqrestore(&host->lock, flags); 2997 } 2998 2999 sdhci_disable_card_detection(host); 3000 3001 mmc_remove_host(host->mmc); 3002 3003 #ifdef SDHCI_USE_LEDS_CLASS 3004 led_classdev_unregister(&host->led); 3005 #endif 3006 3007 if (!dead) 3008 sdhci_reset(host, SDHCI_RESET_ALL); 3009 3010 free_irq(host->irq, host); 3011 3012 del_timer_sync(&host->timer); 3013 if (host->version >= SDHCI_SPEC_300) 3014 del_timer_sync(&host->tuning_timer); 3015 3016 tasklet_kill(&host->card_tasklet); 3017 tasklet_kill(&host->finish_tasklet); 3018 3019 if (host->vmmc) { 3020 regulator_disable(host->vmmc); 3021 regulator_put(host->vmmc); 3022 } 3023 3024 kfree(host->adma_desc); 3025 kfree(host->align_buffer); 3026 3027 host->adma_desc = NULL; 3028 host->align_buffer = NULL; 3029 } 3030 3031 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3032 3033 void sdhci_free_host(struct sdhci_host *host) 3034 { 3035 mmc_free_host(host->mmc); 3036 } 3037 3038 EXPORT_SYMBOL_GPL(sdhci_free_host); 3039 3040 /*****************************************************************************\ 3041 * * 3042 * Driver init/exit * 3043 * * 3044 \*****************************************************************************/ 3045 3046 static int __init sdhci_drv_init(void) 3047 { 3048 pr_info(DRIVER_NAME 3049 ": Secure Digital Host Controller Interface driver\n"); 3050 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3051 3052 return 0; 3053 } 3054 3055 static void __exit sdhci_drv_exit(void) 3056 { 3057 } 3058 3059 module_init(sdhci_drv_init); 3060 module_exit(sdhci_drv_exit); 3061 3062 module_param(debug_quirks, uint, 0444); 3063 module_param(debug_quirks2, uint, 0444); 3064 3065 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3066 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3067 MODULE_LICENSE("GPL"); 3068 3069 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3070 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3071