xref: /openbmc/linux/drivers/mmc/host/sdhci-pxav3.c (revision c915568d99f12898aea4e15845cf891a8b5cc575)
1a702c8abSZhangfei Gao /*
2a702c8abSZhangfei Gao  * Copyright (C) 2010 Marvell International Ltd.
3a702c8abSZhangfei Gao  *		Zhangfei Gao <zhangfei.gao@marvell.com>
4a702c8abSZhangfei Gao  *		Kevin Wang <dwang4@marvell.com>
5a702c8abSZhangfei Gao  *		Mingwei Wang <mwwang@marvell.com>
6a702c8abSZhangfei Gao  *		Philip Rakity <prakity@marvell.com>
7a702c8abSZhangfei Gao  *		Mark Brown <markb@marvell.com>
8a702c8abSZhangfei Gao  *
9a702c8abSZhangfei Gao  * This software is licensed under the terms of the GNU General Public
10a702c8abSZhangfei Gao  * License version 2, as published by the Free Software Foundation, and
11a702c8abSZhangfei Gao  * may be copied, distributed, and modified under those terms.
12a702c8abSZhangfei Gao  *
13a702c8abSZhangfei Gao  * This program is distributed in the hope that it will be useful,
14a702c8abSZhangfei Gao  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15a702c8abSZhangfei Gao  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16a702c8abSZhangfei Gao  * GNU General Public License for more details.
17a702c8abSZhangfei Gao  *
18a702c8abSZhangfei Gao  */
19a702c8abSZhangfei Gao #include <linux/err.h>
20a702c8abSZhangfei Gao #include <linux/init.h>
21a702c8abSZhangfei Gao #include <linux/platform_device.h>
22a702c8abSZhangfei Gao #include <linux/clk.h>
23a702c8abSZhangfei Gao #include <linux/io.h>
24a702c8abSZhangfei Gao #include <linux/gpio.h>
25a702c8abSZhangfei Gao #include <linux/mmc/card.h>
26a702c8abSZhangfei Gao #include <linux/mmc/host.h>
278f63795cSChris Ball #include <linux/mmc/slot-gpio.h>
28bfed345eSZhangfei Gao #include <linux/platform_data/pxa_sdhci.h>
29a702c8abSZhangfei Gao #include <linux/slab.h>
30a702c8abSZhangfei Gao #include <linux/delay.h>
3188b47679SPaul Gortmaker #include <linux/module.h>
32b650352dSChris Ball #include <linux/of.h>
33b650352dSChris Ball #include <linux/of_device.h>
348f63795cSChris Ball #include <linux/of_gpio.h>
35bb691ae4SKevin Liu #include <linux/pm.h>
36bb691ae4SKevin Liu #include <linux/pm_runtime.h>
37b650352dSChris Ball 
38a702c8abSZhangfei Gao #include "sdhci.h"
39a702c8abSZhangfei Gao #include "sdhci-pltfm.h"
40a702c8abSZhangfei Gao 
41bb691ae4SKevin Liu #define PXAV3_RPM_DELAY_MS     50
42bb691ae4SKevin Liu 
43a702c8abSZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP		0x10A
44a702c8abSZhangfei Gao #define SDCLK_SEL	0x100
45a702c8abSZhangfei Gao #define SDCLK_DELAY_SHIFT	9
46a702c8abSZhangfei Gao #define SDCLK_DELAY_MASK	0x1f
47a702c8abSZhangfei Gao 
48a702c8abSZhangfei Gao #define SD_CFG_FIFO_PARAM       0x100
49a702c8abSZhangfei Gao #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
50a702c8abSZhangfei Gao #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
51a702c8abSZhangfei Gao #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
52a702c8abSZhangfei Gao 
53a702c8abSZhangfei Gao #define SD_SPI_MODE          0x108
54a702c8abSZhangfei Gao #define SD_CE_ATA_1          0x10C
55a702c8abSZhangfei Gao 
56a702c8abSZhangfei Gao #define SD_CE_ATA_2          0x10E
57a702c8abSZhangfei Gao #define SDCE_MISC_INT		(1<<2)
58a702c8abSZhangfei Gao #define SDCE_MISC_INT_EN	(1<<1)
59a702c8abSZhangfei Gao 
60a702c8abSZhangfei Gao static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
61a702c8abSZhangfei Gao {
62a702c8abSZhangfei Gao 	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
63a702c8abSZhangfei Gao 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
64a702c8abSZhangfei Gao 
65a702c8abSZhangfei Gao 	if (mask == SDHCI_RESET_ALL) {
66a702c8abSZhangfei Gao 		/*
67a702c8abSZhangfei Gao 		 * tune timing of read data/command when crc error happen
68a702c8abSZhangfei Gao 		 * no performance impact
69a702c8abSZhangfei Gao 		 */
70a702c8abSZhangfei Gao 		if (pdata && 0 != pdata->clk_delay_cycles) {
71a702c8abSZhangfei Gao 			u16 tmp;
72a702c8abSZhangfei Gao 
73a702c8abSZhangfei Gao 			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
74a702c8abSZhangfei Gao 			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
75a702c8abSZhangfei Gao 				<< SDCLK_DELAY_SHIFT;
76a702c8abSZhangfei Gao 			tmp |= SDCLK_SEL;
77a702c8abSZhangfei Gao 			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
78a702c8abSZhangfei Gao 		}
79a702c8abSZhangfei Gao 	}
80a702c8abSZhangfei Gao }
81a702c8abSZhangfei Gao 
82a702c8abSZhangfei Gao #define MAX_WAIT_COUNT 5
83a702c8abSZhangfei Gao static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
84a702c8abSZhangfei Gao {
85a702c8abSZhangfei Gao 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
86a702c8abSZhangfei Gao 	struct sdhci_pxa *pxa = pltfm_host->priv;
87a702c8abSZhangfei Gao 	u16 tmp;
88a702c8abSZhangfei Gao 	int count;
89a702c8abSZhangfei Gao 
90a702c8abSZhangfei Gao 	if (pxa->power_mode == MMC_POWER_UP
91a702c8abSZhangfei Gao 			&& power_mode == MMC_POWER_ON) {
92a702c8abSZhangfei Gao 
93a702c8abSZhangfei Gao 		dev_dbg(mmc_dev(host->mmc),
94a702c8abSZhangfei Gao 				"%s: slot->power_mode = %d,"
95a702c8abSZhangfei Gao 				"ios->power_mode = %d\n",
96a702c8abSZhangfei Gao 				__func__,
97a702c8abSZhangfei Gao 				pxa->power_mode,
98a702c8abSZhangfei Gao 				power_mode);
99a702c8abSZhangfei Gao 
100a702c8abSZhangfei Gao 		/* set we want notice of when 74 clocks are sent */
101a702c8abSZhangfei Gao 		tmp = readw(host->ioaddr + SD_CE_ATA_2);
102a702c8abSZhangfei Gao 		tmp |= SDCE_MISC_INT_EN;
103a702c8abSZhangfei Gao 		writew(tmp, host->ioaddr + SD_CE_ATA_2);
104a702c8abSZhangfei Gao 
105a702c8abSZhangfei Gao 		/* start sending the 74 clocks */
106a702c8abSZhangfei Gao 		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
107a702c8abSZhangfei Gao 		tmp |= SDCFG_GEN_PAD_CLK_ON;
108a702c8abSZhangfei Gao 		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
109a702c8abSZhangfei Gao 
110a702c8abSZhangfei Gao 		/* slowest speed is about 100KHz or 10usec per clock */
111a702c8abSZhangfei Gao 		udelay(740);
112a702c8abSZhangfei Gao 		count = 0;
113a702c8abSZhangfei Gao 
114a702c8abSZhangfei Gao 		while (count++ < MAX_WAIT_COUNT) {
115a702c8abSZhangfei Gao 			if ((readw(host->ioaddr + SD_CE_ATA_2)
116a702c8abSZhangfei Gao 						& SDCE_MISC_INT) == 0)
117a702c8abSZhangfei Gao 				break;
118a702c8abSZhangfei Gao 			udelay(10);
119a702c8abSZhangfei Gao 		}
120a702c8abSZhangfei Gao 
121a702c8abSZhangfei Gao 		if (count == MAX_WAIT_COUNT)
122a702c8abSZhangfei Gao 			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
123a702c8abSZhangfei Gao 
124a702c8abSZhangfei Gao 		/* clear the interrupt bit if posted */
125a702c8abSZhangfei Gao 		tmp = readw(host->ioaddr + SD_CE_ATA_2);
126a702c8abSZhangfei Gao 		tmp |= SDCE_MISC_INT;
127a702c8abSZhangfei Gao 		writew(tmp, host->ioaddr + SD_CE_ATA_2);
128a702c8abSZhangfei Gao 	}
129a702c8abSZhangfei Gao 	pxa->power_mode = power_mode;
130a702c8abSZhangfei Gao }
131a702c8abSZhangfei Gao 
132a702c8abSZhangfei Gao static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
133a702c8abSZhangfei Gao {
134a702c8abSZhangfei Gao 	u16 ctrl_2;
135a702c8abSZhangfei Gao 
136a702c8abSZhangfei Gao 	/*
137a702c8abSZhangfei Gao 	 * Set V18_EN -- UHS modes do not work without this.
138a702c8abSZhangfei Gao 	 * does not change signaling voltage
139a702c8abSZhangfei Gao 	 */
140a702c8abSZhangfei Gao 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
141a702c8abSZhangfei Gao 
142a702c8abSZhangfei Gao 	/* Select Bus Speed Mode for host */
143a702c8abSZhangfei Gao 	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
144a702c8abSZhangfei Gao 	switch (uhs) {
145a702c8abSZhangfei Gao 	case MMC_TIMING_UHS_SDR12:
146a702c8abSZhangfei Gao 		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
147a702c8abSZhangfei Gao 		break;
148a702c8abSZhangfei Gao 	case MMC_TIMING_UHS_SDR25:
149a702c8abSZhangfei Gao 		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
150a702c8abSZhangfei Gao 		break;
151a702c8abSZhangfei Gao 	case MMC_TIMING_UHS_SDR50:
152a702c8abSZhangfei Gao 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
153a702c8abSZhangfei Gao 		break;
154a702c8abSZhangfei Gao 	case MMC_TIMING_UHS_SDR104:
155a702c8abSZhangfei Gao 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
156a702c8abSZhangfei Gao 		break;
157a702c8abSZhangfei Gao 	case MMC_TIMING_UHS_DDR50:
158a702c8abSZhangfei Gao 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
159a702c8abSZhangfei Gao 		break;
160a702c8abSZhangfei Gao 	}
161a702c8abSZhangfei Gao 
162a702c8abSZhangfei Gao 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
163a702c8abSZhangfei Gao 	dev_dbg(mmc_dev(host->mmc),
164a702c8abSZhangfei Gao 		"%s uhs = %d, ctrl_2 = %04X\n",
165a702c8abSZhangfei Gao 		__func__, uhs, ctrl_2);
166a702c8abSZhangfei Gao 
167a702c8abSZhangfei Gao 	return 0;
168a702c8abSZhangfei Gao }
169a702c8abSZhangfei Gao 
170*c915568dSLars-Peter Clausen static const struct sdhci_ops pxav3_sdhci_ops = {
171a702c8abSZhangfei Gao 	.platform_reset_exit = pxav3_set_private_registers,
172a702c8abSZhangfei Gao 	.set_uhs_signaling = pxav3_set_uhs_signaling,
173a702c8abSZhangfei Gao 	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
174d005d943SLars-Peter Clausen 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
175a702c8abSZhangfei Gao };
176a702c8abSZhangfei Gao 
177b650352dSChris Ball #ifdef CONFIG_OF
178b650352dSChris Ball static const struct of_device_id sdhci_pxav3_of_match[] = {
179b650352dSChris Ball 	{
180b650352dSChris Ball 		.compatible = "mrvl,pxav3-mmc",
181b650352dSChris Ball 	},
182b650352dSChris Ball 	{},
183b650352dSChris Ball };
184b650352dSChris Ball MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
185b650352dSChris Ball 
186b650352dSChris Ball static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
187b650352dSChris Ball {
188b650352dSChris Ball 	struct sdhci_pxa_platdata *pdata;
189b650352dSChris Ball 	struct device_node *np = dev->of_node;
190b650352dSChris Ball 	u32 bus_width;
191b650352dSChris Ball 	u32 clk_delay_cycles;
1928f63795cSChris Ball 	enum of_gpio_flags gpio_flags;
193b650352dSChris Ball 
194b650352dSChris Ball 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
195b650352dSChris Ball 	if (!pdata)
196b650352dSChris Ball 		return NULL;
197b650352dSChris Ball 
198b650352dSChris Ball 	if (of_find_property(np, "non-removable", NULL))
199b650352dSChris Ball 		pdata->flags |= PXA_FLAG_CARD_PERMANENT;
200b650352dSChris Ball 
201b650352dSChris Ball 	of_property_read_u32(np, "bus-width", &bus_width);
202b650352dSChris Ball 	if (bus_width == 8)
203b650352dSChris Ball 		pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
204b650352dSChris Ball 
205b650352dSChris Ball 	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
206b650352dSChris Ball 	if (clk_delay_cycles > 0)
207b650352dSChris Ball 		pdata->clk_delay_cycles = clk_delay_cycles;
208b650352dSChris Ball 
2098f63795cSChris Ball 	pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags);
2108f63795cSChris Ball 	if (gpio_flags != OF_GPIO_ACTIVE_LOW)
2118f63795cSChris Ball 		pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
2128f63795cSChris Ball 
213b650352dSChris Ball 	return pdata;
214b650352dSChris Ball }
215b650352dSChris Ball #else
216b650352dSChris Ball static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
217b650352dSChris Ball {
218b650352dSChris Ball 	return NULL;
219b650352dSChris Ball }
220b650352dSChris Ball #endif
221b650352dSChris Ball 
222c3be1efdSBill Pemberton static int sdhci_pxav3_probe(struct platform_device *pdev)
223a702c8abSZhangfei Gao {
224a702c8abSZhangfei Gao 	struct sdhci_pltfm_host *pltfm_host;
225a702c8abSZhangfei Gao 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
226a702c8abSZhangfei Gao 	struct device *dev = &pdev->dev;
227a702c8abSZhangfei Gao 	struct sdhci_host *host = NULL;
228a702c8abSZhangfei Gao 	struct sdhci_pxa *pxa = NULL;
229b650352dSChris Ball 	const struct of_device_id *match;
230b650352dSChris Ball 
231a702c8abSZhangfei Gao 	int ret;
232a702c8abSZhangfei Gao 	struct clk *clk;
233a702c8abSZhangfei Gao 
234a702c8abSZhangfei Gao 	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
235a702c8abSZhangfei Gao 	if (!pxa)
236a702c8abSZhangfei Gao 		return -ENOMEM;
237a702c8abSZhangfei Gao 
238a702c8abSZhangfei Gao 	host = sdhci_pltfm_init(pdev, NULL);
239a702c8abSZhangfei Gao 	if (IS_ERR(host)) {
240a702c8abSZhangfei Gao 		kfree(pxa);
241a702c8abSZhangfei Gao 		return PTR_ERR(host);
242a702c8abSZhangfei Gao 	}
243a702c8abSZhangfei Gao 	pltfm_host = sdhci_priv(host);
244a702c8abSZhangfei Gao 	pltfm_host->priv = pxa;
245a702c8abSZhangfei Gao 
246164378efSChao Xie 	clk = clk_get(dev, NULL);
247a702c8abSZhangfei Gao 	if (IS_ERR(clk)) {
248a702c8abSZhangfei Gao 		dev_err(dev, "failed to get io clock\n");
249a702c8abSZhangfei Gao 		ret = PTR_ERR(clk);
250a702c8abSZhangfei Gao 		goto err_clk_get;
251a702c8abSZhangfei Gao 	}
252a702c8abSZhangfei Gao 	pltfm_host->clk = clk;
253164378efSChao Xie 	clk_prepare_enable(clk);
254a702c8abSZhangfei Gao 
255a702c8abSZhangfei Gao 	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
256606a15e4SPhilip Rakity 		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
25735d110e7SKevin Liu 		| SDHCI_QUIRK_32BIT_ADMA_SIZE
25835d110e7SKevin Liu 		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
259a702c8abSZhangfei Gao 
260a702c8abSZhangfei Gao 	/* enable 1/8V DDR capable */
261a702c8abSZhangfei Gao 	host->mmc->caps |= MMC_CAP_1_8V_DDR;
262a702c8abSZhangfei Gao 
263b650352dSChris Ball 	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
264b650352dSChris Ball 	if (match)
265b650352dSChris Ball 		pdata = pxav3_get_mmc_pdata(dev);
266b650352dSChris Ball 
267a702c8abSZhangfei Gao 	if (pdata) {
268a702c8abSZhangfei Gao 		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
269a702c8abSZhangfei Gao 			/* on-chip device */
270a702c8abSZhangfei Gao 			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
271a702c8abSZhangfei Gao 			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
272a702c8abSZhangfei Gao 		}
273a702c8abSZhangfei Gao 
274a702c8abSZhangfei Gao 		/* If slot design supports 8 bit data, indicate this to MMC. */
275a702c8abSZhangfei Gao 		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
276a702c8abSZhangfei Gao 			host->mmc->caps |= MMC_CAP_8_BIT_DATA;
277a702c8abSZhangfei Gao 
278a702c8abSZhangfei Gao 		if (pdata->quirks)
279a702c8abSZhangfei Gao 			host->quirks |= pdata->quirks;
2807c52d7bbSKevin Liu 		if (pdata->quirks2)
2817c52d7bbSKevin Liu 			host->quirks2 |= pdata->quirks2;
282a702c8abSZhangfei Gao 		if (pdata->host_caps)
283a702c8abSZhangfei Gao 			host->mmc->caps |= pdata->host_caps;
2848f63795cSChris Ball 		if (pdata->host_caps2)
2858f63795cSChris Ball 			host->mmc->caps2 |= pdata->host_caps2;
286a702c8abSZhangfei Gao 		if (pdata->pm_caps)
287a702c8abSZhangfei Gao 			host->mmc->pm_caps |= pdata->pm_caps;
2888f63795cSChris Ball 
2898f63795cSChris Ball 		if (gpio_is_valid(pdata->ext_cd_gpio)) {
2908f63795cSChris Ball 			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
2918f63795cSChris Ball 			if (ret) {
2928f63795cSChris Ball 				dev_err(mmc_dev(host->mmc),
2938f63795cSChris Ball 					"failed to allocate card detect gpio\n");
2948f63795cSChris Ball 				goto err_cd_req;
2958f63795cSChris Ball 			}
2968f63795cSChris Ball 		}
297a702c8abSZhangfei Gao 	}
298a702c8abSZhangfei Gao 
299a702c8abSZhangfei Gao 	host->ops = &pxav3_sdhci_ops;
300a702c8abSZhangfei Gao 
301f4f24adeSChris Ball 	sdhci_get_of_property(pdev);
302f4f24adeSChris Ball 
303bb691ae4SKevin Liu 	pm_runtime_set_active(&pdev->dev);
304bb691ae4SKevin Liu 	pm_runtime_enable(&pdev->dev);
305bb691ae4SKevin Liu 	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
306bb691ae4SKevin Liu 	pm_runtime_use_autosuspend(&pdev->dev);
307bb691ae4SKevin Liu 	pm_suspend_ignore_children(&pdev->dev, 1);
308bb691ae4SKevin Liu 	pm_runtime_get_noresume(&pdev->dev);
309bb691ae4SKevin Liu 
310a702c8abSZhangfei Gao 	ret = sdhci_add_host(host);
311a702c8abSZhangfei Gao 	if (ret) {
312a702c8abSZhangfei Gao 		dev_err(&pdev->dev, "failed to add host\n");
313bb691ae4SKevin Liu 		pm_runtime_forbid(&pdev->dev);
314bb691ae4SKevin Liu 		pm_runtime_disable(&pdev->dev);
315a702c8abSZhangfei Gao 		goto err_add_host;
316a702c8abSZhangfei Gao 	}
317a702c8abSZhangfei Gao 
318a702c8abSZhangfei Gao 	platform_set_drvdata(pdev, host);
319a702c8abSZhangfei Gao 
320740b7a44SKevin Liu 	if (pdata->pm_caps & MMC_PM_KEEP_POWER) {
321740b7a44SKevin Liu 		device_init_wakeup(&pdev->dev, 1);
322740b7a44SKevin Liu 		host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
323740b7a44SKevin Liu 	} else {
324740b7a44SKevin Liu 		device_init_wakeup(&pdev->dev, 0);
325740b7a44SKevin Liu 	}
326740b7a44SKevin Liu 
327bb691ae4SKevin Liu 	pm_runtime_put_autosuspend(&pdev->dev);
328bb691ae4SKevin Liu 
329a702c8abSZhangfei Gao 	return 0;
330a702c8abSZhangfei Gao 
331a702c8abSZhangfei Gao err_add_host:
332164378efSChao Xie 	clk_disable_unprepare(clk);
333a702c8abSZhangfei Gao 	clk_put(clk);
3348f63795cSChris Ball err_cd_req:
335a702c8abSZhangfei Gao err_clk_get:
336a702c8abSZhangfei Gao 	sdhci_pltfm_free(pdev);
337a702c8abSZhangfei Gao 	kfree(pxa);
338a702c8abSZhangfei Gao 	return ret;
339a702c8abSZhangfei Gao }
340a702c8abSZhangfei Gao 
3416e0ee714SBill Pemberton static int sdhci_pxav3_remove(struct platform_device *pdev)
342a702c8abSZhangfei Gao {
343a702c8abSZhangfei Gao 	struct sdhci_host *host = platform_get_drvdata(pdev);
344a702c8abSZhangfei Gao 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
345a702c8abSZhangfei Gao 	struct sdhci_pxa *pxa = pltfm_host->priv;
346a702c8abSZhangfei Gao 
347bb691ae4SKevin Liu 	pm_runtime_get_sync(&pdev->dev);
348a702c8abSZhangfei Gao 	sdhci_remove_host(host, 1);
349bb691ae4SKevin Liu 	pm_runtime_disable(&pdev->dev);
350a702c8abSZhangfei Gao 
351164378efSChao Xie 	clk_disable_unprepare(pltfm_host->clk);
352a702c8abSZhangfei Gao 	clk_put(pltfm_host->clk);
3538f63795cSChris Ball 
354a702c8abSZhangfei Gao 	sdhci_pltfm_free(pdev);
355a702c8abSZhangfei Gao 	kfree(pxa);
356a702c8abSZhangfei Gao 
357a702c8abSZhangfei Gao 	platform_set_drvdata(pdev, NULL);
358a702c8abSZhangfei Gao 
359a702c8abSZhangfei Gao 	return 0;
360a702c8abSZhangfei Gao }
361a702c8abSZhangfei Gao 
362bb691ae4SKevin Liu #ifdef CONFIG_PM_SLEEP
363bb691ae4SKevin Liu static int sdhci_pxav3_suspend(struct device *dev)
364bb691ae4SKevin Liu {
365bb691ae4SKevin Liu 	int ret;
366bb691ae4SKevin Liu 	struct sdhci_host *host = dev_get_drvdata(dev);
367bb691ae4SKevin Liu 
368bb691ae4SKevin Liu 	pm_runtime_get_sync(dev);
369bb691ae4SKevin Liu 	ret = sdhci_suspend_host(host);
370bb691ae4SKevin Liu 	pm_runtime_mark_last_busy(dev);
371bb691ae4SKevin Liu 	pm_runtime_put_autosuspend(dev);
372bb691ae4SKevin Liu 
373bb691ae4SKevin Liu 	return ret;
374bb691ae4SKevin Liu }
375bb691ae4SKevin Liu 
376bb691ae4SKevin Liu static int sdhci_pxav3_resume(struct device *dev)
377bb691ae4SKevin Liu {
378bb691ae4SKevin Liu 	int ret;
379bb691ae4SKevin Liu 	struct sdhci_host *host = dev_get_drvdata(dev);
380bb691ae4SKevin Liu 
381bb691ae4SKevin Liu 	pm_runtime_get_sync(dev);
382bb691ae4SKevin Liu 	ret = sdhci_resume_host(host);
383bb691ae4SKevin Liu 	pm_runtime_mark_last_busy(dev);
384bb691ae4SKevin Liu 	pm_runtime_put_autosuspend(dev);
385bb691ae4SKevin Liu 
386bb691ae4SKevin Liu 	return ret;
387bb691ae4SKevin Liu }
388bb691ae4SKevin Liu #endif
389bb691ae4SKevin Liu 
390bb691ae4SKevin Liu #ifdef CONFIG_PM_RUNTIME
391bb691ae4SKevin Liu static int sdhci_pxav3_runtime_suspend(struct device *dev)
392bb691ae4SKevin Liu {
393bb691ae4SKevin Liu 	struct sdhci_host *host = dev_get_drvdata(dev);
394bb691ae4SKevin Liu 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
395bb691ae4SKevin Liu 	unsigned long flags;
396bb691ae4SKevin Liu 
397bb691ae4SKevin Liu 	if (pltfm_host->clk) {
398bb691ae4SKevin Liu 		spin_lock_irqsave(&host->lock, flags);
399bb691ae4SKevin Liu 		host->runtime_suspended = true;
400bb691ae4SKevin Liu 		spin_unlock_irqrestore(&host->lock, flags);
401bb691ae4SKevin Liu 
402bb691ae4SKevin Liu 		clk_disable_unprepare(pltfm_host->clk);
403bb691ae4SKevin Liu 	}
404bb691ae4SKevin Liu 
405bb691ae4SKevin Liu 	return 0;
406bb691ae4SKevin Liu }
407bb691ae4SKevin Liu 
408bb691ae4SKevin Liu static int sdhci_pxav3_runtime_resume(struct device *dev)
409bb691ae4SKevin Liu {
410bb691ae4SKevin Liu 	struct sdhci_host *host = dev_get_drvdata(dev);
411bb691ae4SKevin Liu 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
412bb691ae4SKevin Liu 	unsigned long flags;
413bb691ae4SKevin Liu 
414bb691ae4SKevin Liu 	if (pltfm_host->clk) {
415bb691ae4SKevin Liu 		clk_prepare_enable(pltfm_host->clk);
416bb691ae4SKevin Liu 
417bb691ae4SKevin Liu 		spin_lock_irqsave(&host->lock, flags);
418bb691ae4SKevin Liu 		host->runtime_suspended = false;
419bb691ae4SKevin Liu 		spin_unlock_irqrestore(&host->lock, flags);
420bb691ae4SKevin Liu 	}
421bb691ae4SKevin Liu 
422bb691ae4SKevin Liu 	return 0;
423bb691ae4SKevin Liu }
424bb691ae4SKevin Liu #endif
425bb691ae4SKevin Liu 
426bb691ae4SKevin Liu #ifdef CONFIG_PM
427bb691ae4SKevin Liu static const struct dev_pm_ops sdhci_pxav3_pmops = {
428bb691ae4SKevin Liu 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
429bb691ae4SKevin Liu 	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
430bb691ae4SKevin Liu 		sdhci_pxav3_runtime_resume, NULL)
431bb691ae4SKevin Liu };
432bb691ae4SKevin Liu 
433bb691ae4SKevin Liu #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
434bb691ae4SKevin Liu 
435bb691ae4SKevin Liu #else
436bb691ae4SKevin Liu #define SDHCI_PXAV3_PMOPS NULL
437bb691ae4SKevin Liu #endif
438bb691ae4SKevin Liu 
439a702c8abSZhangfei Gao static struct platform_driver sdhci_pxav3_driver = {
440a702c8abSZhangfei Gao 	.driver		= {
441a702c8abSZhangfei Gao 		.name	= "sdhci-pxav3",
442b650352dSChris Ball #ifdef CONFIG_OF
443b650352dSChris Ball 		.of_match_table = sdhci_pxav3_of_match,
444b650352dSChris Ball #endif
445a702c8abSZhangfei Gao 		.owner	= THIS_MODULE,
446bb691ae4SKevin Liu 		.pm	= SDHCI_PXAV3_PMOPS,
447a702c8abSZhangfei Gao 	},
448a702c8abSZhangfei Gao 	.probe		= sdhci_pxav3_probe,
4490433c143SBill Pemberton 	.remove		= sdhci_pxav3_remove,
450a702c8abSZhangfei Gao };
451a702c8abSZhangfei Gao 
452d1f81a64SAxel Lin module_platform_driver(sdhci_pxav3_driver);
453a702c8abSZhangfei Gao 
454a702c8abSZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav3");
455a702c8abSZhangfei Gao MODULE_AUTHOR("Marvell International Ltd.");
456a702c8abSZhangfei Gao MODULE_LICENSE("GPL v2");
457a702c8abSZhangfei Gao 
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