1 /* 2 * SN Platform GRU Driver 3 * 4 * FAULT HANDLER FOR GRU DETECTED TLB MISSES 5 * 6 * This file contains code that handles TLB misses within the GRU. 7 * These misses are reported either via interrupts or user polling of 8 * the user CB. 9 * 10 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 27 #include <linux/kernel.h> 28 #include <linux/errno.h> 29 #include <linux/spinlock.h> 30 #include <linux/mm.h> 31 #include <linux/hugetlb.h> 32 #include <linux/device.h> 33 #include <linux/io.h> 34 #include <linux/uaccess.h> 35 #include <linux/security.h> 36 #include <asm/pgtable.h> 37 #include "gru.h" 38 #include "grutables.h" 39 #include "grulib.h" 40 #include "gru_instructions.h" 41 #include <asm/uv/uv_hub.h> 42 43 /* 44 * Test if a physical address is a valid GRU GSEG address 45 */ 46 static inline int is_gru_paddr(unsigned long paddr) 47 { 48 return paddr >= gru_start_paddr && paddr < gru_end_paddr; 49 } 50 51 /* 52 * Find the vma of a GRU segment. Caller must hold mmap_sem. 53 */ 54 struct vm_area_struct *gru_find_vma(unsigned long vaddr) 55 { 56 struct vm_area_struct *vma; 57 58 vma = find_vma(current->mm, vaddr); 59 if (vma && vma->vm_start <= vaddr && vma->vm_ops == &gru_vm_ops) 60 return vma; 61 return NULL; 62 } 63 64 /* 65 * Find and lock the gts that contains the specified user vaddr. 66 * 67 * Returns: 68 * - *gts with the mmap_sem locked for read and the GTS locked. 69 * - NULL if vaddr invalid OR is not a valid GSEG vaddr. 70 */ 71 72 static struct gru_thread_state *gru_find_lock_gts(unsigned long vaddr) 73 { 74 struct mm_struct *mm = current->mm; 75 struct vm_area_struct *vma; 76 struct gru_thread_state *gts = NULL; 77 78 down_read(&mm->mmap_sem); 79 vma = gru_find_vma(vaddr); 80 if (vma) 81 gts = gru_find_thread_state(vma, TSID(vaddr, vma)); 82 if (gts) 83 mutex_lock(>s->ts_ctxlock); 84 else 85 up_read(&mm->mmap_sem); 86 return gts; 87 } 88 89 static struct gru_thread_state *gru_alloc_locked_gts(unsigned long vaddr) 90 { 91 struct mm_struct *mm = current->mm; 92 struct vm_area_struct *vma; 93 struct gru_thread_state *gts = ERR_PTR(-EINVAL); 94 95 down_write(&mm->mmap_sem); 96 vma = gru_find_vma(vaddr); 97 if (!vma) 98 goto err; 99 100 gts = gru_alloc_thread_state(vma, TSID(vaddr, vma)); 101 if (IS_ERR(gts)) 102 goto err; 103 mutex_lock(>s->ts_ctxlock); 104 downgrade_write(&mm->mmap_sem); 105 return gts; 106 107 err: 108 up_write(&mm->mmap_sem); 109 return gts; 110 } 111 112 /* 113 * Unlock a GTS that was previously locked with gru_find_lock_gts(). 114 */ 115 static void gru_unlock_gts(struct gru_thread_state *gts) 116 { 117 mutex_unlock(>s->ts_ctxlock); 118 up_read(¤t->mm->mmap_sem); 119 } 120 121 /* 122 * Set a CB.istatus to active using a user virtual address. This must be done 123 * just prior to a TFH RESTART. The new cb.istatus is an in-cache status ONLY. 124 * If the line is evicted, the status may be lost. The in-cache update 125 * is necessary to prevent the user from seeing a stale cb.istatus that will 126 * change as soon as the TFH restart is complete. Races may cause an 127 * occasional failure to clear the cb.istatus, but that is ok. 128 */ 129 static void gru_cb_set_istatus_active(struct gru_instruction_bits *cbk) 130 { 131 if (cbk) { 132 cbk->istatus = CBS_ACTIVE; 133 } 134 } 135 136 /* 137 * Convert a interrupt IRQ to a pointer to the GRU GTS that caused the 138 * interrupt. Interrupts are always sent to a cpu on the blade that contains the 139 * GRU (except for headless blades which are not currently supported). A blade 140 * has N grus; a block of N consecutive IRQs is assigned to the GRUs. The IRQ 141 * number uniquely identifies the GRU chiplet on the local blade that caused the 142 * interrupt. Always called in interrupt context. 143 */ 144 static inline struct gru_state *irq_to_gru(int irq) 145 { 146 return &gru_base[uv_numa_blade_id()]->bs_grus[irq - IRQ_GRU]; 147 } 148 149 /* 150 * Read & clear a TFM 151 * 152 * The GRU has an array of fault maps. A map is private to a cpu 153 * Only one cpu will be accessing a cpu's fault map. 154 * 155 * This function scans the cpu-private fault map & clears all bits that 156 * are set. The function returns a bitmap that indicates the bits that 157 * were cleared. Note that sense the maps may be updated asynchronously by 158 * the GRU, atomic operations must be used to clear bits. 159 */ 160 static void get_clear_fault_map(struct gru_state *gru, 161 struct gru_tlb_fault_map *imap, 162 struct gru_tlb_fault_map *dmap) 163 { 164 unsigned long i, k; 165 struct gru_tlb_fault_map *tfm; 166 167 tfm = get_tfm_for_cpu(gru, gru_cpu_fault_map_id()); 168 prefetchw(tfm); /* Helps on hardware, required for emulator */ 169 for (i = 0; i < BITS_TO_LONGS(GRU_NUM_CBE); i++) { 170 k = tfm->fault_bits[i]; 171 if (k) 172 k = xchg(&tfm->fault_bits[i], 0UL); 173 imap->fault_bits[i] = k; 174 k = tfm->done_bits[i]; 175 if (k) 176 k = xchg(&tfm->done_bits[i], 0UL); 177 dmap->fault_bits[i] = k; 178 } 179 180 /* 181 * Not functionally required but helps performance. (Required 182 * on emulator) 183 */ 184 gru_flush_cache(tfm); 185 } 186 187 /* 188 * Atomic (interrupt context) & non-atomic (user context) functions to 189 * convert a vaddr into a physical address. The size of the page 190 * is returned in pageshift. 191 * returns: 192 * 0 - successful 193 * < 0 - error code 194 * 1 - (atomic only) try again in non-atomic context 195 */ 196 static int non_atomic_pte_lookup(struct vm_area_struct *vma, 197 unsigned long vaddr, int write, 198 unsigned long *paddr, int *pageshift) 199 { 200 struct page *page; 201 202 /* ZZZ Need to handle HUGE pages */ 203 if (is_vm_hugetlb_page(vma)) 204 return -EFAULT; 205 *pageshift = PAGE_SHIFT; 206 if (get_user_pages 207 (current, current->mm, vaddr, 1, write, 0, &page, NULL) <= 0) 208 return -EFAULT; 209 *paddr = page_to_phys(page); 210 put_page(page); 211 return 0; 212 } 213 214 /* 215 * atomic_pte_lookup 216 * 217 * Convert a user virtual address to a physical address 218 * Only supports Intel large pages (2MB only) on x86_64. 219 * ZZZ - hugepage support is incomplete 220 * 221 * NOTE: mmap_sem is already held on entry to this function. This 222 * guarantees existence of the page tables. 223 */ 224 static int atomic_pte_lookup(struct vm_area_struct *vma, unsigned long vaddr, 225 int write, unsigned long *paddr, int *pageshift) 226 { 227 pgd_t *pgdp; 228 pmd_t *pmdp; 229 pud_t *pudp; 230 pte_t pte; 231 232 pgdp = pgd_offset(vma->vm_mm, vaddr); 233 if (unlikely(pgd_none(*pgdp))) 234 goto err; 235 236 pudp = pud_offset(pgdp, vaddr); 237 if (unlikely(pud_none(*pudp))) 238 goto err; 239 240 pmdp = pmd_offset(pudp, vaddr); 241 if (unlikely(pmd_none(*pmdp))) 242 goto err; 243 #ifdef CONFIG_X86_64 244 if (unlikely(pmd_large(*pmdp))) 245 pte = *(pte_t *) pmdp; 246 else 247 #endif 248 pte = *pte_offset_kernel(pmdp, vaddr); 249 250 if (unlikely(!pte_present(pte) || 251 (write && (!pte_write(pte) || !pte_dirty(pte))))) 252 return 1; 253 254 *paddr = pte_pfn(pte) << PAGE_SHIFT; 255 #ifdef CONFIG_HUGETLB_PAGE 256 *pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT; 257 #else 258 *pageshift = PAGE_SHIFT; 259 #endif 260 return 0; 261 262 err: 263 local_irq_enable(); 264 return 1; 265 } 266 267 static int gru_vtop(struct gru_thread_state *gts, unsigned long vaddr, 268 int write, int atomic, unsigned long *gpa, int *pageshift) 269 { 270 struct mm_struct *mm = gts->ts_mm; 271 struct vm_area_struct *vma; 272 unsigned long paddr; 273 int ret, ps; 274 275 vma = find_vma(mm, vaddr); 276 if (!vma) 277 goto inval; 278 279 /* 280 * Atomic lookup is faster & usually works even if called in non-atomic 281 * context. 282 */ 283 rmb(); /* Must/check ms_range_active before loading PTEs */ 284 ret = atomic_pte_lookup(vma, vaddr, write, &paddr, &ps); 285 if (ret) { 286 if (atomic) 287 goto upm; 288 if (non_atomic_pte_lookup(vma, vaddr, write, &paddr, &ps)) 289 goto inval; 290 } 291 if (is_gru_paddr(paddr)) 292 goto inval; 293 paddr = paddr & ~((1UL << ps) - 1); 294 *gpa = uv_soc_phys_ram_to_gpa(paddr); 295 *pageshift = ps; 296 return 0; 297 298 inval: 299 return -1; 300 upm: 301 return -2; 302 } 303 304 305 /* 306 * Drop a TLB entry into the GRU. The fault is described by info in an TFH. 307 * Input: 308 * cb Address of user CBR. Null if not running in user context 309 * Return: 310 * 0 = dropin, exception, or switch to UPM successful 311 * 1 = range invalidate active 312 * < 0 = error code 313 * 314 */ 315 static int gru_try_dropin(struct gru_thread_state *gts, 316 struct gru_tlb_fault_handle *tfh, 317 struct gru_instruction_bits *cbk) 318 { 319 int pageshift = 0, asid, write, ret, atomic = !cbk; 320 unsigned long gpa = 0, vaddr = 0; 321 322 /* 323 * NOTE: The GRU contains magic hardware that eliminates races between 324 * TLB invalidates and TLB dropins. If an invalidate occurs 325 * in the window between reading the TFH and the subsequent TLB dropin, 326 * the dropin is ignored. This eliminates the need for additional locks. 327 */ 328 329 /* 330 * Error if TFH state is IDLE or FMM mode & the user issuing a UPM call. 331 * Might be a hardware race OR a stupid user. Ignore FMM because FMM 332 * is a transient state. 333 */ 334 if (tfh->status != TFHSTATUS_EXCEPTION) { 335 gru_flush_cache(tfh); 336 if (tfh->status != TFHSTATUS_EXCEPTION) 337 goto failnoexception; 338 STAT(tfh_stale_on_fault); 339 } 340 if (tfh->state == TFHSTATE_IDLE) 341 goto failidle; 342 if (tfh->state == TFHSTATE_MISS_FMM && cbk) 343 goto failfmm; 344 345 write = (tfh->cause & TFHCAUSE_TLB_MOD) != 0; 346 vaddr = tfh->missvaddr; 347 asid = tfh->missasid; 348 if (asid == 0) 349 goto failnoasid; 350 351 rmb(); /* TFH must be cache resident before reading ms_range_active */ 352 353 /* 354 * TFH is cache resident - at least briefly. Fail the dropin 355 * if a range invalidate is active. 356 */ 357 if (atomic_read(>s->ts_gms->ms_range_active)) 358 goto failactive; 359 360 ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift); 361 if (ret == -1) 362 goto failinval; 363 if (ret == -2) 364 goto failupm; 365 366 if (!(gts->ts_sizeavail & GRU_SIZEAVAIL(pageshift))) { 367 gts->ts_sizeavail |= GRU_SIZEAVAIL(pageshift); 368 if (atomic || !gru_update_cch(gts)) { 369 gts->ts_force_cch_reload = 1; 370 goto failupm; 371 } 372 } 373 gru_cb_set_istatus_active(cbk); 374 tfh_write_restart(tfh, gpa, GAA_RAM, vaddr, asid, write, 375 GRU_PAGESIZE(pageshift)); 376 STAT(tlb_dropin); 377 gru_dbg(grudev, 378 "%s: tfh 0x%p, vaddr 0x%lx, asid 0x%x, ps %d, gpa 0x%lx\n", 379 ret ? "non-atomic" : "atomic", tfh, vaddr, asid, 380 pageshift, gpa); 381 return 0; 382 383 failnoasid: 384 /* No asid (delayed unload). */ 385 STAT(tlb_dropin_fail_no_asid); 386 gru_dbg(grudev, "FAILED no_asid tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr); 387 if (!cbk) 388 tfh_user_polling_mode(tfh); 389 else 390 gru_flush_cache(tfh); 391 return -EAGAIN; 392 393 failupm: 394 /* Atomic failure switch CBR to UPM */ 395 tfh_user_polling_mode(tfh); 396 STAT(tlb_dropin_fail_upm); 397 gru_dbg(grudev, "FAILED upm tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr); 398 return 1; 399 400 failfmm: 401 /* FMM state on UPM call */ 402 gru_flush_cache(tfh); 403 STAT(tlb_dropin_fail_fmm); 404 gru_dbg(grudev, "FAILED fmm tfh: 0x%p, state %d\n", tfh, tfh->state); 405 return 0; 406 407 failnoexception: 408 /* TFH status did not show exception pending */ 409 gru_flush_cache(tfh); 410 if (cbk) 411 gru_flush_cache(cbk); 412 STAT(tlb_dropin_fail_no_exception); 413 gru_dbg(grudev, "FAILED non-exception tfh: 0x%p, status %d, state %d\n", 414 tfh, tfh->status, tfh->state); 415 return 0; 416 417 failidle: 418 /* TFH state was idle - no miss pending */ 419 gru_flush_cache(tfh); 420 if (cbk) 421 gru_flush_cache(cbk); 422 STAT(tlb_dropin_fail_idle); 423 gru_dbg(grudev, "FAILED idle tfh: 0x%p, state %d\n", tfh, tfh->state); 424 return 0; 425 426 failinval: 427 /* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */ 428 tfh_exception(tfh); 429 STAT(tlb_dropin_fail_invalid); 430 gru_dbg(grudev, "FAILED inval tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr); 431 return -EFAULT; 432 433 failactive: 434 /* Range invalidate active. Switch to UPM iff atomic */ 435 if (!cbk) 436 tfh_user_polling_mode(tfh); 437 else 438 gru_flush_cache(tfh); 439 STAT(tlb_dropin_fail_range_active); 440 gru_dbg(grudev, "FAILED range active: tfh 0x%p, vaddr 0x%lx\n", 441 tfh, vaddr); 442 return 1; 443 } 444 445 /* 446 * Process an external interrupt from the GRU. This interrupt is 447 * caused by a TLB miss. 448 * Note that this is the interrupt handler that is registered with linux 449 * interrupt handlers. 450 */ 451 irqreturn_t gru_intr(int irq, void *dev_id) 452 { 453 struct gru_state *gru; 454 struct gru_tlb_fault_map imap, dmap; 455 struct gru_thread_state *gts; 456 struct gru_tlb_fault_handle *tfh = NULL; 457 int cbrnum, ctxnum; 458 459 STAT(intr); 460 461 gru = irq_to_gru(irq); 462 if (!gru) { 463 dev_err(grudev, "GRU: invalid interrupt: cpu %d, irq %d\n", 464 raw_smp_processor_id(), irq); 465 return IRQ_NONE; 466 } 467 get_clear_fault_map(gru, &imap, &dmap); 468 469 for_each_cbr_in_tfm(cbrnum, dmap.fault_bits) { 470 complete(gru->gs_blade->bs_async_wq); 471 gru_dbg(grudev, "gid %d, cbr_done %d, done %d\n", 472 gru->gs_gid, cbrnum, gru->gs_blade->bs_async_wq->done); 473 } 474 475 for_each_cbr_in_tfm(cbrnum, imap.fault_bits) { 476 tfh = get_tfh_by_index(gru, cbrnum); 477 prefetchw(tfh); /* Helps on hdw, required for emulator */ 478 479 /* 480 * When hardware sets a bit in the faultmap, it implicitly 481 * locks the GRU context so that it cannot be unloaded. 482 * The gts cannot change until a TFH start/writestart command 483 * is issued. 484 */ 485 ctxnum = tfh->ctxnum; 486 gts = gru->gs_gts[ctxnum]; 487 488 /* 489 * This is running in interrupt context. Trylock the mmap_sem. 490 * If it fails, retry the fault in user context. 491 */ 492 if (!gts->ts_force_cch_reload && 493 down_read_trylock(>s->ts_mm->mmap_sem)) { 494 gts->ustats.fmm_tlbdropin++; 495 gru_try_dropin(gts, tfh, NULL); 496 up_read(>s->ts_mm->mmap_sem); 497 } else { 498 tfh_user_polling_mode(tfh); 499 STAT(intr_mm_lock_failed); 500 } 501 } 502 return IRQ_HANDLED; 503 } 504 505 506 static int gru_user_dropin(struct gru_thread_state *gts, 507 struct gru_tlb_fault_handle *tfh, 508 void *cb) 509 { 510 struct gru_mm_struct *gms = gts->ts_gms; 511 int ret; 512 513 gts->ustats.upm_tlbdropin++; 514 while (1) { 515 wait_event(gms->ms_wait_queue, 516 atomic_read(&gms->ms_range_active) == 0); 517 prefetchw(tfh); /* Helps on hdw, required for emulator */ 518 ret = gru_try_dropin(gts, tfh, cb); 519 if (ret <= 0) 520 return ret; 521 STAT(call_os_wait_queue); 522 } 523 } 524 525 /* 526 * This interface is called as a result of a user detecting a "call OS" bit 527 * in a user CB. Normally means that a TLB fault has occurred. 528 * cb - user virtual address of the CB 529 */ 530 int gru_handle_user_call_os(unsigned long cb) 531 { 532 struct gru_tlb_fault_handle *tfh; 533 struct gru_thread_state *gts; 534 void *cbk; 535 int ucbnum, cbrnum, ret = -EINVAL; 536 537 STAT(call_os); 538 gru_dbg(grudev, "address 0x%lx\n", cb); 539 540 /* sanity check the cb pointer */ 541 ucbnum = get_cb_number((void *)cb); 542 if ((cb & (GRU_HANDLE_STRIDE - 1)) || ucbnum >= GRU_NUM_CB) 543 return -EINVAL; 544 545 gts = gru_find_lock_gts(cb); 546 if (!gts) 547 return -EINVAL; 548 549 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE) 550 goto exit; 551 552 gru_check_context_placement(gts); 553 554 /* 555 * CCH may contain stale data if ts_force_cch_reload is set. 556 */ 557 if (gts->ts_gru && gts->ts_force_cch_reload) { 558 gts->ts_force_cch_reload = 0; 559 gru_update_cch(gts); 560 } 561 562 ret = -EAGAIN; 563 cbrnum = thread_cbr_number(gts, ucbnum); 564 if (gts->ts_gru) { 565 tfh = get_tfh_by_index(gts->ts_gru, cbrnum); 566 cbk = get_gseg_base_address_cb(gts->ts_gru->gs_gru_base_vaddr, 567 gts->ts_ctxnum, ucbnum); 568 ret = gru_user_dropin(gts, tfh, cbk); 569 } 570 exit: 571 gru_unlock_gts(gts); 572 return ret; 573 } 574 575 /* 576 * Fetch the exception detail information for a CB that terminated with 577 * an exception. 578 */ 579 int gru_get_exception_detail(unsigned long arg) 580 { 581 struct control_block_extended_exc_detail excdet; 582 struct gru_control_block_extended *cbe; 583 struct gru_thread_state *gts; 584 int ucbnum, cbrnum, ret; 585 586 STAT(user_exception); 587 if (copy_from_user(&excdet, (void __user *)arg, sizeof(excdet))) 588 return -EFAULT; 589 590 gru_dbg(grudev, "address 0x%lx\n", excdet.cb); 591 gts = gru_find_lock_gts(excdet.cb); 592 if (!gts) 593 return -EINVAL; 594 595 ucbnum = get_cb_number((void *)excdet.cb); 596 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE) { 597 ret = -EINVAL; 598 } else if (gts->ts_gru) { 599 cbrnum = thread_cbr_number(gts, ucbnum); 600 cbe = get_cbe_by_index(gts->ts_gru, cbrnum); 601 gru_flush_cache(cbe); /* CBE not coherent */ 602 excdet.opc = cbe->opccpy; 603 excdet.exopc = cbe->exopccpy; 604 excdet.ecause = cbe->ecause; 605 excdet.exceptdet0 = cbe->idef1upd; 606 excdet.exceptdet1 = cbe->idef3upd; 607 excdet.cbrstate = cbe->cbrstate; 608 excdet.cbrexecstatus = cbe->cbrexecstatus; 609 gru_flush_cache(cbe); 610 ret = 0; 611 } else { 612 ret = -EAGAIN; 613 } 614 gru_unlock_gts(gts); 615 616 gru_dbg(grudev, 617 "cb 0x%lx, op %d, exopc %d, cbrstate %d, cbrexecstatus 0x%x, ecause 0x%x, " 618 "exdet0 0x%lx, exdet1 0x%x\n", 619 excdet.cb, excdet.opc, excdet.exopc, excdet.cbrstate, excdet.cbrexecstatus, 620 excdet.ecause, excdet.exceptdet0, excdet.exceptdet1); 621 if (!ret && copy_to_user((void __user *)arg, &excdet, sizeof(excdet))) 622 ret = -EFAULT; 623 return ret; 624 } 625 626 /* 627 * User request to unload a context. Content is saved for possible reload. 628 */ 629 static int gru_unload_all_contexts(void) 630 { 631 struct gru_thread_state *gts; 632 struct gru_state *gru; 633 int gid, ctxnum; 634 635 if (!capable(CAP_SYS_ADMIN)) 636 return -EPERM; 637 foreach_gid(gid) { 638 gru = GID_TO_GRU(gid); 639 spin_lock(&gru->gs_lock); 640 for (ctxnum = 0; ctxnum < GRU_NUM_CCH; ctxnum++) { 641 gts = gru->gs_gts[ctxnum]; 642 if (gts && mutex_trylock(>s->ts_ctxlock)) { 643 spin_unlock(&gru->gs_lock); 644 gru_unload_context(gts, 1); 645 mutex_unlock(>s->ts_ctxlock); 646 spin_lock(&gru->gs_lock); 647 } 648 } 649 spin_unlock(&gru->gs_lock); 650 } 651 return 0; 652 } 653 654 int gru_user_unload_context(unsigned long arg) 655 { 656 struct gru_thread_state *gts; 657 struct gru_unload_context_req req; 658 659 STAT(user_unload_context); 660 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) 661 return -EFAULT; 662 663 gru_dbg(grudev, "gseg 0x%lx\n", req.gseg); 664 665 if (!req.gseg) 666 return gru_unload_all_contexts(); 667 668 gts = gru_find_lock_gts(req.gseg); 669 if (!gts) 670 return -EINVAL; 671 672 if (gts->ts_gru) 673 gru_unload_context(gts, 1); 674 gru_unlock_gts(gts); 675 676 return 0; 677 } 678 679 /* 680 * User request to flush a range of virtual addresses from the GRU TLB 681 * (Mainly for testing). 682 */ 683 int gru_user_flush_tlb(unsigned long arg) 684 { 685 struct gru_thread_state *gts; 686 struct gru_flush_tlb_req req; 687 struct gru_mm_struct *gms; 688 689 STAT(user_flush_tlb); 690 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) 691 return -EFAULT; 692 693 gru_dbg(grudev, "gseg 0x%lx, vaddr 0x%lx, len 0x%lx\n", req.gseg, 694 req.vaddr, req.len); 695 696 gts = gru_find_lock_gts(req.gseg); 697 if (!gts) 698 return -EINVAL; 699 700 gms = gts->ts_gms; 701 gru_unlock_gts(gts); 702 gru_flush_tlb_range(gms, req.vaddr, req.len); 703 704 return 0; 705 } 706 707 /* 708 * Fetch GSEG statisticss 709 */ 710 long gru_get_gseg_statistics(unsigned long arg) 711 { 712 struct gru_thread_state *gts; 713 struct gru_get_gseg_statistics_req req; 714 715 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) 716 return -EFAULT; 717 718 /* 719 * The library creates arrays of contexts for threaded programs. 720 * If no gts exists in the array, the context has never been used & all 721 * statistics are implicitly 0. 722 */ 723 gts = gru_find_lock_gts(req.gseg); 724 if (gts) { 725 memcpy(&req.stats, >s->ustats, sizeof(gts->ustats)); 726 gru_unlock_gts(gts); 727 } else { 728 memset(&req.stats, 0, sizeof(gts->ustats)); 729 } 730 731 if (copy_to_user((void __user *)arg, &req, sizeof(req))) 732 return -EFAULT; 733 734 return 0; 735 } 736 737 /* 738 * Register the current task as the user of the GSEG slice. 739 * Needed for TLB fault interrupt targeting. 740 */ 741 int gru_set_context_option(unsigned long arg) 742 { 743 struct gru_thread_state *gts; 744 struct gru_set_context_option_req req; 745 int ret = 0; 746 747 STAT(set_context_option); 748 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) 749 return -EFAULT; 750 gru_dbg(grudev, "op %d, gseg 0x%lx, value1 0x%lx\n", req.op, req.gseg, req.val1); 751 752 gts = gru_alloc_locked_gts(req.gseg); 753 if (IS_ERR(gts)) 754 return PTR_ERR(gts); 755 756 switch (req.op) { 757 case sco_blade_chiplet: 758 /* Select blade/chiplet for GRU context */ 759 if (req.val1 < -1 || req.val1 >= GRU_MAX_BLADES || !gru_base[req.val1] || 760 req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB) { 761 ret = -EINVAL; 762 } else { 763 gts->ts_user_blade_id = req.val1; 764 gts->ts_user_chiplet_id = req.val0; 765 gru_check_context_placement(gts); 766 } 767 break; 768 case sco_gseg_owner: 769 /* Register the current task as the GSEG owner */ 770 gts->ts_tgid_owner = current->tgid; 771 break; 772 case sco_cch_req_slice: 773 /* Set the CCH slice option */ 774 gts->ts_cch_req_slice = req.val1 & 3; 775 break; 776 default: 777 ret = -EINVAL; 778 } 779 gru_unlock_gts(gts); 780 781 return ret; 782 } 783