1 /* 2 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU Lesser General Public License as published by 6 * the Free Software Foundation; either version 2.1 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __GRU_INSTRUCTIONS_H__ 20 #define __GRU_INSTRUCTIONS_H__ 21 22 extern int gru_check_status_proc(void *cb); 23 extern int gru_wait_proc(void *cb); 24 extern void gru_wait_abort_proc(void *cb); 25 26 27 28 /* 29 * Architecture dependent functions 30 */ 31 32 #if defined(CONFIG_IA64) 33 #include <linux/compiler.h> 34 #include <asm/intrinsics.h> 35 #define __flush_cache(p) ia64_fc((unsigned long)p) 36 /* Use volatile on IA64 to ensure ordering via st4.rel */ 37 #define gru_ordered_store_ulong(p, v) \ 38 do { \ 39 barrier(); \ 40 *((volatile unsigned long *)(p)) = v; /* force st.rel */ \ 41 } while (0) 42 #elif defined(CONFIG_X86_64) 43 #define __flush_cache(p) clflush(p) 44 #define gru_ordered_store_ulong(p, v) \ 45 do { \ 46 barrier(); \ 47 *(unsigned long *)p = v; \ 48 } while (0) 49 #else 50 #error "Unsupported architecture" 51 #endif 52 53 /* 54 * Control block status and exception codes 55 */ 56 #define CBS_IDLE 0 57 #define CBS_EXCEPTION 1 58 #define CBS_ACTIVE 2 59 #define CBS_CALL_OS 3 60 61 /* CB substatus bitmasks */ 62 #define CBSS_MSG_QUEUE_MASK 7 63 #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8 64 65 /* CB substatus message queue values (low 3 bits of substatus) */ 66 #define CBSS_NO_ERROR 0 67 #define CBSS_LB_OVERFLOWED 1 68 #define CBSS_QLIMIT_REACHED 2 69 #define CBSS_PAGE_OVERFLOW 3 70 #define CBSS_AMO_NACKED 4 71 #define CBSS_PUT_NACKED 5 72 73 /* 74 * Structure used to fetch exception detail for CBs that terminate with 75 * CBS_EXCEPTION 76 */ 77 struct control_block_extended_exc_detail { 78 unsigned long cb; 79 int opc; 80 int ecause; 81 int exopc; 82 long exceptdet0; 83 int exceptdet1; 84 int cbrstate; 85 int cbrexecstatus; 86 }; 87 88 /* 89 * Instruction formats 90 */ 91 92 /* 93 * Generic instruction format. 94 * This definition has precise bit field definitions. 95 */ 96 struct gru_instruction_bits { 97 /* DW 0 - low */ 98 unsigned int icmd: 1; 99 unsigned char ima: 3; /* CB_DelRep, unmapped mode */ 100 unsigned char reserved0: 4; 101 unsigned int xtype: 3; 102 unsigned int iaa0: 2; 103 unsigned int iaa1: 2; 104 unsigned char reserved1: 1; 105 unsigned char opc: 8; /* opcode */ 106 unsigned char exopc: 8; /* extended opcode */ 107 /* DW 0 - high */ 108 unsigned int idef2: 22; /* TRi0 */ 109 unsigned char reserved2: 2; 110 unsigned char istatus: 2; 111 unsigned char isubstatus:4; 112 unsigned char reserved3: 1; 113 unsigned char tlb_fault_color: 1; 114 /* DW 1 */ 115 unsigned long idef4; /* 42 bits: TRi1, BufSize */ 116 /* DW 2-6 */ 117 unsigned long idef1; /* BAddr0 */ 118 unsigned long idef5; /* Nelem */ 119 unsigned long idef6; /* Stride, Operand1 */ 120 unsigned long idef3; /* BAddr1, Value, Operand2 */ 121 unsigned long reserved4; 122 /* DW 7 */ 123 unsigned long avalue; /* AValue */ 124 }; 125 126 /* 127 * Generic instruction with friendlier names. This format is used 128 * for inline instructions. 129 */ 130 struct gru_instruction { 131 /* DW 0 */ 132 union { 133 unsigned long op64; /* icmd,xtype,iaa0,ima,opc,tri0 */ 134 struct { 135 unsigned int op32; 136 unsigned int tri0; 137 }; 138 }; 139 unsigned long tri1_bufsize; /* DW 1 */ 140 unsigned long baddr0; /* DW 2 */ 141 unsigned long nelem; /* DW 3 */ 142 unsigned long op1_stride; /* DW 4 */ 143 unsigned long op2_value_baddr1; /* DW 5 */ 144 unsigned long reserved0; /* DW 6 */ 145 unsigned long avalue; /* DW 7 */ 146 }; 147 148 /* Some shifts and masks for the low 64 bits of a GRU command */ 149 #define GRU_CB_ICMD_SHFT 0 150 #define GRU_CB_ICMD_MASK 0x1 151 #define GRU_CB_XTYPE_SHFT 8 152 #define GRU_CB_XTYPE_MASK 0x7 153 #define GRU_CB_IAA0_SHFT 11 154 #define GRU_CB_IAA0_MASK 0x3 155 #define GRU_CB_IAA1_SHFT 13 156 #define GRU_CB_IAA1_MASK 0x3 157 #define GRU_CB_IMA_SHFT 1 158 #define GRU_CB_IMA_MASK 0x3 159 #define GRU_CB_OPC_SHFT 16 160 #define GRU_CB_OPC_MASK 0xff 161 #define GRU_CB_EXOPC_SHFT 24 162 #define GRU_CB_EXOPC_MASK 0xff 163 #define GRU_IDEF2_SHFT 32 164 #define GRU_IDEF2_MASK 0x3ffff 165 #define GRU_ISTATUS_SHFT 56 166 #define GRU_ISTATUS_MASK 0x3 167 168 /* GRU instruction opcodes (opc field) */ 169 #define OP_NOP 0x00 170 #define OP_BCOPY 0x01 171 #define OP_VLOAD 0x02 172 #define OP_IVLOAD 0x03 173 #define OP_VSTORE 0x04 174 #define OP_IVSTORE 0x05 175 #define OP_VSET 0x06 176 #define OP_IVSET 0x07 177 #define OP_MESQ 0x08 178 #define OP_GAMXR 0x09 179 #define OP_GAMIR 0x0a 180 #define OP_GAMIRR 0x0b 181 #define OP_GAMER 0x0c 182 #define OP_GAMERR 0x0d 183 #define OP_BSTORE 0x0e 184 #define OP_VFLUSH 0x0f 185 186 187 /* Extended opcodes values (exopc field) */ 188 189 /* GAMIR - AMOs with implicit operands */ 190 #define EOP_IR_FETCH 0x01 /* Plain fetch of memory */ 191 #define EOP_IR_CLR 0x02 /* Fetch and clear */ 192 #define EOP_IR_INC 0x05 /* Fetch and increment */ 193 #define EOP_IR_DEC 0x07 /* Fetch and decrement */ 194 #define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */ 195 #define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */ 196 197 /* GAMIRR - Registered AMOs with implicit operands */ 198 #define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */ 199 #define EOP_IRR_CLR 0x02 /* Registered fetch and clear */ 200 #define EOP_IRR_INC 0x05 /* Registered fetch and increment */ 201 #define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */ 202 #define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/ 203 204 /* GAMER - AMOs with explicit operands */ 205 #define EOP_ER_SWAP 0x00 /* Exchange argument and memory */ 206 #define EOP_ER_OR 0x01 /* Logical OR with memory */ 207 #define EOP_ER_AND 0x02 /* Logical AND with memory */ 208 #define EOP_ER_XOR 0x03 /* Logical XOR with memory */ 209 #define EOP_ER_ADD 0x04 /* Add value to memory */ 210 #define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ 211 #define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */ 212 213 /* GAMERR - Registered AMOs with explicit operands */ 214 #define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */ 215 #define EOP_ERR_OR 0x01 /* Logical OR with memory */ 216 #define EOP_ERR_AND 0x02 /* Logical AND with memory */ 217 #define EOP_ERR_XOR 0x03 /* Logical XOR with memory */ 218 #define EOP_ERR_ADD 0x04 /* Add value to memory */ 219 #define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ 220 #define EOP_ERR_EPOLL 0x09 /* Poll for equality */ 221 #define EOP_ERR_NPOLL 0x0a /* Poll for inequality */ 222 223 /* GAMXR - SGI Arithmetic unit */ 224 #define EOP_XR_CSWAP 0x0b /* Masked compare exchange */ 225 226 227 /* Transfer types (xtype field) */ 228 #define XTYPE_B 0x0 /* byte */ 229 #define XTYPE_S 0x1 /* short (2-byte) */ 230 #define XTYPE_W 0x2 /* word (4-byte) */ 231 #define XTYPE_DW 0x3 /* doubleword (8-byte) */ 232 #define XTYPE_CL 0x6 /* cacheline (64-byte) */ 233 234 235 /* Instruction access attributes (iaa0, iaa1 fields) */ 236 #define IAA_RAM 0x0 /* normal cached RAM access */ 237 #define IAA_NCRAM 0x2 /* noncoherent RAM access */ 238 #define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */ 239 #define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */ 240 241 242 /* Instruction mode attributes (ima field) */ 243 #define IMA_MAPPED 0x0 /* Virtual mode */ 244 #define IMA_CB_DELAY 0x1 /* hold read responses until status changes */ 245 #define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */ 246 #define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */ 247 248 /* CBE ecause bits */ 249 #define CBE_CAUSE_RI (1 << 0) 250 #define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1) 251 #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2) 252 #define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3) 253 #define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4) 254 #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5) 255 #define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6) 256 #define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7) 257 #define CBE_CAUSE_TLBHW_ERROR (1 << 8) 258 #define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9) 259 #define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10) 260 #define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11) 261 #define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12) 262 #define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13) 263 #define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14) 264 #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15) 265 #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16) 266 #define CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17) 267 #define CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18) 268 269 /* CBE cbrexecstatus bits */ 270 #define CBR_EXS_ABORT_OCC_BIT 0 271 #define CBR_EXS_INT_OCC_BIT 1 272 #define CBR_EXS_PENDING_BIT 2 273 #define CBR_EXS_QUEUED_BIT 3 274 #define CBR_EXS_TLB_INVAL_BIT 4 275 #define CBR_EXS_EXCEPTION_BIT 5 276 277 #define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT) 278 #define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT) 279 #define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT) 280 #define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT) 281 #define CBR_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT) 282 #define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT) 283 284 /* 285 * Exceptions are retried for the following cases. If any OTHER bits are set 286 * in ecause, the exception is not retryable. 287 */ 288 #define EXCEPTION_RETRY_BITS (CBE_CAUSE_EXECUTION_HW_ERROR | \ 289 CBE_CAUSE_TLBHW_ERROR | \ 290 CBE_CAUSE_RA_REQUEST_TIMEOUT | \ 291 CBE_CAUSE_RA_RESPONSE_NON_FATAL | \ 292 CBE_CAUSE_HA_RESPONSE_NON_FATAL | \ 293 CBE_CAUSE_RA_RESPONSE_DATA_ERROR | \ 294 CBE_CAUSE_HA_RESPONSE_DATA_ERROR \ 295 ) 296 297 /* Message queue head structure */ 298 union gru_mesqhead { 299 unsigned long val; 300 struct { 301 unsigned int head; 302 unsigned int limit; 303 }; 304 }; 305 306 307 /* Generate the low word of a GRU instruction */ 308 static inline unsigned long 309 __opdword(unsigned char opcode, unsigned char exopc, unsigned char xtype, 310 unsigned char iaa0, unsigned char iaa1, 311 unsigned long idef2, unsigned char ima) 312 { 313 return (1 << GRU_CB_ICMD_SHFT) | 314 ((unsigned long)CBS_ACTIVE << GRU_ISTATUS_SHFT) | 315 (idef2<< GRU_IDEF2_SHFT) | 316 (iaa0 << GRU_CB_IAA0_SHFT) | 317 (iaa1 << GRU_CB_IAA1_SHFT) | 318 (ima << GRU_CB_IMA_SHFT) | 319 (xtype << GRU_CB_XTYPE_SHFT) | 320 (opcode << GRU_CB_OPC_SHFT) | 321 (exopc << GRU_CB_EXOPC_SHFT); 322 } 323 324 /* 325 * Architecture specific intrinsics 326 */ 327 static inline void gru_flush_cache(void *p) 328 { 329 __flush_cache(p); 330 } 331 332 /* 333 * Store the lower 64 bits of the command including the "start" bit. Then 334 * start the instruction executing. 335 */ 336 static inline void gru_start_instruction(struct gru_instruction *ins, unsigned long op64) 337 { 338 gru_ordered_store_ulong(ins, op64); 339 mb(); 340 gru_flush_cache(ins); 341 } 342 343 344 /* Convert "hints" to IMA */ 345 #define CB_IMA(h) ((h) | IMA_UNMAPPED) 346 347 /* Convert data segment cache line index into TRI0 / TRI1 value */ 348 #define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES) 349 350 /* Inline functions for GRU instructions. 351 * Note: 352 * - nelem and stride are in elements 353 * - tri0/tri1 is in bytes for the beginning of the data segment. 354 */ 355 static inline void gru_vload_phys(void *cb, unsigned long gpa, 356 unsigned int tri0, int iaa, unsigned long hints) 357 { 358 struct gru_instruction *ins = (struct gru_instruction *)cb; 359 360 ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62); 361 ins->nelem = 1; 362 ins->op1_stride = 1; 363 gru_start_instruction(ins, __opdword(OP_VLOAD, 0, XTYPE_DW, iaa, 0, 364 (unsigned long)tri0, CB_IMA(hints))); 365 } 366 367 static inline void gru_vload(void *cb, unsigned long mem_addr, 368 unsigned int tri0, unsigned char xtype, unsigned long nelem, 369 unsigned long stride, unsigned long hints) 370 { 371 struct gru_instruction *ins = (struct gru_instruction *)cb; 372 373 ins->baddr0 = (long)mem_addr; 374 ins->nelem = nelem; 375 ins->op1_stride = stride; 376 gru_start_instruction(ins, __opdword(OP_VLOAD, 0, xtype, IAA_RAM, 0, 377 (unsigned long)tri0, CB_IMA(hints))); 378 } 379 380 static inline void gru_vstore(void *cb, unsigned long mem_addr, 381 unsigned int tri0, unsigned char xtype, unsigned long nelem, 382 unsigned long stride, unsigned long hints) 383 { 384 struct gru_instruction *ins = (void *)cb; 385 386 ins->baddr0 = (long)mem_addr; 387 ins->nelem = nelem; 388 ins->op1_stride = stride; 389 gru_start_instruction(ins, __opdword(OP_VSTORE, 0, xtype, IAA_RAM, 0, 390 tri0, CB_IMA(hints))); 391 } 392 393 static inline void gru_ivload(void *cb, unsigned long mem_addr, 394 unsigned int tri0, unsigned int tri1, unsigned char xtype, 395 unsigned long nelem, unsigned long hints) 396 { 397 struct gru_instruction *ins = (void *)cb; 398 399 ins->baddr0 = (long)mem_addr; 400 ins->nelem = nelem; 401 ins->tri1_bufsize = tri1; 402 gru_start_instruction(ins, __opdword(OP_IVLOAD, 0, xtype, IAA_RAM, 0, 403 tri0, CB_IMA(hints))); 404 } 405 406 static inline void gru_ivstore(void *cb, unsigned long mem_addr, 407 unsigned int tri0, unsigned int tri1, 408 unsigned char xtype, unsigned long nelem, unsigned long hints) 409 { 410 struct gru_instruction *ins = (void *)cb; 411 412 ins->baddr0 = (long)mem_addr; 413 ins->nelem = nelem; 414 ins->tri1_bufsize = tri1; 415 gru_start_instruction(ins, __opdword(OP_IVSTORE, 0, xtype, IAA_RAM, 0, 416 tri0, CB_IMA(hints))); 417 } 418 419 static inline void gru_vset(void *cb, unsigned long mem_addr, 420 unsigned long value, unsigned char xtype, unsigned long nelem, 421 unsigned long stride, unsigned long hints) 422 { 423 struct gru_instruction *ins = (void *)cb; 424 425 ins->baddr0 = (long)mem_addr; 426 ins->op2_value_baddr1 = value; 427 ins->nelem = nelem; 428 ins->op1_stride = stride; 429 gru_start_instruction(ins, __opdword(OP_VSET, 0, xtype, IAA_RAM, 0, 430 0, CB_IMA(hints))); 431 } 432 433 static inline void gru_ivset(void *cb, unsigned long mem_addr, 434 unsigned int tri1, unsigned long value, unsigned char xtype, 435 unsigned long nelem, unsigned long hints) 436 { 437 struct gru_instruction *ins = (void *)cb; 438 439 ins->baddr0 = (long)mem_addr; 440 ins->op2_value_baddr1 = value; 441 ins->nelem = nelem; 442 ins->tri1_bufsize = tri1; 443 gru_start_instruction(ins, __opdword(OP_IVSET, 0, xtype, IAA_RAM, 0, 444 0, CB_IMA(hints))); 445 } 446 447 static inline void gru_vflush(void *cb, unsigned long mem_addr, 448 unsigned long nelem, unsigned char xtype, unsigned long stride, 449 unsigned long hints) 450 { 451 struct gru_instruction *ins = (void *)cb; 452 453 ins->baddr0 = (long)mem_addr; 454 ins->op1_stride = stride; 455 ins->nelem = nelem; 456 gru_start_instruction(ins, __opdword(OP_VFLUSH, 0, xtype, IAA_RAM, 0, 457 0, CB_IMA(hints))); 458 } 459 460 static inline void gru_nop(void *cb, int hints) 461 { 462 struct gru_instruction *ins = (void *)cb; 463 464 gru_start_instruction(ins, __opdword(OP_NOP, 0, 0, 0, 0, 0, CB_IMA(hints))); 465 } 466 467 468 static inline void gru_bcopy(void *cb, const unsigned long src, 469 unsigned long dest, 470 unsigned int tri0, unsigned int xtype, unsigned long nelem, 471 unsigned int bufsize, unsigned long hints) 472 { 473 struct gru_instruction *ins = (void *)cb; 474 475 ins->baddr0 = (long)src; 476 ins->op2_value_baddr1 = (long)dest; 477 ins->nelem = nelem; 478 ins->tri1_bufsize = bufsize; 479 gru_start_instruction(ins, __opdword(OP_BCOPY, 0, xtype, IAA_RAM, 480 IAA_RAM, tri0, CB_IMA(hints))); 481 } 482 483 static inline void gru_bstore(void *cb, const unsigned long src, 484 unsigned long dest, unsigned int tri0, unsigned int xtype, 485 unsigned long nelem, unsigned long hints) 486 { 487 struct gru_instruction *ins = (void *)cb; 488 489 ins->baddr0 = (long)src; 490 ins->op2_value_baddr1 = (long)dest; 491 ins->nelem = nelem; 492 gru_start_instruction(ins, __opdword(OP_BSTORE, 0, xtype, 0, IAA_RAM, 493 tri0, CB_IMA(hints))); 494 } 495 496 static inline void gru_gamir(void *cb, int exopc, unsigned long src, 497 unsigned int xtype, unsigned long hints) 498 { 499 struct gru_instruction *ins = (void *)cb; 500 501 ins->baddr0 = (long)src; 502 gru_start_instruction(ins, __opdword(OP_GAMIR, exopc, xtype, IAA_RAM, 0, 503 0, CB_IMA(hints))); 504 } 505 506 static inline void gru_gamirr(void *cb, int exopc, unsigned long src, 507 unsigned int xtype, unsigned long hints) 508 { 509 struct gru_instruction *ins = (void *)cb; 510 511 ins->baddr0 = (long)src; 512 gru_start_instruction(ins, __opdword(OP_GAMIRR, exopc, xtype, IAA_RAM, 0, 513 0, CB_IMA(hints))); 514 } 515 516 static inline void gru_gamer(void *cb, int exopc, unsigned long src, 517 unsigned int xtype, 518 unsigned long operand1, unsigned long operand2, 519 unsigned long hints) 520 { 521 struct gru_instruction *ins = (void *)cb; 522 523 ins->baddr0 = (long)src; 524 ins->op1_stride = operand1; 525 ins->op2_value_baddr1 = operand2; 526 gru_start_instruction(ins, __opdword(OP_GAMER, exopc, xtype, IAA_RAM, 0, 527 0, CB_IMA(hints))); 528 } 529 530 static inline void gru_gamerr(void *cb, int exopc, unsigned long src, 531 unsigned int xtype, unsigned long operand1, 532 unsigned long operand2, unsigned long hints) 533 { 534 struct gru_instruction *ins = (void *)cb; 535 536 ins->baddr0 = (long)src; 537 ins->op1_stride = operand1; 538 ins->op2_value_baddr1 = operand2; 539 gru_start_instruction(ins, __opdword(OP_GAMERR, exopc, xtype, IAA_RAM, 0, 540 0, CB_IMA(hints))); 541 } 542 543 static inline void gru_gamxr(void *cb, unsigned long src, 544 unsigned int tri0, unsigned long hints) 545 { 546 struct gru_instruction *ins = (void *)cb; 547 548 ins->baddr0 = (long)src; 549 ins->nelem = 4; 550 gru_start_instruction(ins, __opdword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW, 551 IAA_RAM, 0, 0, CB_IMA(hints))); 552 } 553 554 static inline void gru_mesq(void *cb, unsigned long queue, 555 unsigned long tri0, unsigned long nelem, 556 unsigned long hints) 557 { 558 struct gru_instruction *ins = (void *)cb; 559 560 ins->baddr0 = (long)queue; 561 ins->nelem = nelem; 562 gru_start_instruction(ins, __opdword(OP_MESQ, 0, XTYPE_CL, IAA_RAM, 0, 563 tri0, CB_IMA(hints))); 564 } 565 566 static inline unsigned long gru_get_amo_value(void *cb) 567 { 568 struct gru_instruction *ins = (void *)cb; 569 570 return ins->avalue; 571 } 572 573 static inline int gru_get_amo_value_head(void *cb) 574 { 575 struct gru_instruction *ins = (void *)cb; 576 577 return ins->avalue & 0xffffffff; 578 } 579 580 static inline int gru_get_amo_value_limit(void *cb) 581 { 582 struct gru_instruction *ins = (void *)cb; 583 584 return ins->avalue >> 32; 585 } 586 587 static inline union gru_mesqhead gru_mesq_head(int head, int limit) 588 { 589 union gru_mesqhead mqh; 590 591 mqh.head = head; 592 mqh.limit = limit; 593 return mqh; 594 } 595 596 /* 597 * Get struct control_block_extended_exc_detail for CB. 598 */ 599 extern int gru_get_cb_exception_detail(void *cb, 600 struct control_block_extended_exc_detail *excdet); 601 602 #define GRU_EXC_STR_SIZE 256 603 604 605 /* 606 * Control block definition for checking status 607 */ 608 struct gru_control_block_status { 609 unsigned int icmd :1; 610 unsigned int ima :3; 611 unsigned int reserved0 :4; 612 unsigned int unused1 :24; 613 unsigned int unused2 :24; 614 unsigned int istatus :2; 615 unsigned int isubstatus :4; 616 unsigned int unused3 :2; 617 }; 618 619 /* Get CB status */ 620 static inline int gru_get_cb_status(void *cb) 621 { 622 struct gru_control_block_status *cbs = (void *)cb; 623 624 return cbs->istatus; 625 } 626 627 /* Get CB message queue substatus */ 628 static inline int gru_get_cb_message_queue_substatus(void *cb) 629 { 630 struct gru_control_block_status *cbs = (void *)cb; 631 632 return cbs->isubstatus & CBSS_MSG_QUEUE_MASK; 633 } 634 635 /* Get CB substatus */ 636 static inline int gru_get_cb_substatus(void *cb) 637 { 638 struct gru_control_block_status *cbs = (void *)cb; 639 640 return cbs->isubstatus; 641 } 642 643 /* 644 * User interface to check an instruction status. UPM and exceptions 645 * are handled automatically. However, this function does NOT wait 646 * for an active instruction to complete. 647 * 648 */ 649 static inline int gru_check_status(void *cb) 650 { 651 struct gru_control_block_status *cbs = (void *)cb; 652 int ret; 653 654 ret = cbs->istatus; 655 if (ret != CBS_ACTIVE) 656 ret = gru_check_status_proc(cb); 657 return ret; 658 } 659 660 /* 661 * User interface (via inline function) to wait for an instruction 662 * to complete. Completion status (IDLE or EXCEPTION is returned 663 * to the user. Exception due to hardware errors are automatically 664 * retried before returning an exception. 665 * 666 */ 667 static inline int gru_wait(void *cb) 668 { 669 return gru_wait_proc(cb); 670 } 671 672 /* 673 * Wait for CB to complete. Aborts program if error. (Note: error does NOT 674 * mean TLB mis - only fatal errors such as memory parity error or user 675 * bugs will cause termination. 676 */ 677 static inline void gru_wait_abort(void *cb) 678 { 679 gru_wait_abort_proc(cb); 680 } 681 682 /* 683 * Get a pointer to the start of a gseg 684 * p - Any valid pointer within the gseg 685 */ 686 static inline void *gru_get_gseg_pointer (void *p) 687 { 688 return (void *)((unsigned long)p & ~(GRU_GSEG_PAGESIZE - 1)); 689 } 690 691 /* 692 * Get a pointer to a control block 693 * gseg - GSeg address returned from gru_get_thread_gru_segment() 694 * index - index of desired CB 695 */ 696 static inline void *gru_get_cb_pointer(void *gseg, 697 int index) 698 { 699 return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE; 700 } 701 702 /* 703 * Get a pointer to a cacheline in the data segment portion of a GSeg 704 * gseg - GSeg address returned from gru_get_thread_gru_segment() 705 * index - index of desired cache line 706 */ 707 static inline void *gru_get_data_pointer(void *gseg, int index) 708 { 709 return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES; 710 } 711 712 /* 713 * Convert a vaddr into the tri index within the GSEG 714 * vaddr - virtual address of within gseg 715 */ 716 static inline int gru_get_tri(void *vaddr) 717 { 718 return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE; 719 } 720 #endif /* __GRU_INSTRUCTIONS_H__ */ 721