1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/fs.h> 10 #include <linux/uaccess.h> 11 #include <linux/string.h> 12 #include <linux/pci.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/mutex.h> 16 #include <linux/if_ether.h> 17 #include <linux/ctype.h> 18 #include <linux/dmi.h> 19 #include <linux/of.h> 20 21 #define PHUB_STATUS 0x00 /* Status Register offset */ 22 #define PHUB_CONTROL 0x04 /* Control Register offset */ 23 #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 24 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 25 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 26 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 27 offset */ 28 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 29 offset */ 30 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 31 (Intel EG20T PCH)*/ 32 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 33 offset(LAPIS Semicon ML7213) 34 */ 35 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 36 offset(LAPIS Semicon ML7223) 37 */ 38 39 /* MAX number of INT_REDUCE_CONTROL registers */ 40 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128 41 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801 42 #define PCH_MINOR_NOS 1 43 #define CLKCFG_CAN_50MHZ 0x12000000 44 #define CLKCFG_CANCLK_MASK 0xFF000000 45 #define CLKCFG_UART_MASK 0xFFFFFF 46 47 /* CM-iTC */ 48 #define CLKCFG_UART_48MHZ (1 << 16) 49 #define CLKCFG_UART_25MHZ (2 << 16) 50 #define CLKCFG_BAUDDIV (2 << 20) 51 #define CLKCFG_PLL2VCO (8 << 9) 52 #define CLKCFG_UARTCLKSEL (1 << 18) 53 54 /* Macros for ML7213 */ 55 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 56 57 /* Macros for ML7223 */ 58 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 59 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 60 61 /* Macros for ML7831 */ 62 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801 63 64 /* SROM ACCESS Macro */ 65 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 66 67 /* Registers address offset */ 68 #define PCH_PHUB_ID_REG 0x0000 69 #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 70 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 71 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 72 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 73 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 74 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 75 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 76 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 77 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 78 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 79 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 80 #define CLKCFG_REG_OFFSET 0x500 81 #define FUNCSEL_REG_OFFSET 0x508 82 83 #define PCH_PHUB_OROM_SIZE 15360 84 85 /** 86 * struct pch_phub_reg - PHUB register structure 87 * @phub_id_reg: PHUB_ID register val 88 * @q_pri_val_reg: QUEUE_PRI_VAL register val 89 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 90 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 91 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 92 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 93 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 94 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 95 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 96 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 97 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 98 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 99 * @clkcfg_reg: CLK CFG register val 100 * @funcsel_reg: Function select register value 101 * @pch_phub_base_address: Register base address 102 * @pch_phub_extrom_base_address: external rom base address 103 * @pch_mac_start_address: MAC address area start address 104 * @pch_opt_rom_start_address: Option ROM start address 105 * @ioh_type: Save IOH type 106 * @pdev: pointer to pci device struct 107 */ 108 struct pch_phub_reg { 109 u32 phub_id_reg; 110 u32 q_pri_val_reg; 111 u32 rc_q_maxsize_reg; 112 u32 bri_q_maxsize_reg; 113 u32 comp_resp_timeout_reg; 114 u32 bus_slave_control_reg; 115 u32 deadlock_avoid_type_reg; 116 u32 intpin_reg_wpermit_reg0; 117 u32 intpin_reg_wpermit_reg1; 118 u32 intpin_reg_wpermit_reg2; 119 u32 intpin_reg_wpermit_reg3; 120 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 121 u32 clkcfg_reg; 122 u32 funcsel_reg; 123 void __iomem *pch_phub_base_address; 124 void __iomem *pch_phub_extrom_base_address; 125 u32 pch_mac_start_address; 126 u32 pch_opt_rom_start_address; 127 int ioh_type; 128 struct pci_dev *pdev; 129 }; 130 131 /* SROM SPEC for MAC address assignment offset */ 132 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 133 134 static DEFINE_MUTEX(pch_phub_mutex); 135 136 /** 137 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 138 * @reg_addr_offset: Register offset address value. 139 * @data: Writing value. 140 * @mask: Mask value. 141 */ 142 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 143 unsigned int reg_addr_offset, 144 unsigned int data, unsigned int mask) 145 { 146 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 147 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 148 } 149 150 /* pch_phub_save_reg_conf - saves register configuration */ 151 static void __maybe_unused pch_phub_save_reg_conf(struct pci_dev *pdev) 152 { 153 unsigned int i; 154 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 155 156 void __iomem *p = chip->pch_phub_base_address; 157 158 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); 159 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); 160 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 161 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 162 chip->comp_resp_timeout_reg = 163 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 164 chip->bus_slave_control_reg = 165 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 166 chip->deadlock_avoid_type_reg = 167 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 168 chip->intpin_reg_wpermit_reg0 = 169 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 170 chip->intpin_reg_wpermit_reg1 = 171 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 172 chip->intpin_reg_wpermit_reg2 = 173 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 174 chip->intpin_reg_wpermit_reg3 = 175 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 176 dev_dbg(&pdev->dev, "%s : " 177 "chip->phub_id_reg=%x, " 178 "chip->q_pri_val_reg=%x, " 179 "chip->rc_q_maxsize_reg=%x, " 180 "chip->bri_q_maxsize_reg=%x, " 181 "chip->comp_resp_timeout_reg=%x, " 182 "chip->bus_slave_control_reg=%x, " 183 "chip->deadlock_avoid_type_reg=%x, " 184 "chip->intpin_reg_wpermit_reg0=%x, " 185 "chip->intpin_reg_wpermit_reg1=%x, " 186 "chip->intpin_reg_wpermit_reg2=%x, " 187 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 188 chip->phub_id_reg, 189 chip->q_pri_val_reg, 190 chip->rc_q_maxsize_reg, 191 chip->bri_q_maxsize_reg, 192 chip->comp_resp_timeout_reg, 193 chip->bus_slave_control_reg, 194 chip->deadlock_avoid_type_reg, 195 chip->intpin_reg_wpermit_reg0, 196 chip->intpin_reg_wpermit_reg1, 197 chip->intpin_reg_wpermit_reg2, 198 chip->intpin_reg_wpermit_reg3); 199 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 200 chip->int_reduce_control_reg[i] = 201 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 202 dev_dbg(&pdev->dev, "%s : " 203 "chip->int_reduce_control_reg[%d]=%x\n", 204 __func__, i, chip->int_reduce_control_reg[i]); 205 } 206 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); 207 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 208 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); 209 } 210 211 /* pch_phub_restore_reg_conf - restore register configuration */ 212 static void __maybe_unused pch_phub_restore_reg_conf(struct pci_dev *pdev) 213 { 214 unsigned int i; 215 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 216 void __iomem *p; 217 p = chip->pch_phub_base_address; 218 219 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); 220 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); 221 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 222 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 223 iowrite32(chip->comp_resp_timeout_reg, 224 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 225 iowrite32(chip->bus_slave_control_reg, 226 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 227 iowrite32(chip->deadlock_avoid_type_reg, 228 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 229 iowrite32(chip->intpin_reg_wpermit_reg0, 230 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 231 iowrite32(chip->intpin_reg_wpermit_reg1, 232 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 233 iowrite32(chip->intpin_reg_wpermit_reg2, 234 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 235 iowrite32(chip->intpin_reg_wpermit_reg3, 236 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 237 dev_dbg(&pdev->dev, "%s : " 238 "chip->phub_id_reg=%x, " 239 "chip->q_pri_val_reg=%x, " 240 "chip->rc_q_maxsize_reg=%x, " 241 "chip->bri_q_maxsize_reg=%x, " 242 "chip->comp_resp_timeout_reg=%x, " 243 "chip->bus_slave_control_reg=%x, " 244 "chip->deadlock_avoid_type_reg=%x, " 245 "chip->intpin_reg_wpermit_reg0=%x, " 246 "chip->intpin_reg_wpermit_reg1=%x, " 247 "chip->intpin_reg_wpermit_reg2=%x, " 248 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 249 chip->phub_id_reg, 250 chip->q_pri_val_reg, 251 chip->rc_q_maxsize_reg, 252 chip->bri_q_maxsize_reg, 253 chip->comp_resp_timeout_reg, 254 chip->bus_slave_control_reg, 255 chip->deadlock_avoid_type_reg, 256 chip->intpin_reg_wpermit_reg0, 257 chip->intpin_reg_wpermit_reg1, 258 chip->intpin_reg_wpermit_reg2, 259 chip->intpin_reg_wpermit_reg3); 260 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 261 iowrite32(chip->int_reduce_control_reg[i], 262 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 263 dev_dbg(&pdev->dev, "%s : " 264 "chip->int_reduce_control_reg[%d]=%x\n", 265 __func__, i, chip->int_reduce_control_reg[i]); 266 } 267 268 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); 269 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 270 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); 271 } 272 273 /** 274 * pch_phub_read_serial_rom() - Reading Serial ROM 275 * @offset_address: Serial ROM offset address to read. 276 * @data: Read buffer for specified Serial ROM value. 277 */ 278 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 279 unsigned int offset_address, u8 *data) 280 { 281 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 282 offset_address; 283 284 *data = ioread8(mem_addr); 285 } 286 287 /** 288 * pch_phub_write_serial_rom() - Writing Serial ROM 289 * @offset_address: Serial ROM offset address. 290 * @data: Serial ROM value to write. 291 */ 292 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 293 unsigned int offset_address, u8 data) 294 { 295 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 296 (offset_address & PCH_WORD_ADDR_MASK); 297 int i; 298 unsigned int word_data; 299 unsigned int pos; 300 unsigned int mask; 301 pos = (offset_address % 4) * 8; 302 mask = ~(0xFF << pos); 303 304 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 305 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 306 307 word_data = ioread32(mem_addr); 308 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 309 310 i = 0; 311 while (ioread8(chip->pch_phub_extrom_base_address + 312 PHUB_STATUS) != 0x00) { 313 msleep(1); 314 if (i == PHUB_TIMEOUT) 315 return -ETIMEDOUT; 316 i++; 317 } 318 319 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 320 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 321 322 return 0; 323 } 324 325 /** 326 * pch_phub_read_serial_rom_val() - Read Serial ROM value 327 * @offset_address: Serial ROM address offset value. 328 * @data: Serial ROM value to read. 329 */ 330 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 331 unsigned int offset_address, u8 *data) 332 { 333 unsigned int mem_addr; 334 335 mem_addr = chip->pch_mac_start_address + 336 pch_phub_mac_offset[offset_address]; 337 338 pch_phub_read_serial_rom(chip, mem_addr, data); 339 } 340 341 /** 342 * pch_phub_write_serial_rom_val() - writing Serial ROM value 343 * @offset_address: Serial ROM address offset value. 344 * @data: Serial ROM value. 345 */ 346 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 347 unsigned int offset_address, u8 data) 348 { 349 int retval; 350 unsigned int mem_addr; 351 352 mem_addr = chip->pch_mac_start_address + 353 pch_phub_mac_offset[offset_address]; 354 355 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 356 357 return retval; 358 } 359 360 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 361 * for Gigabit Ethernet MAC address 362 */ 363 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 364 { 365 int retval; 366 367 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 368 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 369 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 370 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 371 372 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 373 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 374 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 375 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 376 377 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 378 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 379 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 380 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 381 382 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 383 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 384 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 385 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 386 387 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 388 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 389 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 390 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 391 392 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 393 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 394 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 395 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 396 397 return retval; 398 } 399 400 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 401 * for Gigabit Ethernet MAC address 402 */ 403 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 404 { 405 int retval; 406 u32 offset_addr; 407 408 offset_addr = 0x200; 409 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 410 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 411 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 412 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 413 414 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 415 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 416 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 417 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 418 419 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 420 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 421 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 422 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 423 424 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 425 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 426 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 427 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 428 429 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 430 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 431 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 432 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 433 434 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 435 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 436 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 437 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 438 439 return retval; 440 } 441 442 /** 443 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 444 * @offset_address: Gigabit Ethernet MAC address offset value. 445 * @data: Buffer of the Gigabit Ethernet MAC address value. 446 */ 447 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 448 { 449 int i; 450 for (i = 0; i < ETH_ALEN; i++) 451 pch_phub_read_serial_rom_val(chip, i, &data[i]); 452 } 453 454 /** 455 * pch_phub_write_gbe_mac_addr() - Write MAC address 456 * @offset_address: Gigabit Ethernet MAC address offset value. 457 * @data: Gigabit Ethernet MAC address value. 458 */ 459 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 460 { 461 int retval; 462 int i; 463 464 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/ 465 retval = pch_phub_gbe_serial_rom_conf(chip); 466 else /* ML7223 */ 467 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 468 if (retval) 469 return retval; 470 471 for (i = 0; i < ETH_ALEN; i++) { 472 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 473 if (retval) 474 return retval; 475 } 476 477 return retval; 478 } 479 480 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 481 struct bin_attribute *attr, char *buf, 482 loff_t off, size_t count) 483 { 484 unsigned int rom_signature; 485 unsigned char rom_length; 486 unsigned int tmp; 487 unsigned int addr_offset; 488 unsigned int orom_size; 489 int ret; 490 int err; 491 ssize_t rom_size; 492 493 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 494 495 ret = mutex_lock_interruptible(&pch_phub_mutex); 496 if (ret) { 497 err = -ERESTARTSYS; 498 goto return_err_nomutex; 499 } 500 501 /* Get Rom signature */ 502 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 503 if (!chip->pch_phub_extrom_base_address) { 504 err = -ENODATA; 505 goto exrom_map_err; 506 } 507 508 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 509 (unsigned char *)&rom_signature); 510 rom_signature &= 0xff; 511 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 512 (unsigned char *)&tmp); 513 rom_signature |= (tmp & 0xff) << 8; 514 if (rom_signature == 0xAA55) { 515 pch_phub_read_serial_rom(chip, 516 chip->pch_opt_rom_start_address + 2, 517 &rom_length); 518 orom_size = rom_length * 512; 519 if (orom_size < off) { 520 addr_offset = 0; 521 goto return_ok; 522 } 523 if (orom_size < count) { 524 addr_offset = 0; 525 goto return_ok; 526 } 527 528 for (addr_offset = 0; addr_offset < count; addr_offset++) { 529 pch_phub_read_serial_rom(chip, 530 chip->pch_opt_rom_start_address + addr_offset + off, 531 &buf[addr_offset]); 532 } 533 } else { 534 err = -ENODATA; 535 goto return_err; 536 } 537 return_ok: 538 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 539 mutex_unlock(&pch_phub_mutex); 540 return addr_offset; 541 542 return_err: 543 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 544 exrom_map_err: 545 mutex_unlock(&pch_phub_mutex); 546 return_err_nomutex: 547 return err; 548 } 549 550 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 551 struct bin_attribute *attr, 552 char *buf, loff_t off, size_t count) 553 { 554 int err; 555 unsigned int addr_offset; 556 int ret; 557 ssize_t rom_size; 558 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 559 560 ret = mutex_lock_interruptible(&pch_phub_mutex); 561 if (ret) 562 return -ERESTARTSYS; 563 564 if (off > PCH_PHUB_OROM_SIZE) { 565 addr_offset = 0; 566 goto return_ok; 567 } 568 if (count > PCH_PHUB_OROM_SIZE) { 569 addr_offset = 0; 570 goto return_ok; 571 } 572 573 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 574 if (!chip->pch_phub_extrom_base_address) { 575 err = -ENOMEM; 576 goto exrom_map_err; 577 } 578 579 for (addr_offset = 0; addr_offset < count; addr_offset++) { 580 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 581 goto return_ok; 582 583 ret = pch_phub_write_serial_rom(chip, 584 chip->pch_opt_rom_start_address + addr_offset + off, 585 buf[addr_offset]); 586 if (ret) { 587 err = ret; 588 goto return_err; 589 } 590 } 591 592 return_ok: 593 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 594 mutex_unlock(&pch_phub_mutex); 595 return addr_offset; 596 597 return_err: 598 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 599 600 exrom_map_err: 601 mutex_unlock(&pch_phub_mutex); 602 return err; 603 } 604 605 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 606 char *buf) 607 { 608 u8 mac[8]; 609 struct pch_phub_reg *chip = dev_get_drvdata(dev); 610 ssize_t rom_size; 611 612 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 613 if (!chip->pch_phub_extrom_base_address) 614 return -ENOMEM; 615 616 pch_phub_read_gbe_mac_addr(chip, mac); 617 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 618 619 return sprintf(buf, "%pM\n", mac); 620 } 621 622 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 623 const char *buf, size_t count) 624 { 625 u8 mac[ETH_ALEN]; 626 ssize_t rom_size; 627 struct pch_phub_reg *chip = dev_get_drvdata(dev); 628 int ret; 629 630 if (!mac_pton(buf, mac)) 631 return -EINVAL; 632 633 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 634 if (!chip->pch_phub_extrom_base_address) 635 return -ENOMEM; 636 637 ret = pch_phub_write_gbe_mac_addr(chip, mac); 638 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 639 if (ret) 640 return ret; 641 642 return count; 643 } 644 645 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 646 647 static const struct bin_attribute pch_bin_attr = { 648 .attr = { 649 .name = "pch_firmware", 650 .mode = S_IRUGO | S_IWUSR, 651 }, 652 .size = PCH_PHUB_OROM_SIZE + 1, 653 .read = pch_phub_bin_read, 654 .write = pch_phub_bin_write, 655 }; 656 657 static int pch_phub_probe(struct pci_dev *pdev, 658 const struct pci_device_id *id) 659 { 660 int ret; 661 struct pch_phub_reg *chip; 662 663 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); 664 if (chip == NULL) 665 return -ENOMEM; 666 667 ret = pci_enable_device(pdev); 668 if (ret) { 669 dev_err(&pdev->dev, 670 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 671 goto err_pci_enable_dev; 672 } 673 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 674 ret); 675 676 ret = pci_request_regions(pdev, KBUILD_MODNAME); 677 if (ret) { 678 dev_err(&pdev->dev, 679 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 680 goto err_req_regions; 681 } 682 dev_dbg(&pdev->dev, "%s : " 683 "pci_request_regions returns %d\n", __func__, ret); 684 685 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 686 687 688 if (chip->pch_phub_base_address == NULL) { 689 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 690 ret = -ENOMEM; 691 goto err_pci_iomap; 692 } 693 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 694 "in pch_phub_base_address variable is %p\n", __func__, 695 chip->pch_phub_base_address); 696 697 chip->pdev = pdev; /* Save pci device struct */ 698 699 if (id->driver_data == 1) { /* EG20T PCH */ 700 const char *board_name; 701 unsigned int prefetch = 0x000affaa; 702 703 if (pdev->dev.of_node) 704 of_property_read_u32(pdev->dev.of_node, 705 "intel,eg20t-prefetch", 706 &prefetch); 707 708 ret = sysfs_create_file(&pdev->dev.kobj, 709 &dev_attr_pch_mac.attr); 710 if (ret) 711 goto err_sysfs_create; 712 713 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 714 if (ret) 715 goto exit_bin_attr; 716 717 pch_phub_read_modify_write_reg(chip, 718 (unsigned int)CLKCFG_REG_OFFSET, 719 CLKCFG_CAN_50MHZ, 720 CLKCFG_CANCLK_MASK); 721 722 /* quirk for CM-iTC board */ 723 board_name = dmi_get_system_info(DMI_BOARD_NAME); 724 if (board_name && strstr(board_name, "CM-iTC")) 725 pch_phub_read_modify_write_reg(chip, 726 (unsigned int)CLKCFG_REG_OFFSET, 727 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 728 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 729 CLKCFG_UART_MASK); 730 731 /* set the prefech value */ 732 iowrite32(prefetch, chip->pch_phub_base_address + 0x14); 733 /* set the interrupt delay value */ 734 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 735 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 736 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 737 738 /* quirk for MIPS Boston platform */ 739 if (pdev->dev.of_node) { 740 if (of_machine_is_compatible("img,boston")) { 741 pch_phub_read_modify_write_reg(chip, 742 (unsigned int)CLKCFG_REG_OFFSET, 743 CLKCFG_UART_25MHZ, 744 CLKCFG_UART_MASK); 745 } 746 } 747 } else if (id->driver_data == 2) { /* ML7213 IOH */ 748 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 749 if (ret) 750 goto err_sysfs_create; 751 /* set the prefech value 752 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 753 * Device4(SDIO #0,1,2):f 754 * Device6(SATA 2):f 755 * Device8(USB OHCI #0/ USB EHCI #0):a 756 */ 757 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 758 chip->pch_opt_rom_start_address =\ 759 PCH_PHUB_ROM_START_ADDR_ML7213; 760 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ 761 /* set the prefech value 762 * Device8(GbE) 763 */ 764 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 765 /* set the interrupt delay value */ 766 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 767 chip->pch_opt_rom_start_address =\ 768 PCH_PHUB_ROM_START_ADDR_ML7223; 769 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 770 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ 771 ret = sysfs_create_file(&pdev->dev.kobj, 772 &dev_attr_pch_mac.attr); 773 if (ret) 774 goto err_sysfs_create; 775 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 776 if (ret) 777 goto exit_bin_attr; 778 /* set the prefech value 779 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 780 * Device4(SDIO #0,1):f 781 * Device6(SATA 2):f 782 */ 783 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 784 chip->pch_opt_rom_start_address =\ 785 PCH_PHUB_ROM_START_ADDR_ML7223; 786 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 787 } else if (id->driver_data == 5) { /* ML7831 */ 788 ret = sysfs_create_file(&pdev->dev.kobj, 789 &dev_attr_pch_mac.attr); 790 if (ret) 791 goto err_sysfs_create; 792 793 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 794 if (ret) 795 goto exit_bin_attr; 796 797 /* set the prefech value */ 798 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 799 /* set the interrupt delay value */ 800 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 801 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 802 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 803 } 804 805 chip->ioh_type = id->driver_data; 806 pci_set_drvdata(pdev, chip); 807 808 return 0; 809 exit_bin_attr: 810 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 811 812 err_sysfs_create: 813 pci_iounmap(pdev, chip->pch_phub_base_address); 814 err_pci_iomap: 815 pci_release_regions(pdev); 816 err_req_regions: 817 pci_disable_device(pdev); 818 err_pci_enable_dev: 819 kfree(chip); 820 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 821 return ret; 822 } 823 824 static void pch_phub_remove(struct pci_dev *pdev) 825 { 826 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 827 828 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 829 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 830 pci_iounmap(pdev, chip->pch_phub_base_address); 831 pci_release_regions(pdev); 832 pci_disable_device(pdev); 833 kfree(chip); 834 } 835 836 static int __maybe_unused pch_phub_suspend(struct device *dev_d) 837 { 838 device_wakeup_disable(dev_d); 839 840 return 0; 841 } 842 843 static int __maybe_unused pch_phub_resume(struct device *dev_d) 844 { 845 device_wakeup_disable(dev_d); 846 847 return 0; 848 } 849 850 static const struct pci_device_id pch_phub_pcidev_id[] = { 851 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, 852 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, 853 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, }, 854 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, }, 855 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, }, 856 { } 857 }; 858 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 859 860 static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume); 861 862 static struct pci_driver pch_phub_driver = { 863 .name = "pch_phub", 864 .id_table = pch_phub_pcidev_id, 865 .probe = pch_phub_probe, 866 .remove = pch_phub_remove, 867 .driver.pm = &pch_phub_pm_ops, 868 }; 869 870 module_pci_driver(pch_phub_driver); 871 872 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB"); 873 MODULE_LICENSE("GPL"); 874