1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/sched.h> 15 #include <linux/interrupt.h> 16 17 #include <linux/pm_domain.h> 18 #include <linux/pm_runtime.h> 19 20 #include <linux/mei.h> 21 22 #include "mei_dev.h" 23 #include "client.h" 24 #include "hw-me-regs.h" 25 #include "hw-me.h" 26 27 /* mei_pci_tbl - PCI Device ID Table */ 28 static const struct pci_device_id mei_me_pci_tbl[] = { 29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 40 41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 50 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 55 56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 69 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 76 77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 79 80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 81 82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, 87 88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, 92 93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, 101 102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 106 107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, 108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 109 110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 111 112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, 113 114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, 115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, 116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, 117 118 /* required last entry */ 119 {0, } 120 }; 121 122 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 123 124 #ifdef CONFIG_PM 125 static inline void mei_me_set_pm_domain(struct mei_device *dev); 126 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 127 #else 128 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 129 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 130 #endif /* CONFIG_PM */ 131 132 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) 133 { 134 struct pci_dev *pdev = to_pci_dev(dev->dev); 135 136 return pci_read_config_dword(pdev, where, val); 137 } 138 139 /** 140 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 141 * 142 * @pdev: PCI device structure 143 * @cfg: per generation config 144 * 145 * Return: true if ME Interface is valid, false otherwise 146 */ 147 static bool mei_me_quirk_probe(struct pci_dev *pdev, 148 const struct mei_cfg *cfg) 149 { 150 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 151 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 152 return false; 153 } 154 155 return true; 156 } 157 158 /** 159 * mei_me_probe - Device Initialization Routine 160 * 161 * @pdev: PCI device structure 162 * @ent: entry in kcs_pci_tbl 163 * 164 * Return: 0 on success, <0 on failure. 165 */ 166 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 167 { 168 const struct mei_cfg *cfg; 169 struct mei_device *dev; 170 struct mei_me_hw *hw; 171 unsigned int irqflags; 172 int err; 173 174 cfg = mei_me_get_cfg(ent->driver_data); 175 if (!cfg) 176 return -ENODEV; 177 178 if (!mei_me_quirk_probe(pdev, cfg)) 179 return -ENODEV; 180 181 /* enable pci dev */ 182 err = pcim_enable_device(pdev); 183 if (err) { 184 dev_err(&pdev->dev, "failed to enable pci device.\n"); 185 goto end; 186 } 187 /* set PCI host mastering */ 188 pci_set_master(pdev); 189 /* pci request regions and mapping IO device memory for mei driver */ 190 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 191 if (err) { 192 dev_err(&pdev->dev, "failed to get pci regions.\n"); 193 goto end; 194 } 195 196 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 197 if (err) { 198 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 199 goto end; 200 } 201 202 /* allocates and initializes the mei dev structure */ 203 dev = mei_me_dev_init(&pdev->dev, cfg); 204 if (!dev) { 205 err = -ENOMEM; 206 goto end; 207 } 208 hw = to_me_hw(dev); 209 hw->mem_addr = pcim_iomap_table(pdev)[0]; 210 hw->read_fws = mei_me_read_fws; 211 212 pci_enable_msi(pdev); 213 214 hw->irq = pdev->irq; 215 216 /* request and enable interrupt */ 217 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 218 219 err = request_threaded_irq(pdev->irq, 220 mei_me_irq_quick_handler, 221 mei_me_irq_thread_handler, 222 irqflags, KBUILD_MODNAME, dev); 223 if (err) { 224 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 225 pdev->irq); 226 goto end; 227 } 228 229 if (mei_start(dev)) { 230 dev_err(&pdev->dev, "init hw failure.\n"); 231 err = -ENODEV; 232 goto release_irq; 233 } 234 235 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 236 pm_runtime_use_autosuspend(&pdev->dev); 237 238 err = mei_register(dev, &pdev->dev); 239 if (err) 240 goto stop; 241 242 pci_set_drvdata(pdev, dev); 243 244 /* 245 * MEI requires to resume from runtime suspend mode 246 * in order to perform link reset flow upon system suspend. 247 */ 248 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 249 250 /* 251 * ME maps runtime suspend/resume to D0i states, 252 * hence we need to go around native PCI runtime service which 253 * eventually brings the device into D3cold/hot state, 254 * but the mei device cannot wake up from D3 unlike from D0i3. 255 * To get around the PCI device native runtime pm, 256 * ME uses runtime pm domain handlers which take precedence 257 * over the driver's pm handlers. 258 */ 259 mei_me_set_pm_domain(dev); 260 261 if (mei_pg_is_enabled(dev)) { 262 pm_runtime_put_noidle(&pdev->dev); 263 if (hw->d0i3_supported) 264 pm_runtime_allow(&pdev->dev); 265 } 266 267 dev_dbg(&pdev->dev, "initialization successful.\n"); 268 269 return 0; 270 271 stop: 272 mei_stop(dev); 273 release_irq: 274 mei_cancel_work(dev); 275 mei_disable_interrupts(dev); 276 free_irq(pdev->irq, dev); 277 end: 278 dev_err(&pdev->dev, "initialization failed.\n"); 279 return err; 280 } 281 282 /** 283 * mei_me_shutdown - Device Removal Routine 284 * 285 * @pdev: PCI device structure 286 * 287 * mei_me_shutdown is called from the reboot notifier 288 * it's a simplified version of remove so we go down 289 * faster. 290 */ 291 static void mei_me_shutdown(struct pci_dev *pdev) 292 { 293 struct mei_device *dev; 294 295 dev = pci_get_drvdata(pdev); 296 if (!dev) 297 return; 298 299 dev_dbg(&pdev->dev, "shutdown\n"); 300 mei_stop(dev); 301 302 mei_me_unset_pm_domain(dev); 303 304 mei_disable_interrupts(dev); 305 free_irq(pdev->irq, dev); 306 } 307 308 /** 309 * mei_me_remove - Device Removal Routine 310 * 311 * @pdev: PCI device structure 312 * 313 * mei_me_remove is called by the PCI subsystem to alert the driver 314 * that it should release a PCI device. 315 */ 316 static void mei_me_remove(struct pci_dev *pdev) 317 { 318 struct mei_device *dev; 319 320 dev = pci_get_drvdata(pdev); 321 if (!dev) 322 return; 323 324 if (mei_pg_is_enabled(dev)) 325 pm_runtime_get_noresume(&pdev->dev); 326 327 dev_dbg(&pdev->dev, "stop\n"); 328 mei_stop(dev); 329 330 mei_me_unset_pm_domain(dev); 331 332 mei_disable_interrupts(dev); 333 334 free_irq(pdev->irq, dev); 335 336 mei_deregister(dev); 337 } 338 339 #ifdef CONFIG_PM_SLEEP 340 static int mei_me_pci_suspend(struct device *device) 341 { 342 struct pci_dev *pdev = to_pci_dev(device); 343 struct mei_device *dev = pci_get_drvdata(pdev); 344 345 if (!dev) 346 return -ENODEV; 347 348 dev_dbg(&pdev->dev, "suspend\n"); 349 350 mei_stop(dev); 351 352 mei_disable_interrupts(dev); 353 354 free_irq(pdev->irq, dev); 355 pci_disable_msi(pdev); 356 357 return 0; 358 } 359 360 static int mei_me_pci_resume(struct device *device) 361 { 362 struct pci_dev *pdev = to_pci_dev(device); 363 struct mei_device *dev; 364 unsigned int irqflags; 365 int err; 366 367 dev = pci_get_drvdata(pdev); 368 if (!dev) 369 return -ENODEV; 370 371 pci_enable_msi(pdev); 372 373 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 374 375 /* request and enable interrupt */ 376 err = request_threaded_irq(pdev->irq, 377 mei_me_irq_quick_handler, 378 mei_me_irq_thread_handler, 379 irqflags, KBUILD_MODNAME, dev); 380 381 if (err) { 382 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 383 pdev->irq); 384 return err; 385 } 386 387 err = mei_restart(dev); 388 if (err) 389 return err; 390 391 /* Start timer if stopped in suspend */ 392 schedule_delayed_work(&dev->timer_work, HZ); 393 394 return 0; 395 } 396 #endif /* CONFIG_PM_SLEEP */ 397 398 #ifdef CONFIG_PM 399 static int mei_me_pm_runtime_idle(struct device *device) 400 { 401 struct mei_device *dev; 402 403 dev_dbg(device, "rpm: me: runtime_idle\n"); 404 405 dev = dev_get_drvdata(device); 406 if (!dev) 407 return -ENODEV; 408 if (mei_write_is_idle(dev)) 409 pm_runtime_autosuspend(device); 410 411 return -EBUSY; 412 } 413 414 static int mei_me_pm_runtime_suspend(struct device *device) 415 { 416 struct mei_device *dev; 417 int ret; 418 419 dev_dbg(device, "rpm: me: runtime suspend\n"); 420 421 dev = dev_get_drvdata(device); 422 if (!dev) 423 return -ENODEV; 424 425 mutex_lock(&dev->device_lock); 426 427 if (mei_write_is_idle(dev)) 428 ret = mei_me_pg_enter_sync(dev); 429 else 430 ret = -EAGAIN; 431 432 mutex_unlock(&dev->device_lock); 433 434 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); 435 436 if (ret && ret != -EAGAIN) 437 schedule_work(&dev->reset_work); 438 439 return ret; 440 } 441 442 static int mei_me_pm_runtime_resume(struct device *device) 443 { 444 struct mei_device *dev; 445 int ret; 446 447 dev_dbg(device, "rpm: me: runtime resume\n"); 448 449 dev = dev_get_drvdata(device); 450 if (!dev) 451 return -ENODEV; 452 453 mutex_lock(&dev->device_lock); 454 455 ret = mei_me_pg_exit_sync(dev); 456 457 mutex_unlock(&dev->device_lock); 458 459 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); 460 461 if (ret) 462 schedule_work(&dev->reset_work); 463 464 return ret; 465 } 466 467 /** 468 * mei_me_set_pm_domain - fill and set pm domain structure for device 469 * 470 * @dev: mei_device 471 */ 472 static inline void mei_me_set_pm_domain(struct mei_device *dev) 473 { 474 struct pci_dev *pdev = to_pci_dev(dev->dev); 475 476 if (pdev->dev.bus && pdev->dev.bus->pm) { 477 dev->pg_domain.ops = *pdev->dev.bus->pm; 478 479 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; 480 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; 481 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; 482 483 dev_pm_domain_set(&pdev->dev, &dev->pg_domain); 484 } 485 } 486 487 /** 488 * mei_me_unset_pm_domain - clean pm domain structure for device 489 * 490 * @dev: mei_device 491 */ 492 static inline void mei_me_unset_pm_domain(struct mei_device *dev) 493 { 494 /* stop using pm callbacks if any */ 495 dev_pm_domain_set(dev->dev, NULL); 496 } 497 498 static const struct dev_pm_ops mei_me_pm_ops = { 499 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, 500 mei_me_pci_resume) 501 SET_RUNTIME_PM_OPS( 502 mei_me_pm_runtime_suspend, 503 mei_me_pm_runtime_resume, 504 mei_me_pm_runtime_idle) 505 }; 506 507 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 508 #else 509 #define MEI_ME_PM_OPS NULL 510 #endif /* CONFIG_PM */ 511 /* 512 * PCI driver structure 513 */ 514 static struct pci_driver mei_me_driver = { 515 .name = KBUILD_MODNAME, 516 .id_table = mei_me_pci_tbl, 517 .probe = mei_me_probe, 518 .remove = mei_me_remove, 519 .shutdown = mei_me_shutdown, 520 .driver.pm = MEI_ME_PM_OPS, 521 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, 522 }; 523 524 module_pci_driver(mei_me_driver); 525 526 MODULE_AUTHOR("Intel Corporation"); 527 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 528 MODULE_LICENSE("GPL v2"); 529