19fff0425STomas Winkler /* SPDX-License-Identifier: GPL-2.0 */ 2266f6178STomas Winkler /* 3*1e55b609STomas Winkler * Copyright (c) 2013-2016, Intel Corporation. All rights reserved. 4266f6178STomas Winkler * Intel Management Engine Interface (Intel MEI) Linux driver 5266f6178STomas Winkler */ 6266f6178STomas Winkler 7266f6178STomas Winkler #ifndef _MEI_HW_TXE_H_ 8266f6178STomas Winkler #define _MEI_HW_TXE_H_ 9266f6178STomas Winkler 104a22176aSStephen Rothwell #include <linux/irqreturn.h> 114a22176aSStephen Rothwell 12266f6178STomas Winkler #include "hw.h" 13266f6178STomas Winkler #include "hw-txe-regs.h" 14266f6178STomas Winkler 15cfe5ab85SAlexander Usyskin #define MEI_TXI_RPM_TIMEOUT 500 /* ms */ 16cfe5ab85SAlexander Usyskin 17266f6178STomas Winkler /* Flatten Hierarchy interrupt cause */ 18266f6178STomas Winkler #define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */ 19266f6178STomas Winkler #define TXE_INTR_READINESS HISR_INT_0_STS 20266f6178STomas Winkler #define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */ 21266f6178STomas Winkler #define TXE_INTR_ALIVENESS HISR_INT_1_STS 22266f6178STomas Winkler #define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */ 23266f6178STomas Winkler #define TXE_INTR_OUT_DB HISR_INT_2_STS 24266f6178STomas Winkler #define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */ 25266f6178STomas Winkler #define TXE_INTR_IN_READY BIT(8) 26266f6178STomas Winkler 27266f6178STomas Winkler /** 28266f6178STomas Winkler * struct mei_txe_hw - txe hardware specifics 29266f6178STomas Winkler * 30266f6178STomas Winkler * @mem_addr: SeC and BRIDGE bars 31266f6178STomas Winkler * @aliveness: aliveness (power gating) state of the hardware 32266f6178STomas Winkler * @readiness: readiness state of the hardware 33ce23139cSAlexander Usyskin * @slots: number of empty slots 34964a2331STomas Winkler * @wait_aliveness_resp: aliveness wait queue 35266f6178STomas Winkler * @intr_cause: translated interrupt cause 36266f6178STomas Winkler */ 37266f6178STomas Winkler struct mei_txe_hw { 38f8a09605STomas Winkler void __iomem * const *mem_addr; 39266f6178STomas Winkler u32 aliveness; 40266f6178STomas Winkler u32 readiness; 419d098192STomas Winkler u32 slots; 42266f6178STomas Winkler 43964a2331STomas Winkler wait_queue_head_t wait_aliveness_resp; 44266f6178STomas Winkler 45266f6178STomas Winkler unsigned long intr_cause; 46266f6178STomas Winkler }; 47266f6178STomas Winkler 48266f6178STomas Winkler #define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw) 49266f6178STomas Winkler hw_txe_to_mei(struct mei_txe_hw * hw)50266f6178STomas Winklerstatic inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw) 51266f6178STomas Winkler { 52266f6178STomas Winkler return container_of((void *)hw, struct mei_device, hw); 53266f6178STomas Winkler } 54266f6178STomas Winkler 554ad96db6STomas Winkler struct mei_device *mei_txe_dev_init(struct pci_dev *pdev); 56266f6178STomas Winkler 57266f6178STomas Winkler irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id); 58266f6178STomas Winkler irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id); 59266f6178STomas Winkler 60266f6178STomas Winkler int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req); 61266f6178STomas Winkler 62266f6178STomas Winkler int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range); 63266f6178STomas Winkler 64266f6178STomas Winkler 65266f6178STomas Winkler #endif /* _MEI_HW_TXE_H_ */ 66