1*6a3d119bSBalaji Rao /* NXP PCF50633 GPIO Driver 2*6a3d119bSBalaji Rao * 3*6a3d119bSBalaji Rao * (C) 2006-2008 by Openmoko, Inc. 4*6a3d119bSBalaji Rao * Author: Balaji Rao <balajirrao@openmoko.org> 5*6a3d119bSBalaji Rao * All rights reserved. 6*6a3d119bSBalaji Rao * 7*6a3d119bSBalaji Rao * Broken down from monstrous PCF50633 driver mainly by 8*6a3d119bSBalaji Rao * Harald Welte, Andy Green and Werner Almesberger 9*6a3d119bSBalaji Rao * 10*6a3d119bSBalaji Rao * This program is free software; you can redistribute it and/or modify it 11*6a3d119bSBalaji Rao * under the terms of the GNU General Public License as published by the 12*6a3d119bSBalaji Rao * Free Software Foundation; either version 2 of the License, or (at your 13*6a3d119bSBalaji Rao * option) any later version. 14*6a3d119bSBalaji Rao * 15*6a3d119bSBalaji Rao */ 16*6a3d119bSBalaji Rao 17*6a3d119bSBalaji Rao #include <linux/kernel.h> 18*6a3d119bSBalaji Rao 19*6a3d119bSBalaji Rao #include <linux/mfd/pcf50633/core.h> 20*6a3d119bSBalaji Rao #include <linux/mfd/pcf50633/gpio.h> 21*6a3d119bSBalaji Rao 22*6a3d119bSBalaji Rao enum pcf50633_regulator_id { 23*6a3d119bSBalaji Rao PCF50633_REGULATOR_AUTO, 24*6a3d119bSBalaji Rao PCF50633_REGULATOR_DOWN1, 25*6a3d119bSBalaji Rao PCF50633_REGULATOR_DOWN2, 26*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO1, 27*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO2, 28*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO3, 29*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO4, 30*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO5, 31*6a3d119bSBalaji Rao PCF50633_REGULATOR_LDO6, 32*6a3d119bSBalaji Rao PCF50633_REGULATOR_HCLDO, 33*6a3d119bSBalaji Rao PCF50633_REGULATOR_MEMLDO, 34*6a3d119bSBalaji Rao }; 35*6a3d119bSBalaji Rao 36*6a3d119bSBalaji Rao #define PCF50633_REG_AUTOOUT 0x1a 37*6a3d119bSBalaji Rao #define PCF50633_REG_DOWN1OUT 0x1e 38*6a3d119bSBalaji Rao #define PCF50633_REG_DOWN2OUT 0x22 39*6a3d119bSBalaji Rao #define PCF50633_REG_MEMLDOOUT 0x26 40*6a3d119bSBalaji Rao #define PCF50633_REG_LDO1OUT 0x2d 41*6a3d119bSBalaji Rao #define PCF50633_REG_LDO2OUT 0x2f 42*6a3d119bSBalaji Rao #define PCF50633_REG_LDO3OUT 0x31 43*6a3d119bSBalaji Rao #define PCF50633_REG_LDO4OUT 0x33 44*6a3d119bSBalaji Rao #define PCF50633_REG_LDO5OUT 0x35 45*6a3d119bSBalaji Rao #define PCF50633_REG_LDO6OUT 0x37 46*6a3d119bSBalaji Rao #define PCF50633_REG_HCLDOOUT 0x39 47*6a3d119bSBalaji Rao 48*6a3d119bSBalaji Rao static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = { 49*6a3d119bSBalaji Rao [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT, 50*6a3d119bSBalaji Rao [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT, 51*6a3d119bSBalaji Rao [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT, 52*6a3d119bSBalaji Rao [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT, 53*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT, 54*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT, 55*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT, 56*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT, 57*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT, 58*6a3d119bSBalaji Rao [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT, 59*6a3d119bSBalaji Rao [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT, 60*6a3d119bSBalaji Rao }; 61*6a3d119bSBalaji Rao 62*6a3d119bSBalaji Rao int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) 63*6a3d119bSBalaji Rao { 64*6a3d119bSBalaji Rao u8 reg; 65*6a3d119bSBalaji Rao 66*6a3d119bSBalaji Rao reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; 67*6a3d119bSBalaji Rao 68*6a3d119bSBalaji Rao return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); 69*6a3d119bSBalaji Rao } 70*6a3d119bSBalaji Rao EXPORT_SYMBOL_GPL(pcf50633_gpio_set); 71*6a3d119bSBalaji Rao 72*6a3d119bSBalaji Rao u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio) 73*6a3d119bSBalaji Rao { 74*6a3d119bSBalaji Rao u8 reg, val; 75*6a3d119bSBalaji Rao 76*6a3d119bSBalaji Rao reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; 77*6a3d119bSBalaji Rao val = pcf50633_reg_read(pcf, reg) & 0x07; 78*6a3d119bSBalaji Rao 79*6a3d119bSBalaji Rao return val; 80*6a3d119bSBalaji Rao } 81*6a3d119bSBalaji Rao EXPORT_SYMBOL_GPL(pcf50633_gpio_get); 82*6a3d119bSBalaji Rao 83*6a3d119bSBalaji Rao int pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert) 84*6a3d119bSBalaji Rao { 85*6a3d119bSBalaji Rao u8 val, reg; 86*6a3d119bSBalaji Rao 87*6a3d119bSBalaji Rao reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; 88*6a3d119bSBalaji Rao val = !!invert << 3; 89*6a3d119bSBalaji Rao 90*6a3d119bSBalaji Rao return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); 91*6a3d119bSBalaji Rao } 92*6a3d119bSBalaji Rao EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set); 93*6a3d119bSBalaji Rao 94*6a3d119bSBalaji Rao int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio) 95*6a3d119bSBalaji Rao { 96*6a3d119bSBalaji Rao u8 reg, val; 97*6a3d119bSBalaji Rao 98*6a3d119bSBalaji Rao reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; 99*6a3d119bSBalaji Rao val = pcf50633_reg_read(pcf, reg); 100*6a3d119bSBalaji Rao 101*6a3d119bSBalaji Rao return val & (1 << 3); 102*6a3d119bSBalaji Rao } 103*6a3d119bSBalaji Rao EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get); 104*6a3d119bSBalaji Rao 105*6a3d119bSBalaji Rao int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf, 106*6a3d119bSBalaji Rao int gpio, int regulator, int on) 107*6a3d119bSBalaji Rao { 108*6a3d119bSBalaji Rao u8 reg, val, mask; 109*6a3d119bSBalaji Rao 110*6a3d119bSBalaji Rao /* the *ENA register is always one after the *OUT register */ 111*6a3d119bSBalaji Rao reg = pcf50633_regulator_registers[regulator] + 1; 112*6a3d119bSBalaji Rao 113*6a3d119bSBalaji Rao val = !!on << (gpio - PCF50633_GPIO1); 114*6a3d119bSBalaji Rao mask = 1 << (gpio - PCF50633_GPIO1); 115*6a3d119bSBalaji Rao 116*6a3d119bSBalaji Rao return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); 117*6a3d119bSBalaji Rao } 118*6a3d119bSBalaji Rao EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set); 119