1*d3ea2127SMarek Vasut /* 2*d3ea2127SMarek Vasut * ROHM BD9571MWV-M MFD driver 3*d3ea2127SMarek Vasut * 4*d3ea2127SMarek Vasut * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> 5*d3ea2127SMarek Vasut * 6*d3ea2127SMarek Vasut * This program is free software; you can redistribute it and/or 7*d3ea2127SMarek Vasut * modify it under the terms of the GNU General Public License version 2 as 8*d3ea2127SMarek Vasut * published by the Free Software Foundation. 9*d3ea2127SMarek Vasut * 10*d3ea2127SMarek Vasut * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11*d3ea2127SMarek Vasut * kind, whether expressed or implied; without even the implied warranty 12*d3ea2127SMarek Vasut * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*d3ea2127SMarek Vasut * GNU General Public License version 2 for more details. 14*d3ea2127SMarek Vasut * 15*d3ea2127SMarek Vasut * Based on the TPS65086 driver 16*d3ea2127SMarek Vasut */ 17*d3ea2127SMarek Vasut 18*d3ea2127SMarek Vasut #include <linux/i2c.h> 19*d3ea2127SMarek Vasut #include <linux/interrupt.h> 20*d3ea2127SMarek Vasut #include <linux/mfd/core.h> 21*d3ea2127SMarek Vasut #include <linux/module.h> 22*d3ea2127SMarek Vasut 23*d3ea2127SMarek Vasut #include <linux/mfd/bd9571mwv.h> 24*d3ea2127SMarek Vasut 25*d3ea2127SMarek Vasut static const struct mfd_cell bd9571mwv_cells[] = { 26*d3ea2127SMarek Vasut { .name = "bd9571mwv-regulator", }, 27*d3ea2127SMarek Vasut { .name = "bd9571mwv-gpio", }, 28*d3ea2127SMarek Vasut }; 29*d3ea2127SMarek Vasut 30*d3ea2127SMarek Vasut static const struct regmap_range bd9571mwv_readable_yes_ranges[] = { 31*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION), 32*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_AVS_SET_MONI, BD9571MWV_AVS_DVFS_VID(3)), 33*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_VD18_VID, BD9571MWV_VD33_VID), 34*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_VINIT), 35*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_DVFS_SETVMAX, BD9571MWV_DVFS_MONIVDAC), 36*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN), 37*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK), 38*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK), 39*d3ea2127SMarek Vasut }; 40*d3ea2127SMarek Vasut 41*d3ea2127SMarek Vasut static const struct regmap_access_table bd9571mwv_readable_table = { 42*d3ea2127SMarek Vasut .yes_ranges = bd9571mwv_readable_yes_ranges, 43*d3ea2127SMarek Vasut .n_yes_ranges = ARRAY_SIZE(bd9571mwv_readable_yes_ranges), 44*d3ea2127SMarek Vasut }; 45*d3ea2127SMarek Vasut 46*d3ea2127SMarek Vasut static const struct regmap_range bd9571mwv_writable_yes_ranges[] = { 47*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_AVS_VD09_VID(0), BD9571MWV_AVS_VD09_VID(3)), 48*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID), 49*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT), 50*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK), 51*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK), 52*d3ea2127SMarek Vasut }; 53*d3ea2127SMarek Vasut 54*d3ea2127SMarek Vasut static const struct regmap_access_table bd9571mwv_writable_table = { 55*d3ea2127SMarek Vasut .yes_ranges = bd9571mwv_writable_yes_ranges, 56*d3ea2127SMarek Vasut .n_yes_ranges = ARRAY_SIZE(bd9571mwv_writable_yes_ranges), 57*d3ea2127SMarek Vasut }; 58*d3ea2127SMarek Vasut 59*d3ea2127SMarek Vasut static const struct regmap_range bd9571mwv_volatile_yes_ranges[] = { 60*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN), 61*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT), 62*d3ea2127SMarek Vasut regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ), 63*d3ea2127SMarek Vasut }; 64*d3ea2127SMarek Vasut 65*d3ea2127SMarek Vasut static const struct regmap_access_table bd9571mwv_volatile_table = { 66*d3ea2127SMarek Vasut .yes_ranges = bd9571mwv_volatile_yes_ranges, 67*d3ea2127SMarek Vasut .n_yes_ranges = ARRAY_SIZE(bd9571mwv_volatile_yes_ranges), 68*d3ea2127SMarek Vasut }; 69*d3ea2127SMarek Vasut 70*d3ea2127SMarek Vasut static const struct regmap_config bd9571mwv_regmap_config = { 71*d3ea2127SMarek Vasut .reg_bits = 8, 72*d3ea2127SMarek Vasut .val_bits = 8, 73*d3ea2127SMarek Vasut .cache_type = REGCACHE_RBTREE, 74*d3ea2127SMarek Vasut .rd_table = &bd9571mwv_readable_table, 75*d3ea2127SMarek Vasut .wr_table = &bd9571mwv_writable_table, 76*d3ea2127SMarek Vasut .volatile_table = &bd9571mwv_volatile_table, 77*d3ea2127SMarek Vasut .max_register = 0xff, 78*d3ea2127SMarek Vasut }; 79*d3ea2127SMarek Vasut 80*d3ea2127SMarek Vasut static const struct regmap_irq bd9571mwv_irqs[] = { 81*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_MD1, 0, 82*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_MD1_INT), 83*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E1, 0, 84*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_MD2_E1_INT), 85*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E2, 0, 86*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_MD2_E2_INT), 87*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_PROT_ERR, 0, 88*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_PROT_ERR_INT), 89*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_GP, 0, 90*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_GP_INT), 91*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_128H_OF, 0, 92*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_128H_OF_INT), 93*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_WDT_OF, 0, 94*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_WDT_OF_INT), 95*d3ea2127SMarek Vasut REGMAP_IRQ_REG(BD9571MWV_IRQ_BKUP_TRG, 0, 96*d3ea2127SMarek Vasut BD9571MWV_INT_INTREQ_BKUP_TRG_INT), 97*d3ea2127SMarek Vasut }; 98*d3ea2127SMarek Vasut 99*d3ea2127SMarek Vasut static struct regmap_irq_chip bd9571mwv_irq_chip = { 100*d3ea2127SMarek Vasut .name = "bd9571mwv", 101*d3ea2127SMarek Vasut .status_base = BD9571MWV_INT_INTREQ, 102*d3ea2127SMarek Vasut .mask_base = BD9571MWV_INT_INTMASK, 103*d3ea2127SMarek Vasut .ack_base = BD9571MWV_INT_INTREQ, 104*d3ea2127SMarek Vasut .init_ack_masked = true, 105*d3ea2127SMarek Vasut .num_regs = 1, 106*d3ea2127SMarek Vasut .irqs = bd9571mwv_irqs, 107*d3ea2127SMarek Vasut .num_irqs = ARRAY_SIZE(bd9571mwv_irqs), 108*d3ea2127SMarek Vasut }; 109*d3ea2127SMarek Vasut 110*d3ea2127SMarek Vasut static int bd9571mwv_identify(struct bd9571mwv *bd) 111*d3ea2127SMarek Vasut { 112*d3ea2127SMarek Vasut struct device *dev = bd->dev; 113*d3ea2127SMarek Vasut unsigned int value; 114*d3ea2127SMarek Vasut int ret; 115*d3ea2127SMarek Vasut 116*d3ea2127SMarek Vasut ret = regmap_read(bd->regmap, BD9571MWV_VENDOR_CODE, &value); 117*d3ea2127SMarek Vasut if (ret) { 118*d3ea2127SMarek Vasut dev_err(dev, "Failed to read vendor code register (ret=%i)\n", 119*d3ea2127SMarek Vasut ret); 120*d3ea2127SMarek Vasut return ret; 121*d3ea2127SMarek Vasut } 122*d3ea2127SMarek Vasut 123*d3ea2127SMarek Vasut if (value != BD9571MWV_VENDOR_CODE_VAL) { 124*d3ea2127SMarek Vasut dev_err(dev, "Invalid vendor code ID %02x (expected %02x)\n", 125*d3ea2127SMarek Vasut value, BD9571MWV_VENDOR_CODE_VAL); 126*d3ea2127SMarek Vasut return -EINVAL; 127*d3ea2127SMarek Vasut } 128*d3ea2127SMarek Vasut 129*d3ea2127SMarek Vasut ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_CODE, &value); 130*d3ea2127SMarek Vasut if (ret) { 131*d3ea2127SMarek Vasut dev_err(dev, "Failed to read product code register (ret=%i)\n", 132*d3ea2127SMarek Vasut ret); 133*d3ea2127SMarek Vasut return ret; 134*d3ea2127SMarek Vasut } 135*d3ea2127SMarek Vasut 136*d3ea2127SMarek Vasut if (value != BD9571MWV_PRODUCT_CODE_VAL) { 137*d3ea2127SMarek Vasut dev_err(dev, "Invalid product code ID %02x (expected %02x)\n", 138*d3ea2127SMarek Vasut value, BD9571MWV_PRODUCT_CODE_VAL); 139*d3ea2127SMarek Vasut return -EINVAL; 140*d3ea2127SMarek Vasut } 141*d3ea2127SMarek Vasut 142*d3ea2127SMarek Vasut ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_REVISION, &value); 143*d3ea2127SMarek Vasut if (ret) { 144*d3ea2127SMarek Vasut dev_err(dev, "Failed to read revision register (ret=%i)\n", 145*d3ea2127SMarek Vasut ret); 146*d3ea2127SMarek Vasut return ret; 147*d3ea2127SMarek Vasut } 148*d3ea2127SMarek Vasut 149*d3ea2127SMarek Vasut dev_info(dev, "Device: BD9571MWV rev. %d\n", value & 0xff); 150*d3ea2127SMarek Vasut 151*d3ea2127SMarek Vasut return 0; 152*d3ea2127SMarek Vasut } 153*d3ea2127SMarek Vasut 154*d3ea2127SMarek Vasut static int bd9571mwv_probe(struct i2c_client *client, 155*d3ea2127SMarek Vasut const struct i2c_device_id *ids) 156*d3ea2127SMarek Vasut { 157*d3ea2127SMarek Vasut struct bd9571mwv *bd; 158*d3ea2127SMarek Vasut int ret; 159*d3ea2127SMarek Vasut 160*d3ea2127SMarek Vasut bd = devm_kzalloc(&client->dev, sizeof(*bd), GFP_KERNEL); 161*d3ea2127SMarek Vasut if (!bd) 162*d3ea2127SMarek Vasut return -ENOMEM; 163*d3ea2127SMarek Vasut 164*d3ea2127SMarek Vasut i2c_set_clientdata(client, bd); 165*d3ea2127SMarek Vasut bd->dev = &client->dev; 166*d3ea2127SMarek Vasut bd->irq = client->irq; 167*d3ea2127SMarek Vasut 168*d3ea2127SMarek Vasut bd->regmap = devm_regmap_init_i2c(client, &bd9571mwv_regmap_config); 169*d3ea2127SMarek Vasut if (IS_ERR(bd->regmap)) { 170*d3ea2127SMarek Vasut dev_err(bd->dev, "Failed to initialize register map\n"); 171*d3ea2127SMarek Vasut return PTR_ERR(bd->regmap); 172*d3ea2127SMarek Vasut } 173*d3ea2127SMarek Vasut 174*d3ea2127SMarek Vasut ret = bd9571mwv_identify(bd); 175*d3ea2127SMarek Vasut if (ret) 176*d3ea2127SMarek Vasut return ret; 177*d3ea2127SMarek Vasut 178*d3ea2127SMarek Vasut ret = regmap_add_irq_chip(bd->regmap, bd->irq, IRQF_ONESHOT, 0, 179*d3ea2127SMarek Vasut &bd9571mwv_irq_chip, &bd->irq_data); 180*d3ea2127SMarek Vasut if (ret) { 181*d3ea2127SMarek Vasut dev_err(bd->dev, "Failed to register IRQ chip\n"); 182*d3ea2127SMarek Vasut return ret; 183*d3ea2127SMarek Vasut } 184*d3ea2127SMarek Vasut 185*d3ea2127SMarek Vasut ret = mfd_add_devices(bd->dev, PLATFORM_DEVID_AUTO, bd9571mwv_cells, 186*d3ea2127SMarek Vasut ARRAY_SIZE(bd9571mwv_cells), NULL, 0, 187*d3ea2127SMarek Vasut regmap_irq_get_domain(bd->irq_data)); 188*d3ea2127SMarek Vasut if (ret) { 189*d3ea2127SMarek Vasut regmap_del_irq_chip(bd->irq, bd->irq_data); 190*d3ea2127SMarek Vasut return ret; 191*d3ea2127SMarek Vasut } 192*d3ea2127SMarek Vasut 193*d3ea2127SMarek Vasut return 0; 194*d3ea2127SMarek Vasut } 195*d3ea2127SMarek Vasut 196*d3ea2127SMarek Vasut static int bd9571mwv_remove(struct i2c_client *client) 197*d3ea2127SMarek Vasut { 198*d3ea2127SMarek Vasut struct bd9571mwv *bd = i2c_get_clientdata(client); 199*d3ea2127SMarek Vasut 200*d3ea2127SMarek Vasut regmap_del_irq_chip(bd->irq, bd->irq_data); 201*d3ea2127SMarek Vasut 202*d3ea2127SMarek Vasut return 0; 203*d3ea2127SMarek Vasut } 204*d3ea2127SMarek Vasut 205*d3ea2127SMarek Vasut static const struct of_device_id bd9571mwv_of_match_table[] = { 206*d3ea2127SMarek Vasut { .compatible = "rohm,bd9571mwv", }, 207*d3ea2127SMarek Vasut { /* sentinel */ } 208*d3ea2127SMarek Vasut }; 209*d3ea2127SMarek Vasut MODULE_DEVICE_TABLE(of, bd9571mwv_of_match_table); 210*d3ea2127SMarek Vasut 211*d3ea2127SMarek Vasut static const struct i2c_device_id bd9571mwv_id_table[] = { 212*d3ea2127SMarek Vasut { "bd9571mwv", 0 }, 213*d3ea2127SMarek Vasut { /* sentinel */ } 214*d3ea2127SMarek Vasut }; 215*d3ea2127SMarek Vasut MODULE_DEVICE_TABLE(i2c, bd9571mwv_id_table); 216*d3ea2127SMarek Vasut 217*d3ea2127SMarek Vasut static struct i2c_driver bd9571mwv_driver = { 218*d3ea2127SMarek Vasut .driver = { 219*d3ea2127SMarek Vasut .name = "bd9571mwv", 220*d3ea2127SMarek Vasut .of_match_table = bd9571mwv_of_match_table, 221*d3ea2127SMarek Vasut }, 222*d3ea2127SMarek Vasut .probe = bd9571mwv_probe, 223*d3ea2127SMarek Vasut .remove = bd9571mwv_remove, 224*d3ea2127SMarek Vasut .id_table = bd9571mwv_id_table, 225*d3ea2127SMarek Vasut }; 226*d3ea2127SMarek Vasut module_i2c_driver(bd9571mwv_driver); 227*d3ea2127SMarek Vasut 228*d3ea2127SMarek Vasut MODULE_AUTHOR("Marek Vasut <marek.vasut+renesas@gmail.com>"); 229*d3ea2127SMarek Vasut MODULE_DESCRIPTION("BD9571MWV PMIC Driver"); 230*d3ea2127SMarek Vasut MODULE_LICENSE("GPL v2"); 231