1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <soc/mediatek/smi.h> 17 #include <dt-bindings/memory/mt2701-larb-port.h> 18 #include <dt-bindings/memory/mtk-memory-port.h> 19 20 /* SMI COMMON */ 21 #define SMI_L1LEN 0x100 22 23 #define SMI_BUS_SEL 0x220 24 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 25 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 26 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 27 28 #define SMI_M4U_TH 0x234 29 #define SMI_FIFO_TH1 0x238 30 #define SMI_FIFO_TH2 0x23c 31 #define SMI_DCM 0x300 32 #define SMI_DUMMY 0x444 33 34 /* SMI LARB */ 35 #define SMI_LARB_CMD_THRT_CON 0x24 36 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 37 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 38 39 #define SMI_LARB_SW_FLAG 0x40 40 #define SMI_LARB_SW_FLAG_1 0x1 41 42 #define SMI_LARB_OSTDL_PORT 0x200 43 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 44 45 /* Below are about mmu enable registers, they are different in SoCs */ 46 /* gen1: mt2701 */ 47 #define REG_SMI_SECUR_CON_BASE 0x5c0 48 49 /* every register control 8 port, register offset 0x4 */ 50 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 51 #define REG_SMI_SECUR_CON_ADDR(id) \ 52 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 53 54 /* 55 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 56 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 57 * or non-security. 58 */ 59 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 60 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 61 /* mt2701 domain should be set to 3 */ 62 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 63 64 /* gen2: */ 65 /* mt8167 */ 66 #define MT8167_SMI_LARB_MMU_EN 0xfc0 67 68 /* mt8173 */ 69 #define MT8173_SMI_LARB_MMU_EN 0xf00 70 71 /* general */ 72 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 73 #define F_MMU_EN BIT(0) 74 #define BANK_SEL(id) ({ \ 75 u32 _id = (id) & 0x3; \ 76 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 77 }) 78 79 #define SMI_COMMON_INIT_REGS_NR 6 80 #define SMI_LARB_PORT_NR_MAX 32 81 82 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 83 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 84 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 85 86 struct mtk_smi_reg_pair { 87 unsigned int offset; 88 u32 value; 89 }; 90 91 enum mtk_smi_type { 92 MTK_SMI_GEN1, 93 MTK_SMI_GEN2, /* gen2 smi common */ 94 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 95 }; 96 97 #define MTK_SMI_CLK_NR_MAX 4 98 99 /* larbs: Require apb/smi clocks while gals is optional. */ 100 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 101 #define MTK_SMI_LARB_REQ_CLK_NR 2 102 #define MTK_SMI_LARB_OPT_CLK_NR 1 103 104 /* 105 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 106 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 107 */ 108 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 109 #define MTK_SMI_COM_REQ_CLK_NR 2 110 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 111 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 112 113 struct mtk_smi_common_plat { 114 enum mtk_smi_type type; 115 bool has_gals; 116 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 117 118 const struct mtk_smi_reg_pair *init; 119 }; 120 121 struct mtk_smi_larb_gen { 122 int port_in_larb[MTK_LARB_NR_MAX + 1]; 123 void (*config_port)(struct device *dev); 124 unsigned int larb_direct_to_common_mask; 125 unsigned int flags_general; 126 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 127 }; 128 129 struct mtk_smi { 130 struct device *dev; 131 unsigned int clk_num; 132 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 133 struct clk *clk_async; /*only needed by mt2701*/ 134 union { 135 void __iomem *smi_ao_base; /* only for gen1 */ 136 void __iomem *base; /* only for gen2 */ 137 }; 138 struct device *smi_common_dev; /* for sub common */ 139 const struct mtk_smi_common_plat *plat; 140 }; 141 142 struct mtk_smi_larb { /* larb: local arbiter */ 143 struct mtk_smi smi; 144 void __iomem *base; 145 struct device *smi_common_dev; /* common or sub-common dev */ 146 const struct mtk_smi_larb_gen *larb_gen; 147 int larbid; 148 u32 *mmu; 149 unsigned char *bank; 150 }; 151 152 static int 153 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 154 { 155 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 156 struct mtk_smi_larb_iommu *larb_mmu = data; 157 unsigned int i; 158 159 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 160 if (dev == larb_mmu[i].dev) { 161 larb->larbid = i; 162 larb->mmu = &larb_mmu[i].mmu; 163 larb->bank = larb_mmu[i].bank; 164 return 0; 165 } 166 } 167 return -ENODEV; 168 } 169 170 static void 171 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 172 { 173 /* Do nothing as the iommu is always enabled. */ 174 } 175 176 static const struct component_ops mtk_smi_larb_component_ops = { 177 .bind = mtk_smi_larb_bind, 178 .unbind = mtk_smi_larb_unbind, 179 }; 180 181 static void mtk_smi_larb_config_port_gen1(struct device *dev) 182 { 183 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 184 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 185 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 186 int i, m4u_port_id, larb_port_num; 187 u32 sec_con_val, reg_val; 188 189 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 190 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 191 - larb_gen->port_in_larb[larb->larbid]; 192 193 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 194 if (*larb->mmu & BIT(i)) { 195 /* bit[port + 3] controls the virtual or physical */ 196 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 197 } else { 198 /* do not need to enable m4u for this port */ 199 continue; 200 } 201 reg_val = readl(common->smi_ao_base 202 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 203 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 204 reg_val |= sec_con_val; 205 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 206 writel(reg_val, 207 common->smi_ao_base 208 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 209 } 210 } 211 212 static void mtk_smi_larb_config_port_mt8167(struct device *dev) 213 { 214 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 215 216 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 217 } 218 219 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 220 { 221 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 222 223 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 224 } 225 226 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 227 { 228 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 229 u32 reg, flags_general = larb->larb_gen->flags_general; 230 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 231 int i; 232 233 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 234 return; 235 236 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 237 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 238 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 239 reg |= SMI_LARB_THRT_RD_NU_LMT; 240 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 241 } 242 243 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 244 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 245 246 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 247 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 248 249 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 250 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 251 reg |= F_MMU_EN; 252 reg |= BANK_SEL(larb->bank[i]); 253 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 254 } 255 } 256 257 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 258 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 259 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 260 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 261 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 262 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 263 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 264 [6] = {0x06, 0x01, 0x06, 0x0a,}, 265 [7] = {0x0c, 0x0c, 0x12,}, 266 [8] = {0x0c, 0x0c, 0x12,}, 267 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 268 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 269 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 270 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 271 0x0d, 0x06, 0x10, 0x10,}, 272 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 273 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 274 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 275 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 276 0x01, 0x02, 0x02, 0x08, 0x02,}, 277 [15] = {}, 278 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 279 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 280 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 281 [18] = {0x12, 0x06, 0x12, 0x06,}, 282 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 283 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 284 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 285 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 286 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 287 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 288 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 289 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 290 [23] = {0x18, 0x01,}, 291 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 292 0x01, 0x01,}, 293 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 294 0x02, 0x01,}, 295 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 296 0x02, 0x01,}, 297 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 298 0x02, 0x01,}, 299 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 300 }; 301 302 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 303 .port_in_larb = { 304 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 305 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 306 }, 307 .config_port = mtk_smi_larb_config_port_gen1, 308 }; 309 310 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 311 .config_port = mtk_smi_larb_config_port_gen2_general, 312 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 313 }; 314 315 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 316 .config_port = mtk_smi_larb_config_port_gen2_general, 317 .larb_direct_to_common_mask = 318 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 319 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 320 }; 321 322 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 323 /* mt8167 do not need the port in larb */ 324 .config_port = mtk_smi_larb_config_port_mt8167, 325 }; 326 327 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 328 /* mt8173 do not need the port in larb */ 329 .config_port = mtk_smi_larb_config_port_mt8173, 330 }; 331 332 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 333 .config_port = mtk_smi_larb_config_port_gen2_general, 334 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 335 /* IPU0 | IPU1 | CCU */ 336 }; 337 338 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 339 .config_port = mtk_smi_larb_config_port_gen2_general, 340 }; 341 342 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 343 .config_port = mtk_smi_larb_config_port_gen2_general, 344 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, 345 .ostd = mtk_smi_larb_mt8195_ostd, 346 }; 347 348 static const struct of_device_id mtk_smi_larb_of_ids[] = { 349 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 350 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 351 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 352 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 353 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 354 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 355 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 356 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 357 {} 358 }; 359 360 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 361 { 362 struct platform_device *smi_com_pdev; 363 struct device_node *smi_com_node; 364 struct device *smi_com_dev; 365 struct device_link *link; 366 367 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 368 if (!smi_com_node) 369 return -EINVAL; 370 371 smi_com_pdev = of_find_device_by_node(smi_com_node); 372 of_node_put(smi_com_node); 373 if (smi_com_pdev) { 374 /* smi common is the supplier, Make sure it is ready before */ 375 if (!platform_get_drvdata(smi_com_pdev)) 376 return -EPROBE_DEFER; 377 smi_com_dev = &smi_com_pdev->dev; 378 link = device_link_add(dev, smi_com_dev, 379 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 380 if (!link) { 381 dev_err(dev, "Unable to link smi-common dev\n"); 382 return -ENODEV; 383 } 384 *com_dev = smi_com_dev; 385 } else { 386 dev_err(dev, "Failed to get the smi_common device\n"); 387 return -EINVAL; 388 } 389 return 0; 390 } 391 392 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 393 const char * const clks[], 394 unsigned int clk_nr_required, 395 unsigned int clk_nr_optional) 396 { 397 int i, ret; 398 399 for (i = 0; i < clk_nr_required; i++) 400 smi->clks[i].id = clks[i]; 401 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 402 if (ret) 403 return ret; 404 405 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 406 smi->clks[i].id = clks[i]; 407 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 408 smi->clks + clk_nr_required); 409 smi->clk_num = clk_nr_required + clk_nr_optional; 410 return ret; 411 } 412 413 static int mtk_smi_larb_probe(struct platform_device *pdev) 414 { 415 struct mtk_smi_larb *larb; 416 struct device *dev = &pdev->dev; 417 int ret; 418 419 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 420 if (!larb) 421 return -ENOMEM; 422 423 larb->larb_gen = of_device_get_match_data(dev); 424 larb->base = devm_platform_ioremap_resource(pdev, 0); 425 if (IS_ERR(larb->base)) 426 return PTR_ERR(larb->base); 427 428 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 429 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 430 if (ret) 431 return ret; 432 433 larb->smi.dev = dev; 434 435 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 436 if (ret < 0) 437 return ret; 438 439 pm_runtime_enable(dev); 440 platform_set_drvdata(pdev, larb); 441 ret = component_add(dev, &mtk_smi_larb_component_ops); 442 if (ret) 443 goto err_pm_disable; 444 return 0; 445 446 err_pm_disable: 447 pm_runtime_disable(dev); 448 device_link_remove(dev, larb->smi_common_dev); 449 return ret; 450 } 451 452 static int mtk_smi_larb_remove(struct platform_device *pdev) 453 { 454 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 455 456 device_link_remove(&pdev->dev, larb->smi_common_dev); 457 pm_runtime_disable(&pdev->dev); 458 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 459 return 0; 460 } 461 462 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 463 { 464 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 465 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 466 int ret; 467 468 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 469 if (ret < 0) 470 return ret; 471 472 /* Configure the basic setting for this larb */ 473 larb_gen->config_port(dev); 474 475 return 0; 476 } 477 478 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 479 { 480 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 481 482 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 483 return 0; 484 } 485 486 static const struct dev_pm_ops smi_larb_pm_ops = { 487 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 488 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 489 pm_runtime_force_resume) 490 }; 491 492 static struct platform_driver mtk_smi_larb_driver = { 493 .probe = mtk_smi_larb_probe, 494 .remove = mtk_smi_larb_remove, 495 .driver = { 496 .name = "mtk-smi-larb", 497 .of_match_table = mtk_smi_larb_of_ids, 498 .pm = &smi_larb_pm_ops, 499 } 500 }; 501 502 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 503 {SMI_L1LEN, 0xb}, 504 {SMI_M4U_TH, 0xe100e10}, 505 {SMI_FIFO_TH1, 0x506090a}, 506 {SMI_FIFO_TH2, 0x506090a}, 507 {SMI_DCM, 0x4f1}, 508 {SMI_DUMMY, 0x1}, 509 }; 510 511 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 512 .type = MTK_SMI_GEN1, 513 }; 514 515 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 516 .type = MTK_SMI_GEN2, 517 }; 518 519 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 520 .type = MTK_SMI_GEN2, 521 .has_gals = true, 522 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 523 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 524 }; 525 526 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 527 .type = MTK_SMI_GEN2, 528 .has_gals = true, 529 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 530 F_MMU1_LARB(7), 531 }; 532 533 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 534 .type = MTK_SMI_GEN2, 535 .has_gals = true, 536 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 537 F_MMU1_LARB(6), 538 }; 539 540 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 541 .type = MTK_SMI_GEN2, 542 .has_gals = true, 543 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 544 F_MMU1_LARB(7), 545 .init = mtk_smi_common_mt8195_init, 546 }; 547 548 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 549 .type = MTK_SMI_GEN2, 550 .has_gals = true, 551 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 552 .init = mtk_smi_common_mt8195_init, 553 }; 554 555 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 556 .type = MTK_SMI_GEN2_SUB_COMM, 557 .has_gals = true, 558 }; 559 560 static const struct of_device_id mtk_smi_common_of_ids[] = { 561 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 562 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 563 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 564 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 565 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 566 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 567 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 568 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 569 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 570 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 571 {} 572 }; 573 574 static int mtk_smi_common_probe(struct platform_device *pdev) 575 { 576 struct device *dev = &pdev->dev; 577 struct mtk_smi *common; 578 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 579 580 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 581 if (!common) 582 return -ENOMEM; 583 common->dev = dev; 584 common->plat = of_device_get_match_data(dev); 585 586 if (common->plat->has_gals) { 587 if (common->plat->type == MTK_SMI_GEN2) 588 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 589 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 590 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 591 } 592 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 593 if (ret) 594 return ret; 595 596 /* 597 * for mtk smi gen 1, we need to get the ao(always on) base to config 598 * m4u port, and we need to enable the aync clock for transform the smi 599 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 600 * base. 601 */ 602 if (common->plat->type == MTK_SMI_GEN1) { 603 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 604 if (IS_ERR(common->smi_ao_base)) 605 return PTR_ERR(common->smi_ao_base); 606 607 common->clk_async = devm_clk_get(dev, "async"); 608 if (IS_ERR(common->clk_async)) 609 return PTR_ERR(common->clk_async); 610 611 ret = clk_prepare_enable(common->clk_async); 612 if (ret) 613 return ret; 614 } else { 615 common->base = devm_platform_ioremap_resource(pdev, 0); 616 if (IS_ERR(common->base)) 617 return PTR_ERR(common->base); 618 } 619 620 /* link its smi-common if this is smi-sub-common */ 621 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 622 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 623 if (ret < 0) 624 return ret; 625 } 626 627 pm_runtime_enable(dev); 628 platform_set_drvdata(pdev, common); 629 return 0; 630 } 631 632 static int mtk_smi_common_remove(struct platform_device *pdev) 633 { 634 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 635 636 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 637 device_link_remove(&pdev->dev, common->smi_common_dev); 638 pm_runtime_disable(&pdev->dev); 639 return 0; 640 } 641 642 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 643 { 644 struct mtk_smi *common = dev_get_drvdata(dev); 645 const struct mtk_smi_reg_pair *init = common->plat->init; 646 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 647 int ret, i; 648 649 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 650 if (ret) 651 return ret; 652 653 if (common->plat->type != MTK_SMI_GEN2) 654 return 0; 655 656 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 657 writel_relaxed(init[i].value, common->base + init[i].offset); 658 659 writel(bus_sel, common->base + SMI_BUS_SEL); 660 return 0; 661 } 662 663 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 664 { 665 struct mtk_smi *common = dev_get_drvdata(dev); 666 667 clk_bulk_disable_unprepare(common->clk_num, common->clks); 668 return 0; 669 } 670 671 static const struct dev_pm_ops smi_common_pm_ops = { 672 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 673 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 674 pm_runtime_force_resume) 675 }; 676 677 static struct platform_driver mtk_smi_common_driver = { 678 .probe = mtk_smi_common_probe, 679 .remove = mtk_smi_common_remove, 680 .driver = { 681 .name = "mtk-smi-common", 682 .of_match_table = mtk_smi_common_of_ids, 683 .pm = &smi_common_pm_ops, 684 } 685 }; 686 687 static struct platform_driver * const smidrivers[] = { 688 &mtk_smi_common_driver, 689 &mtk_smi_larb_driver, 690 }; 691 692 static int __init mtk_smi_init(void) 693 { 694 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 695 } 696 module_init(mtk_smi_init); 697 698 static void __exit mtk_smi_exit(void) 699 { 700 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 701 } 702 module_exit(mtk_smi_exit); 703 704 MODULE_DESCRIPTION("MediaTek SMI driver"); 705 MODULE_LICENSE("GPL v2"); 706