1*a10e763bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
20c0d06caSMauro Carvalho Chehab /*
30c0d06caSMauro Carvalho Chehab * Hauppauge HD PVR USB driver
40c0d06caSMauro Carvalho Chehab *
50c0d06caSMauro Carvalho Chehab * Copyright (C) 2008 Janne Grunau (j@jannau.net)
60c0d06caSMauro Carvalho Chehab */
70c0d06caSMauro Carvalho Chehab
80c0d06caSMauro Carvalho Chehab #include <linux/usb.h>
90c0d06caSMauro Carvalho Chehab #include <linux/i2c.h>
100c0d06caSMauro Carvalho Chehab #include <linux/mutex.h>
110c0d06caSMauro Carvalho Chehab #include <linux/workqueue.h>
120c0d06caSMauro Carvalho Chehab #include <linux/videodev2.h>
130c0d06caSMauro Carvalho Chehab
140c0d06caSMauro Carvalho Chehab #include <media/v4l2-device.h>
1599c77aa4SHans Verkuil #include <media/v4l2-ctrls.h>
16b5dcee22SMauro Carvalho Chehab #include <media/i2c/ir-kbd-i2c.h>
170c0d06caSMauro Carvalho Chehab
180c0d06caSMauro Carvalho Chehab #define HDPVR_MAX 8
190c0d06caSMauro Carvalho Chehab #define HDPVR_I2C_MAX_SIZE 128
200c0d06caSMauro Carvalho Chehab
210c0d06caSMauro Carvalho Chehab /* Define these values to match your devices */
220c0d06caSMauro Carvalho Chehab #define HD_PVR_VENDOR_ID 0x2040
230c0d06caSMauro Carvalho Chehab #define HD_PVR_PRODUCT_ID 0x4900
240c0d06caSMauro Carvalho Chehab #define HD_PVR_PRODUCT_ID1 0x4901
250c0d06caSMauro Carvalho Chehab #define HD_PVR_PRODUCT_ID2 0x4902
260c0d06caSMauro Carvalho Chehab #define HD_PVR_PRODUCT_ID4 0x4903
270c0d06caSMauro Carvalho Chehab #define HD_PVR_PRODUCT_ID3 0x4982
280c0d06caSMauro Carvalho Chehab
290c0d06caSMauro Carvalho Chehab #define UNSET (-1U)
300c0d06caSMauro Carvalho Chehab
310c0d06caSMauro Carvalho Chehab #define NUM_BUFFERS 64
320c0d06caSMauro Carvalho Chehab
330c0d06caSMauro Carvalho Chehab #define HDPVR_FIRMWARE_VERSION 0x08
340c0d06caSMauro Carvalho Chehab #define HDPVR_FIRMWARE_VERSION_AC3 0x0d
350c0d06caSMauro Carvalho Chehab #define HDPVR_FIRMWARE_VERSION_0X12 0x12
360c0d06caSMauro Carvalho Chehab #define HDPVR_FIRMWARE_VERSION_0X15 0x15
37c7a2c84aSHans Verkuil #define HDPVR_FIRMWARE_VERSION_0X1E 0x1e
380c0d06caSMauro Carvalho Chehab
390c0d06caSMauro Carvalho Chehab /* #define HDPVR_DEBUG */
400c0d06caSMauro Carvalho Chehab
410c0d06caSMauro Carvalho Chehab extern int hdpvr_debug;
420c0d06caSMauro Carvalho Chehab
430c0d06caSMauro Carvalho Chehab #define MSG_INFO 1
440c0d06caSMauro Carvalho Chehab #define MSG_BUFFER 2
450c0d06caSMauro Carvalho Chehab
460c0d06caSMauro Carvalho Chehab struct hdpvr_options {
470c0d06caSMauro Carvalho Chehab u8 video_std;
480c0d06caSMauro Carvalho Chehab u8 video_input;
490c0d06caSMauro Carvalho Chehab u8 audio_input;
500c0d06caSMauro Carvalho Chehab u8 bitrate; /* in 100kbps */
510c0d06caSMauro Carvalho Chehab u8 peak_bitrate; /* in 100kbps */
520c0d06caSMauro Carvalho Chehab u8 bitrate_mode;
530c0d06caSMauro Carvalho Chehab u8 gop_mode;
540c0d06caSMauro Carvalho Chehab enum v4l2_mpeg_audio_encoding audio_codec;
550c0d06caSMauro Carvalho Chehab u8 brightness;
560c0d06caSMauro Carvalho Chehab u8 contrast;
570c0d06caSMauro Carvalho Chehab u8 hue;
580c0d06caSMauro Carvalho Chehab u8 saturation;
590c0d06caSMauro Carvalho Chehab u8 sharpness;
600c0d06caSMauro Carvalho Chehab };
610c0d06caSMauro Carvalho Chehab
620c0d06caSMauro Carvalho Chehab /* Structure to hold all of our device specific stuff */
630c0d06caSMauro Carvalho Chehab struct hdpvr_device {
640c0d06caSMauro Carvalho Chehab /* the v4l device for this device */
654b30409bSHans Verkuil struct video_device video_dev;
6699c77aa4SHans Verkuil /* the control handler for this device */
6799c77aa4SHans Verkuil struct v4l2_ctrl_handler hdl;
680c0d06caSMauro Carvalho Chehab /* the usb device for this device */
690c0d06caSMauro Carvalho Chehab struct usb_device *udev;
700c0d06caSMauro Carvalho Chehab /* v4l2-device unused */
710c0d06caSMauro Carvalho Chehab struct v4l2_device v4l2_dev;
7299c77aa4SHans Verkuil struct { /* video mode/bitrate control cluster */
7399c77aa4SHans Verkuil struct v4l2_ctrl *video_mode;
7499c77aa4SHans Verkuil struct v4l2_ctrl *video_bitrate;
7599c77aa4SHans Verkuil struct v4l2_ctrl *video_bitrate_peak;
7699c77aa4SHans Verkuil };
778f69da95SHans Verkuil /* v4l2 format */
788f69da95SHans Verkuil uint width, height;
790c0d06caSMauro Carvalho Chehab
800c0d06caSMauro Carvalho Chehab /* the max packet size of the bulk endpoint */
810c0d06caSMauro Carvalho Chehab size_t bulk_in_size;
820c0d06caSMauro Carvalho Chehab /* the address of the bulk in endpoint */
830c0d06caSMauro Carvalho Chehab __u8 bulk_in_endpointAddr;
840c0d06caSMauro Carvalho Chehab
850c0d06caSMauro Carvalho Chehab /* holds the current device status */
860c0d06caSMauro Carvalho Chehab __u8 status;
870c0d06caSMauro Carvalho Chehab
888f69da95SHans Verkuil /* holds the current set options */
890c0d06caSMauro Carvalho Chehab struct hdpvr_options options;
908f69da95SHans Verkuil v4l2_std_id cur_std;
913315c59aSHans Verkuil struct v4l2_dv_timings cur_dv_timings;
920c0d06caSMauro Carvalho Chehab
930c0d06caSMauro Carvalho Chehab uint flags;
940c0d06caSMauro Carvalho Chehab
950c0d06caSMauro Carvalho Chehab /* synchronize I/O */
960c0d06caSMauro Carvalho Chehab struct mutex io_mutex;
970c0d06caSMauro Carvalho Chehab /* available buffers */
980c0d06caSMauro Carvalho Chehab struct list_head free_buff_list;
990c0d06caSMauro Carvalho Chehab /* in progress buffers */
1000c0d06caSMauro Carvalho Chehab struct list_head rec_buff_list;
1010c0d06caSMauro Carvalho Chehab /* waitqueue for buffers */
1020c0d06caSMauro Carvalho Chehab wait_queue_head_t wait_buffer;
1030c0d06caSMauro Carvalho Chehab /* waitqueue for data */
1040c0d06caSMauro Carvalho Chehab wait_queue_head_t wait_data;
1050c0d06caSMauro Carvalho Chehab /**/
1060c0d06caSMauro Carvalho Chehab struct work_struct worker;
107ede197aaSHans Verkuil /* current stream owner */
108ede197aaSHans Verkuil struct v4l2_fh *owner;
1090c0d06caSMauro Carvalho Chehab
1100c0d06caSMauro Carvalho Chehab /* I2C adapter */
1110c0d06caSMauro Carvalho Chehab struct i2c_adapter i2c_adapter;
1120c0d06caSMauro Carvalho Chehab /* I2C lock */
1130c0d06caSMauro Carvalho Chehab struct mutex i2c_mutex;
1140c0d06caSMauro Carvalho Chehab /* I2C message buffer space */
1150c0d06caSMauro Carvalho Chehab char i2c_buf[HDPVR_I2C_MAX_SIZE];
1160c0d06caSMauro Carvalho Chehab
1170c0d06caSMauro Carvalho Chehab /* For passing data to ir-kbd-i2c */
1180c0d06caSMauro Carvalho Chehab struct IR_i2c_init_data ir_i2c_init_data;
1190c0d06caSMauro Carvalho Chehab
1200c0d06caSMauro Carvalho Chehab /* usb control transfer buffer and lock */
1210c0d06caSMauro Carvalho Chehab struct mutex usbc_mutex;
1220c0d06caSMauro Carvalho Chehab u8 *usbc_buf;
1230c0d06caSMauro Carvalho Chehab u8 fw_ver;
1240c0d06caSMauro Carvalho Chehab };
1250c0d06caSMauro Carvalho Chehab
to_hdpvr_dev(struct v4l2_device * v4l2_dev)1260c0d06caSMauro Carvalho Chehab static inline struct hdpvr_device *to_hdpvr_dev(struct v4l2_device *v4l2_dev)
1270c0d06caSMauro Carvalho Chehab {
1280c0d06caSMauro Carvalho Chehab return container_of(v4l2_dev, struct hdpvr_device, v4l2_dev);
1290c0d06caSMauro Carvalho Chehab }
1300c0d06caSMauro Carvalho Chehab
1310c0d06caSMauro Carvalho Chehab
1320c0d06caSMauro Carvalho Chehab /* buffer one bulk urb of data */
1330c0d06caSMauro Carvalho Chehab struct hdpvr_buffer {
1340c0d06caSMauro Carvalho Chehab struct list_head buff_list;
1350c0d06caSMauro Carvalho Chehab
1360c0d06caSMauro Carvalho Chehab struct urb *urb;
1370c0d06caSMauro Carvalho Chehab
1380c0d06caSMauro Carvalho Chehab struct hdpvr_device *dev;
1390c0d06caSMauro Carvalho Chehab
1400c0d06caSMauro Carvalho Chehab uint pos;
1410c0d06caSMauro Carvalho Chehab
1420c0d06caSMauro Carvalho Chehab __u8 status;
1430c0d06caSMauro Carvalho Chehab };
1440c0d06caSMauro Carvalho Chehab
1450c0d06caSMauro Carvalho Chehab /* */
1460c0d06caSMauro Carvalho Chehab
1470c0d06caSMauro Carvalho Chehab struct hdpvr_video_info {
1480c0d06caSMauro Carvalho Chehab u16 width;
1490c0d06caSMauro Carvalho Chehab u16 height;
1500c0d06caSMauro Carvalho Chehab u8 fps;
1515f454d82SHans Verkuil bool valid;
1520c0d06caSMauro Carvalho Chehab };
1530c0d06caSMauro Carvalho Chehab
1540c0d06caSMauro Carvalho Chehab enum {
1550c0d06caSMauro Carvalho Chehab STATUS_UNINITIALIZED = 0,
1560c0d06caSMauro Carvalho Chehab STATUS_IDLE,
1570c0d06caSMauro Carvalho Chehab STATUS_STARTING,
1580c0d06caSMauro Carvalho Chehab STATUS_SHUTTING_DOWN,
1590c0d06caSMauro Carvalho Chehab STATUS_STREAMING,
1600c0d06caSMauro Carvalho Chehab STATUS_ERROR,
1610c0d06caSMauro Carvalho Chehab STATUS_DISCONNECTED,
1620c0d06caSMauro Carvalho Chehab };
1630c0d06caSMauro Carvalho Chehab
1640c0d06caSMauro Carvalho Chehab enum {
1650c0d06caSMauro Carvalho Chehab HDPVR_FLAG_AC3_CAP = 1,
1660c0d06caSMauro Carvalho Chehab };
1670c0d06caSMauro Carvalho Chehab
1680c0d06caSMauro Carvalho Chehab enum {
1690c0d06caSMauro Carvalho Chehab BUFSTAT_UNINITIALIZED = 0,
1700c0d06caSMauro Carvalho Chehab BUFSTAT_AVAILABLE,
1710c0d06caSMauro Carvalho Chehab BUFSTAT_INPROGRESS,
1720c0d06caSMauro Carvalho Chehab BUFSTAT_READY,
1730c0d06caSMauro Carvalho Chehab };
1740c0d06caSMauro Carvalho Chehab
1750c0d06caSMauro Carvalho Chehab #define CTRL_START_STREAMING_VALUE 0x0700
1760c0d06caSMauro Carvalho Chehab #define CTRL_STOP_STREAMING_VALUE 0x0800
1770c0d06caSMauro Carvalho Chehab #define CTRL_BITRATE_VALUE 0x1000
1780c0d06caSMauro Carvalho Chehab #define CTRL_BITRATE_MODE_VALUE 0x1200
1790c0d06caSMauro Carvalho Chehab #define CTRL_GOP_MODE_VALUE 0x1300
1800c0d06caSMauro Carvalho Chehab #define CTRL_VIDEO_INPUT_VALUE 0x1500
1810c0d06caSMauro Carvalho Chehab #define CTRL_VIDEO_STD_TYPE 0x1700
1820c0d06caSMauro Carvalho Chehab #define CTRL_AUDIO_INPUT_VALUE 0x2500
1830c0d06caSMauro Carvalho Chehab #define CTRL_BRIGHTNESS 0x2900
1840c0d06caSMauro Carvalho Chehab #define CTRL_CONTRAST 0x2a00
1850c0d06caSMauro Carvalho Chehab #define CTRL_HUE 0x2b00
1860c0d06caSMauro Carvalho Chehab #define CTRL_SATURATION 0x2c00
1870c0d06caSMauro Carvalho Chehab #define CTRL_SHARPNESS 0x2d00
1880c0d06caSMauro Carvalho Chehab #define CTRL_LOW_PASS_FILTER_VALUE 0x3100
1890c0d06caSMauro Carvalho Chehab
1900c0d06caSMauro Carvalho Chehab #define CTRL_DEFAULT_INDEX 0x0003
1910c0d06caSMauro Carvalho Chehab
1920c0d06caSMauro Carvalho Chehab
1930c0d06caSMauro Carvalho Chehab /* :0 s 38 01 1000 0003 0004 4 = 0a00ca00
1940c0d06caSMauro Carvalho Chehab * BITRATE SETTING
1950c0d06caSMauro Carvalho Chehab * 1st and 2nd byte (little endian): average bitrate in 100 000 bit/s
1960c0d06caSMauro Carvalho Chehab * min: 1 mbit/s, max: 13.5 mbit/s
1970c0d06caSMauro Carvalho Chehab * 3rd and 4th byte (little endian): peak bitrate in 100 000 bit/s
1980c0d06caSMauro Carvalho Chehab * min: average + 100kbit/s,
1990c0d06caSMauro Carvalho Chehab * max: 20.2 mbit/s
2000c0d06caSMauro Carvalho Chehab */
2010c0d06caSMauro Carvalho Chehab
2020c0d06caSMauro Carvalho Chehab /* :0 s 38 01 1200 0003 0001 1 = 02
2030c0d06caSMauro Carvalho Chehab * BIT RATE MODE
2040c0d06caSMauro Carvalho Chehab * constant = 1, variable (peak) = 2, variable (average) = 3
2050c0d06caSMauro Carvalho Chehab */
2060c0d06caSMauro Carvalho Chehab
2070c0d06caSMauro Carvalho Chehab /* :0 s 38 01 1300 0003 0001 1 = 03
2080c0d06caSMauro Carvalho Chehab * GOP MODE (2 bit)
2090c0d06caSMauro Carvalho Chehab * low bit 0/1: advanced/simple GOP
2100c0d06caSMauro Carvalho Chehab * high bit 0/1: IDR(4/32/128) / no IDR (4/32/0)
2110c0d06caSMauro Carvalho Chehab */
2120c0d06caSMauro Carvalho Chehab
2130c0d06caSMauro Carvalho Chehab /* :0 s 38 01 1700 0003 0001 1 = 00
2143e4d8f48SMauro Carvalho Chehab * VIDEO STANDARD or FREQUENCY 0 = 60hz, 1 = 50hz
2150c0d06caSMauro Carvalho Chehab */
2160c0d06caSMauro Carvalho Chehab
2170c0d06caSMauro Carvalho Chehab /* :0 s 38 01 3100 0003 0004 4 = 03030000
2180c0d06caSMauro Carvalho Chehab * FILTER CONTROL
2190c0d06caSMauro Carvalho Chehab * 1st byte luma low pass filter strength,
2200c0d06caSMauro Carvalho Chehab * 2nd byte chroma low pass filter strength,
2210c0d06caSMauro Carvalho Chehab * 3rd byte MF enable chroma, min=0, max=1
2220c0d06caSMauro Carvalho Chehab * 4th byte n
2230c0d06caSMauro Carvalho Chehab */
2240c0d06caSMauro Carvalho Chehab
2250c0d06caSMauro Carvalho Chehab
2260c0d06caSMauro Carvalho Chehab /* :0 s 38 b9 0001 0000 0000 0 */
2270c0d06caSMauro Carvalho Chehab
2280c0d06caSMauro Carvalho Chehab
2290c0d06caSMauro Carvalho Chehab
2300c0d06caSMauro Carvalho Chehab /* :0 s 38 d3 0000 0000 0001 1 = 00 */
2310c0d06caSMauro Carvalho Chehab /* ret = usb_control_msg(dev->udev, */
2320c0d06caSMauro Carvalho Chehab /* usb_sndctrlpipe(dev->udev, 0), */
2330c0d06caSMauro Carvalho Chehab /* 0xd3, 0x38, */
2340c0d06caSMauro Carvalho Chehab /* 0, 0, */
2350c0d06caSMauro Carvalho Chehab /* "\0", 1, */
2360c0d06caSMauro Carvalho Chehab /* 1000); */
2370c0d06caSMauro Carvalho Chehab
2380c0d06caSMauro Carvalho Chehab /* info("control request returned %d", ret); */
2390c0d06caSMauro Carvalho Chehab /* msleep(5000); */
2400c0d06caSMauro Carvalho Chehab
2410c0d06caSMauro Carvalho Chehab
2420c0d06caSMauro Carvalho Chehab /* :0 s b8 81 1400 0003 0005 5 <
2430c0d06caSMauro Carvalho Chehab * :0 0 5 = d0024002 19
2440c0d06caSMauro Carvalho Chehab * QUERY FRAME SIZE AND RATE
2450c0d06caSMauro Carvalho Chehab * 1st and 2nd byte (little endian): horizontal resolution
2460c0d06caSMauro Carvalho Chehab * 3rd and 4th byte (little endian): vertical resolution
2470c0d06caSMauro Carvalho Chehab * 5th byte: frame rate
2480c0d06caSMauro Carvalho Chehab */
2490c0d06caSMauro Carvalho Chehab
2500c0d06caSMauro Carvalho Chehab /* :0 s b8 81 1800 0003 0003 3 <
2510c0d06caSMauro Carvalho Chehab * :0 0 3 = 030104
2520c0d06caSMauro Carvalho Chehab * QUERY SIGNAL AND DETECTED LINES, maybe INPUT
2530c0d06caSMauro Carvalho Chehab */
2540c0d06caSMauro Carvalho Chehab
2550c0d06caSMauro Carvalho Chehab enum hdpvr_video_std {
2560c0d06caSMauro Carvalho Chehab HDPVR_60HZ = 0,
2570c0d06caSMauro Carvalho Chehab HDPVR_50HZ,
2580c0d06caSMauro Carvalho Chehab };
2590c0d06caSMauro Carvalho Chehab
2600c0d06caSMauro Carvalho Chehab enum hdpvr_video_input {
2610c0d06caSMauro Carvalho Chehab HDPVR_COMPONENT = 0,
2620c0d06caSMauro Carvalho Chehab HDPVR_SVIDEO,
2630c0d06caSMauro Carvalho Chehab HDPVR_COMPOSITE,
2640c0d06caSMauro Carvalho Chehab HDPVR_VIDEO_INPUTS
2650c0d06caSMauro Carvalho Chehab };
2660c0d06caSMauro Carvalho Chehab
2670c0d06caSMauro Carvalho Chehab enum hdpvr_audio_inputs {
2680c0d06caSMauro Carvalho Chehab HDPVR_RCA_BACK = 0,
2690c0d06caSMauro Carvalho Chehab HDPVR_RCA_FRONT,
2700c0d06caSMauro Carvalho Chehab HDPVR_SPDIF,
2710c0d06caSMauro Carvalho Chehab HDPVR_AUDIO_INPUTS
2720c0d06caSMauro Carvalho Chehab };
2730c0d06caSMauro Carvalho Chehab
2740c0d06caSMauro Carvalho Chehab enum hdpvr_bitrate_mode {
2750c0d06caSMauro Carvalho Chehab HDPVR_CONSTANT = 1,
2760c0d06caSMauro Carvalho Chehab HDPVR_VARIABLE_PEAK,
2770c0d06caSMauro Carvalho Chehab HDPVR_VARIABLE_AVERAGE,
2780c0d06caSMauro Carvalho Chehab };
2790c0d06caSMauro Carvalho Chehab
2800c0d06caSMauro Carvalho Chehab enum hdpvr_gop_mode {
2810c0d06caSMauro Carvalho Chehab HDPVR_ADVANCED_IDR_GOP = 0,
2820c0d06caSMauro Carvalho Chehab HDPVR_SIMPLE_IDR_GOP,
2830c0d06caSMauro Carvalho Chehab HDPVR_ADVANCED_NOIDR_GOP,
2840c0d06caSMauro Carvalho Chehab HDPVR_SIMPLE_NOIDR_GOP,
2850c0d06caSMauro Carvalho Chehab };
2860c0d06caSMauro Carvalho Chehab
2870c0d06caSMauro Carvalho Chehab void hdpvr_delete(struct hdpvr_device *dev);
2880c0d06caSMauro Carvalho Chehab
2890c0d06caSMauro Carvalho Chehab /*========================================================================*/
2900c0d06caSMauro Carvalho Chehab /* hardware control functions */
2910c0d06caSMauro Carvalho Chehab int hdpvr_set_options(struct hdpvr_device *dev);
2920c0d06caSMauro Carvalho Chehab
2930c0d06caSMauro Carvalho Chehab int hdpvr_set_bitrate(struct hdpvr_device *dev);
2940c0d06caSMauro Carvalho Chehab
2950c0d06caSMauro Carvalho Chehab int hdpvr_set_audio(struct hdpvr_device *dev, u8 input,
2960c0d06caSMauro Carvalho Chehab enum v4l2_mpeg_audio_encoding codec);
2970c0d06caSMauro Carvalho Chehab
2980c0d06caSMauro Carvalho Chehab int hdpvr_config_call(struct hdpvr_device *dev, uint value,
2990c0d06caSMauro Carvalho Chehab unsigned char valbuf);
3000c0d06caSMauro Carvalho Chehab
3014d601c4cSLeonid Kegulskiy int get_video_info(struct hdpvr_device *dev, struct hdpvr_video_info *vid_info);
3020c0d06caSMauro Carvalho Chehab
3030c0d06caSMauro Carvalho Chehab /* :0 s b8 81 1800 0003 0003 3 < */
3040c0d06caSMauro Carvalho Chehab /* :0 0 3 = 0301ff */
3050c0d06caSMauro Carvalho Chehab int get_input_lines_info(struct hdpvr_device *dev);
3060c0d06caSMauro Carvalho Chehab
3070c0d06caSMauro Carvalho Chehab
3080c0d06caSMauro Carvalho Chehab /*========================================================================*/
3090c0d06caSMauro Carvalho Chehab /* v4l2 registration */
3100c0d06caSMauro Carvalho Chehab int hdpvr_register_videodev(struct hdpvr_device *dev, struct device *parent,
3110c0d06caSMauro Carvalho Chehab int devnumber);
3120c0d06caSMauro Carvalho Chehab
3130c0d06caSMauro Carvalho Chehab int hdpvr_cancel_queue(struct hdpvr_device *dev);
3140c0d06caSMauro Carvalho Chehab
3150c0d06caSMauro Carvalho Chehab /*========================================================================*/
3160c0d06caSMauro Carvalho Chehab /* i2c adapter registration */
3170c0d06caSMauro Carvalho Chehab int hdpvr_register_i2c_adapter(struct hdpvr_device *dev);
3180c0d06caSMauro Carvalho Chehab
319ab5222edSSean Young struct i2c_client *hdpvr_register_ir_i2c(struct hdpvr_device *dev);
3200c0d06caSMauro Carvalho Chehab
3210c0d06caSMauro Carvalho Chehab /*========================================================================*/
3220c0d06caSMauro Carvalho Chehab /* buffer management */
3230c0d06caSMauro Carvalho Chehab int hdpvr_free_buffers(struct hdpvr_device *dev);
3240c0d06caSMauro Carvalho Chehab int hdpvr_alloc_buffers(struct hdpvr_device *dev, uint count);
325