1*0c0d06caSMauro Carvalho Chehab /* 2*0c0d06caSMauro Carvalho Chehab cx231xx.h - driver for Conexant Cx23100/101/102 USB video capture devices 3*0c0d06caSMauro Carvalho Chehab 4*0c0d06caSMauro Carvalho Chehab Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 5*0c0d06caSMauro Carvalho Chehab Based on em28xx driver 6*0c0d06caSMauro Carvalho Chehab 7*0c0d06caSMauro Carvalho Chehab This program is free software; you can redistribute it and/or modify 8*0c0d06caSMauro Carvalho Chehab it under the terms of the GNU General Public License as published by 9*0c0d06caSMauro Carvalho Chehab the Free Software Foundation; either version 2 of the License, or 10*0c0d06caSMauro Carvalho Chehab (at your option) any later version. 11*0c0d06caSMauro Carvalho Chehab 12*0c0d06caSMauro Carvalho Chehab This program is distributed in the hope that it will be useful, 13*0c0d06caSMauro Carvalho Chehab but WITHOUT ANY WARRANTY; without even the implied warranty of 14*0c0d06caSMauro Carvalho Chehab MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*0c0d06caSMauro Carvalho Chehab GNU General Public License for more details. 16*0c0d06caSMauro Carvalho Chehab 17*0c0d06caSMauro Carvalho Chehab You should have received a copy of the GNU General Public License 18*0c0d06caSMauro Carvalho Chehab along with this program; if not, write to the Free Software 19*0c0d06caSMauro Carvalho Chehab Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*0c0d06caSMauro Carvalho Chehab */ 21*0c0d06caSMauro Carvalho Chehab 22*0c0d06caSMauro Carvalho Chehab #ifndef _CX231XX_H 23*0c0d06caSMauro Carvalho Chehab #define _CX231XX_H 24*0c0d06caSMauro Carvalho Chehab 25*0c0d06caSMauro Carvalho Chehab #include <linux/videodev2.h> 26*0c0d06caSMauro Carvalho Chehab #include <linux/types.h> 27*0c0d06caSMauro Carvalho Chehab #include <linux/ioctl.h> 28*0c0d06caSMauro Carvalho Chehab #include <linux/i2c.h> 29*0c0d06caSMauro Carvalho Chehab #include <linux/workqueue.h> 30*0c0d06caSMauro Carvalho Chehab #include <linux/mutex.h> 31*0c0d06caSMauro Carvalho Chehab 32*0c0d06caSMauro Carvalho Chehab #include <media/cx2341x.h> 33*0c0d06caSMauro Carvalho Chehab 34*0c0d06caSMauro Carvalho Chehab #include <media/videobuf-vmalloc.h> 35*0c0d06caSMauro Carvalho Chehab #include <media/v4l2-device.h> 36*0c0d06caSMauro Carvalho Chehab #include <media/rc-core.h> 37*0c0d06caSMauro Carvalho Chehab #include <media/ir-kbd-i2c.h> 38*0c0d06caSMauro Carvalho Chehab #include <media/videobuf-dvb.h> 39*0c0d06caSMauro Carvalho Chehab 40*0c0d06caSMauro Carvalho Chehab #include "cx231xx-reg.h" 41*0c0d06caSMauro Carvalho Chehab #include "cx231xx-pcb-cfg.h" 42*0c0d06caSMauro Carvalho Chehab #include "cx231xx-conf-reg.h" 43*0c0d06caSMauro Carvalho Chehab 44*0c0d06caSMauro Carvalho Chehab #define DRIVER_NAME "cx231xx" 45*0c0d06caSMauro Carvalho Chehab #define PWR_SLEEP_INTERVAL 10 46*0c0d06caSMauro Carvalho Chehab 47*0c0d06caSMauro Carvalho Chehab /* I2C addresses for control block in Cx231xx */ 48*0c0d06caSMauro Carvalho Chehab #define AFE_DEVICE_ADDRESS 0x60 49*0c0d06caSMauro Carvalho Chehab #define I2S_BLK_DEVICE_ADDRESS 0x98 50*0c0d06caSMauro Carvalho Chehab #define VID_BLK_I2C_ADDRESS 0x88 51*0c0d06caSMauro Carvalho Chehab #define VERVE_I2C_ADDRESS 0x40 52*0c0d06caSMauro Carvalho Chehab #define DIF_USE_BASEBAND 0xFFFFFFFF 53*0c0d06caSMauro Carvalho Chehab 54*0c0d06caSMauro Carvalho Chehab /* Boards supported by driver */ 55*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_UNKNOWN 0 56*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_CARRAERA 1 57*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_SHELBY 2 58*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_RDE_253S 3 59*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_RDU_253S 4 60*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5 61*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_RDE_250 6 62*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_CNXT_RDU_250 7 63*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_HAUPPAUGE_EXETER 8 64*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9 65*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_PV_PLAYTV_USB_HYBRID 10 66*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_PV_XCAPTURE_USB 11 67*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_KWORLD_UB430_USB_HYBRID 12 68*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_ICONBIT_U100 13 69*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL 14 70*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC 15 71*0c0d06caSMauro Carvalho Chehab 72*0c0d06caSMauro Carvalho Chehab /* Limits minimum and default number of buffers */ 73*0c0d06caSMauro Carvalho Chehab #define CX231XX_MIN_BUF 4 74*0c0d06caSMauro Carvalho Chehab #define CX231XX_DEF_BUF 12 75*0c0d06caSMauro Carvalho Chehab #define CX231XX_DEF_VBI_BUF 6 76*0c0d06caSMauro Carvalho Chehab 77*0c0d06caSMauro Carvalho Chehab #define VBI_LINE_COUNT 17 78*0c0d06caSMauro Carvalho Chehab #define VBI_LINE_LENGTH 1440 79*0c0d06caSMauro Carvalho Chehab 80*0c0d06caSMauro Carvalho Chehab /*Limits the max URB message size */ 81*0c0d06caSMauro Carvalho Chehab #define URB_MAX_CTRL_SIZE 80 82*0c0d06caSMauro Carvalho Chehab 83*0c0d06caSMauro Carvalho Chehab /* Params for validated field */ 84*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_NOT_VALIDATED 1 85*0c0d06caSMauro Carvalho Chehab #define CX231XX_BOARD_VALIDATED 0 86*0c0d06caSMauro Carvalho Chehab 87*0c0d06caSMauro Carvalho Chehab /* maximum number of cx231xx boards */ 88*0c0d06caSMauro Carvalho Chehab #define CX231XX_MAXBOARDS 8 89*0c0d06caSMauro Carvalho Chehab 90*0c0d06caSMauro Carvalho Chehab /* maximum number of frames that can be queued */ 91*0c0d06caSMauro Carvalho Chehab #define CX231XX_NUM_FRAMES 5 92*0c0d06caSMauro Carvalho Chehab 93*0c0d06caSMauro Carvalho Chehab /* number of buffers for isoc transfers */ 94*0c0d06caSMauro Carvalho Chehab #define CX231XX_NUM_BUFS 8 95*0c0d06caSMauro Carvalho Chehab 96*0c0d06caSMauro Carvalho Chehab /* number of packets for each buffer 97*0c0d06caSMauro Carvalho Chehab windows requests only 40 packets .. so we better do the same 98*0c0d06caSMauro Carvalho Chehab this is what I found out for all alternate numbers there! 99*0c0d06caSMauro Carvalho Chehab */ 100*0c0d06caSMauro Carvalho Chehab #define CX231XX_NUM_PACKETS 40 101*0c0d06caSMauro Carvalho Chehab 102*0c0d06caSMauro Carvalho Chehab /* default alternate; 0 means choose the best */ 103*0c0d06caSMauro Carvalho Chehab #define CX231XX_PINOUT 0 104*0c0d06caSMauro Carvalho Chehab 105*0c0d06caSMauro Carvalho Chehab #define CX231XX_INTERLACED_DEFAULT 1 106*0c0d06caSMauro Carvalho Chehab 107*0c0d06caSMauro Carvalho Chehab /* time to wait when stopping the isoc transfer */ 108*0c0d06caSMauro Carvalho Chehab #define CX231XX_URB_TIMEOUT \ 109*0c0d06caSMauro Carvalho Chehab msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS) 110*0c0d06caSMauro Carvalho Chehab 111*0c0d06caSMauro Carvalho Chehab #define CX231xx_NORMS (\ 112*0c0d06caSMauro Carvalho Chehab V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \ 113*0c0d06caSMauro Carvalho Chehab V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ 114*0c0d06caSMauro Carvalho Chehab V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \ 115*0c0d06caSMauro Carvalho Chehab V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK) 116*0c0d06caSMauro Carvalho Chehab 117*0c0d06caSMauro Carvalho Chehab #define SLEEP_S5H1432 30 118*0c0d06caSMauro Carvalho Chehab #define CX23417_OSC_EN 8 119*0c0d06caSMauro Carvalho Chehab #define CX23417_RESET 9 120*0c0d06caSMauro Carvalho Chehab 121*0c0d06caSMauro Carvalho Chehab struct cx23417_fmt { 122*0c0d06caSMauro Carvalho Chehab char *name; 123*0c0d06caSMauro Carvalho Chehab u32 fourcc; /* v4l2 format id */ 124*0c0d06caSMauro Carvalho Chehab int depth; 125*0c0d06caSMauro Carvalho Chehab int flags; 126*0c0d06caSMauro Carvalho Chehab u32 cxformat; 127*0c0d06caSMauro Carvalho Chehab }; 128*0c0d06caSMauro Carvalho Chehab enum cx231xx_mode { 129*0c0d06caSMauro Carvalho Chehab CX231XX_SUSPEND, 130*0c0d06caSMauro Carvalho Chehab CX231XX_ANALOG_MODE, 131*0c0d06caSMauro Carvalho Chehab CX231XX_DIGITAL_MODE, 132*0c0d06caSMauro Carvalho Chehab }; 133*0c0d06caSMauro Carvalho Chehab 134*0c0d06caSMauro Carvalho Chehab enum cx231xx_std_mode { 135*0c0d06caSMauro Carvalho Chehab CX231XX_TV_AIR = 0, 136*0c0d06caSMauro Carvalho Chehab CX231XX_TV_CABLE 137*0c0d06caSMauro Carvalho Chehab }; 138*0c0d06caSMauro Carvalho Chehab 139*0c0d06caSMauro Carvalho Chehab enum cx231xx_stream_state { 140*0c0d06caSMauro Carvalho Chehab STREAM_OFF, 141*0c0d06caSMauro Carvalho Chehab STREAM_INTERRUPT, 142*0c0d06caSMauro Carvalho Chehab STREAM_ON, 143*0c0d06caSMauro Carvalho Chehab }; 144*0c0d06caSMauro Carvalho Chehab 145*0c0d06caSMauro Carvalho Chehab struct cx231xx; 146*0c0d06caSMauro Carvalho Chehab 147*0c0d06caSMauro Carvalho Chehab struct cx231xx_isoc_ctl { 148*0c0d06caSMauro Carvalho Chehab /* max packet size of isoc transaction */ 149*0c0d06caSMauro Carvalho Chehab int max_pkt_size; 150*0c0d06caSMauro Carvalho Chehab 151*0c0d06caSMauro Carvalho Chehab /* number of allocated urbs */ 152*0c0d06caSMauro Carvalho Chehab int num_bufs; 153*0c0d06caSMauro Carvalho Chehab 154*0c0d06caSMauro Carvalho Chehab /* urb for isoc transfers */ 155*0c0d06caSMauro Carvalho Chehab struct urb **urb; 156*0c0d06caSMauro Carvalho Chehab 157*0c0d06caSMauro Carvalho Chehab /* transfer buffers for isoc transfer */ 158*0c0d06caSMauro Carvalho Chehab char **transfer_buffer; 159*0c0d06caSMauro Carvalho Chehab 160*0c0d06caSMauro Carvalho Chehab /* Last buffer command and region */ 161*0c0d06caSMauro Carvalho Chehab u8 cmd; 162*0c0d06caSMauro Carvalho Chehab int pos, size, pktsize; 163*0c0d06caSMauro Carvalho Chehab 164*0c0d06caSMauro Carvalho Chehab /* Last field: ODD or EVEN? */ 165*0c0d06caSMauro Carvalho Chehab int field; 166*0c0d06caSMauro Carvalho Chehab 167*0c0d06caSMauro Carvalho Chehab /* Stores incomplete commands */ 168*0c0d06caSMauro Carvalho Chehab u32 tmp_buf; 169*0c0d06caSMauro Carvalho Chehab int tmp_buf_len; 170*0c0d06caSMauro Carvalho Chehab 171*0c0d06caSMauro Carvalho Chehab /* Stores already requested buffers */ 172*0c0d06caSMauro Carvalho Chehab struct cx231xx_buffer *buf; 173*0c0d06caSMauro Carvalho Chehab 174*0c0d06caSMauro Carvalho Chehab /* Stores the number of received fields */ 175*0c0d06caSMauro Carvalho Chehab int nfields; 176*0c0d06caSMauro Carvalho Chehab 177*0c0d06caSMauro Carvalho Chehab /* isoc urb callback */ 178*0c0d06caSMauro Carvalho Chehab int (*isoc_copy) (struct cx231xx *dev, struct urb *urb); 179*0c0d06caSMauro Carvalho Chehab }; 180*0c0d06caSMauro Carvalho Chehab 181*0c0d06caSMauro Carvalho Chehab struct cx231xx_bulk_ctl { 182*0c0d06caSMauro Carvalho Chehab /* max packet size of bulk transaction */ 183*0c0d06caSMauro Carvalho Chehab int max_pkt_size; 184*0c0d06caSMauro Carvalho Chehab 185*0c0d06caSMauro Carvalho Chehab /* number of allocated urbs */ 186*0c0d06caSMauro Carvalho Chehab int num_bufs; 187*0c0d06caSMauro Carvalho Chehab 188*0c0d06caSMauro Carvalho Chehab /* urb for bulk transfers */ 189*0c0d06caSMauro Carvalho Chehab struct urb **urb; 190*0c0d06caSMauro Carvalho Chehab 191*0c0d06caSMauro Carvalho Chehab /* transfer buffers for bulk transfer */ 192*0c0d06caSMauro Carvalho Chehab char **transfer_buffer; 193*0c0d06caSMauro Carvalho Chehab 194*0c0d06caSMauro Carvalho Chehab /* Last buffer command and region */ 195*0c0d06caSMauro Carvalho Chehab u8 cmd; 196*0c0d06caSMauro Carvalho Chehab int pos, size, pktsize; 197*0c0d06caSMauro Carvalho Chehab 198*0c0d06caSMauro Carvalho Chehab /* Last field: ODD or EVEN? */ 199*0c0d06caSMauro Carvalho Chehab int field; 200*0c0d06caSMauro Carvalho Chehab 201*0c0d06caSMauro Carvalho Chehab /* Stores incomplete commands */ 202*0c0d06caSMauro Carvalho Chehab u32 tmp_buf; 203*0c0d06caSMauro Carvalho Chehab int tmp_buf_len; 204*0c0d06caSMauro Carvalho Chehab 205*0c0d06caSMauro Carvalho Chehab /* Stores already requested buffers */ 206*0c0d06caSMauro Carvalho Chehab struct cx231xx_buffer *buf; 207*0c0d06caSMauro Carvalho Chehab 208*0c0d06caSMauro Carvalho Chehab /* Stores the number of received fields */ 209*0c0d06caSMauro Carvalho Chehab int nfields; 210*0c0d06caSMauro Carvalho Chehab 211*0c0d06caSMauro Carvalho Chehab /* bulk urb callback */ 212*0c0d06caSMauro Carvalho Chehab int (*bulk_copy) (struct cx231xx *dev, struct urb *urb); 213*0c0d06caSMauro Carvalho Chehab }; 214*0c0d06caSMauro Carvalho Chehab 215*0c0d06caSMauro Carvalho Chehab struct cx231xx_fmt { 216*0c0d06caSMauro Carvalho Chehab char *name; 217*0c0d06caSMauro Carvalho Chehab u32 fourcc; /* v4l2 format id */ 218*0c0d06caSMauro Carvalho Chehab int depth; 219*0c0d06caSMauro Carvalho Chehab int reg; 220*0c0d06caSMauro Carvalho Chehab }; 221*0c0d06caSMauro Carvalho Chehab 222*0c0d06caSMauro Carvalho Chehab /* buffer for one video frame */ 223*0c0d06caSMauro Carvalho Chehab struct cx231xx_buffer { 224*0c0d06caSMauro Carvalho Chehab /* common v4l buffer stuff -- must be first */ 225*0c0d06caSMauro Carvalho Chehab struct videobuf_buffer vb; 226*0c0d06caSMauro Carvalho Chehab 227*0c0d06caSMauro Carvalho Chehab struct list_head frame; 228*0c0d06caSMauro Carvalho Chehab int top_field; 229*0c0d06caSMauro Carvalho Chehab int receiving; 230*0c0d06caSMauro Carvalho Chehab }; 231*0c0d06caSMauro Carvalho Chehab 232*0c0d06caSMauro Carvalho Chehab enum ps_package_head { 233*0c0d06caSMauro Carvalho Chehab CX231XX_NEED_ADD_PS_PACKAGE_HEAD = 0, 234*0c0d06caSMauro Carvalho Chehab CX231XX_NONEED_PS_PACKAGE_HEAD 235*0c0d06caSMauro Carvalho Chehab }; 236*0c0d06caSMauro Carvalho Chehab 237*0c0d06caSMauro Carvalho Chehab struct cx231xx_dmaqueue { 238*0c0d06caSMauro Carvalho Chehab struct list_head active; 239*0c0d06caSMauro Carvalho Chehab struct list_head queued; 240*0c0d06caSMauro Carvalho Chehab 241*0c0d06caSMauro Carvalho Chehab wait_queue_head_t wq; 242*0c0d06caSMauro Carvalho Chehab 243*0c0d06caSMauro Carvalho Chehab /* Counters to control buffer fill */ 244*0c0d06caSMauro Carvalho Chehab int pos; 245*0c0d06caSMauro Carvalho Chehab u8 is_partial_line; 246*0c0d06caSMauro Carvalho Chehab u8 partial_buf[8]; 247*0c0d06caSMauro Carvalho Chehab u8 last_sav; 248*0c0d06caSMauro Carvalho Chehab int current_field; 249*0c0d06caSMauro Carvalho Chehab u32 bytes_left_in_line; 250*0c0d06caSMauro Carvalho Chehab u32 lines_completed; 251*0c0d06caSMauro Carvalho Chehab u8 field1_done; 252*0c0d06caSMauro Carvalho Chehab u32 lines_per_field; 253*0c0d06caSMauro Carvalho Chehab 254*0c0d06caSMauro Carvalho Chehab /*Mpeg2 control buffer*/ 255*0c0d06caSMauro Carvalho Chehab u8 *p_left_data; 256*0c0d06caSMauro Carvalho Chehab u32 left_data_count; 257*0c0d06caSMauro Carvalho Chehab u8 mpeg_buffer_done; 258*0c0d06caSMauro Carvalho Chehab u32 mpeg_buffer_completed; 259*0c0d06caSMauro Carvalho Chehab enum ps_package_head add_ps_package_head; 260*0c0d06caSMauro Carvalho Chehab char ps_head[10]; 261*0c0d06caSMauro Carvalho Chehab }; 262*0c0d06caSMauro Carvalho Chehab 263*0c0d06caSMauro Carvalho Chehab /* inputs */ 264*0c0d06caSMauro Carvalho Chehab 265*0c0d06caSMauro Carvalho Chehab #define MAX_CX231XX_INPUT 4 266*0c0d06caSMauro Carvalho Chehab 267*0c0d06caSMauro Carvalho Chehab enum cx231xx_itype { 268*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_COMPOSITE1 = 1, 269*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_SVIDEO, 270*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION, 271*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_CABLE, 272*0c0d06caSMauro Carvalho Chehab CX231XX_RADIO, 273*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_DVB, 274*0c0d06caSMauro Carvalho Chehab CX231XX_VMUX_DEBUG 275*0c0d06caSMauro Carvalho Chehab }; 276*0c0d06caSMauro Carvalho Chehab 277*0c0d06caSMauro Carvalho Chehab enum cx231xx_v_input { 278*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_1_1 = 0x1, 279*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_2_1, 280*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_3_1, 281*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_4_1, 282*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_1_2 = 0x01, 283*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_2_2, 284*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_3_2, 285*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_1_3 = 0x1, 286*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_2_3, 287*0c0d06caSMauro Carvalho Chehab CX231XX_VIN_3_3, 288*0c0d06caSMauro Carvalho Chehab }; 289*0c0d06caSMauro Carvalho Chehab 290*0c0d06caSMauro Carvalho Chehab /* cx231xx has two audio inputs: tuner and line in */ 291*0c0d06caSMauro Carvalho Chehab enum cx231xx_amux { 292*0c0d06caSMauro Carvalho Chehab /* This is the only entry for cx231xx tuner input */ 293*0c0d06caSMauro Carvalho Chehab CX231XX_AMUX_VIDEO, /* cx231xx tuner */ 294*0c0d06caSMauro Carvalho Chehab CX231XX_AMUX_LINE_IN, /* Line In */ 295*0c0d06caSMauro Carvalho Chehab }; 296*0c0d06caSMauro Carvalho Chehab 297*0c0d06caSMauro Carvalho Chehab struct cx231xx_reg_seq { 298*0c0d06caSMauro Carvalho Chehab unsigned char bit; 299*0c0d06caSMauro Carvalho Chehab unsigned char val; 300*0c0d06caSMauro Carvalho Chehab int sleep; 301*0c0d06caSMauro Carvalho Chehab }; 302*0c0d06caSMauro Carvalho Chehab 303*0c0d06caSMauro Carvalho Chehab struct cx231xx_input { 304*0c0d06caSMauro Carvalho Chehab enum cx231xx_itype type; 305*0c0d06caSMauro Carvalho Chehab unsigned int vmux; 306*0c0d06caSMauro Carvalho Chehab enum cx231xx_amux amux; 307*0c0d06caSMauro Carvalho Chehab struct cx231xx_reg_seq *gpio; 308*0c0d06caSMauro Carvalho Chehab }; 309*0c0d06caSMauro Carvalho Chehab 310*0c0d06caSMauro Carvalho Chehab #define INPUT(nr) (&cx231xx_boards[dev->model].input[nr]) 311*0c0d06caSMauro Carvalho Chehab 312*0c0d06caSMauro Carvalho Chehab enum cx231xx_decoder { 313*0c0d06caSMauro Carvalho Chehab CX231XX_NODECODER, 314*0c0d06caSMauro Carvalho Chehab CX231XX_AVDECODER 315*0c0d06caSMauro Carvalho Chehab }; 316*0c0d06caSMauro Carvalho Chehab 317*0c0d06caSMauro Carvalho Chehab enum CX231XX_I2C_MASTER_PORT { 318*0c0d06caSMauro Carvalho Chehab I2C_0 = 0, 319*0c0d06caSMauro Carvalho Chehab I2C_1 = 1, 320*0c0d06caSMauro Carvalho Chehab I2C_2 = 2, 321*0c0d06caSMauro Carvalho Chehab I2C_3 = 3 322*0c0d06caSMauro Carvalho Chehab }; 323*0c0d06caSMauro Carvalho Chehab 324*0c0d06caSMauro Carvalho Chehab struct cx231xx_board { 325*0c0d06caSMauro Carvalho Chehab char *name; 326*0c0d06caSMauro Carvalho Chehab int vchannels; 327*0c0d06caSMauro Carvalho Chehab int tuner_type; 328*0c0d06caSMauro Carvalho Chehab int tuner_addr; 329*0c0d06caSMauro Carvalho Chehab v4l2_std_id norm; /* tv norm */ 330*0c0d06caSMauro Carvalho Chehab 331*0c0d06caSMauro Carvalho Chehab /* demod related */ 332*0c0d06caSMauro Carvalho Chehab int demod_addr; 333*0c0d06caSMauro Carvalho Chehab u8 demod_xfer_mode; /* 0 - Serial; 1 - parallel */ 334*0c0d06caSMauro Carvalho Chehab 335*0c0d06caSMauro Carvalho Chehab /* GPIO Pins */ 336*0c0d06caSMauro Carvalho Chehab struct cx231xx_reg_seq *dvb_gpio; 337*0c0d06caSMauro Carvalho Chehab struct cx231xx_reg_seq *suspend_gpio; 338*0c0d06caSMauro Carvalho Chehab struct cx231xx_reg_seq *tuner_gpio; 339*0c0d06caSMauro Carvalho Chehab /* Negative means don't use it */ 340*0c0d06caSMauro Carvalho Chehab s8 tuner_sif_gpio; 341*0c0d06caSMauro Carvalho Chehab s8 tuner_scl_gpio; 342*0c0d06caSMauro Carvalho Chehab s8 tuner_sda_gpio; 343*0c0d06caSMauro Carvalho Chehab 344*0c0d06caSMauro Carvalho Chehab /* PIN ctrl */ 345*0c0d06caSMauro Carvalho Chehab u32 ctl_pin_status_mask; 346*0c0d06caSMauro Carvalho Chehab u8 agc_analog_digital_select_gpio; 347*0c0d06caSMauro Carvalho Chehab u32 gpio_pin_status_mask; 348*0c0d06caSMauro Carvalho Chehab 349*0c0d06caSMauro Carvalho Chehab /* i2c masters */ 350*0c0d06caSMauro Carvalho Chehab u8 tuner_i2c_master; 351*0c0d06caSMauro Carvalho Chehab u8 demod_i2c_master; 352*0c0d06caSMauro Carvalho Chehab u8 ir_i2c_master; 353*0c0d06caSMauro Carvalho Chehab 354*0c0d06caSMauro Carvalho Chehab /* for devices with I2C chips for IR */ 355*0c0d06caSMauro Carvalho Chehab char *rc_map_name; 356*0c0d06caSMauro Carvalho Chehab 357*0c0d06caSMauro Carvalho Chehab unsigned int max_range_640_480:1; 358*0c0d06caSMauro Carvalho Chehab unsigned int has_dvb:1; 359*0c0d06caSMauro Carvalho Chehab unsigned int has_417:1; 360*0c0d06caSMauro Carvalho Chehab unsigned int valid:1; 361*0c0d06caSMauro Carvalho Chehab unsigned int no_alt_vanc:1; 362*0c0d06caSMauro Carvalho Chehab unsigned int external_av:1; 363*0c0d06caSMauro Carvalho Chehab unsigned int dont_use_port_3:1; 364*0c0d06caSMauro Carvalho Chehab 365*0c0d06caSMauro Carvalho Chehab unsigned char xclk, i2c_speed; 366*0c0d06caSMauro Carvalho Chehab 367*0c0d06caSMauro Carvalho Chehab enum cx231xx_decoder decoder; 368*0c0d06caSMauro Carvalho Chehab int output_mode; 369*0c0d06caSMauro Carvalho Chehab 370*0c0d06caSMauro Carvalho Chehab struct cx231xx_input input[MAX_CX231XX_INPUT]; 371*0c0d06caSMauro Carvalho Chehab struct cx231xx_input radio; 372*0c0d06caSMauro Carvalho Chehab struct rc_map *ir_codes; 373*0c0d06caSMauro Carvalho Chehab }; 374*0c0d06caSMauro Carvalho Chehab 375*0c0d06caSMauro Carvalho Chehab /* device states */ 376*0c0d06caSMauro Carvalho Chehab enum cx231xx_dev_state { 377*0c0d06caSMauro Carvalho Chehab DEV_INITIALIZED = 0x01, 378*0c0d06caSMauro Carvalho Chehab DEV_DISCONNECTED = 0x02, 379*0c0d06caSMauro Carvalho Chehab }; 380*0c0d06caSMauro Carvalho Chehab 381*0c0d06caSMauro Carvalho Chehab enum AFE_MODE { 382*0c0d06caSMauro Carvalho Chehab AFE_MODE_LOW_IF, 383*0c0d06caSMauro Carvalho Chehab AFE_MODE_BASEBAND, 384*0c0d06caSMauro Carvalho Chehab AFE_MODE_EU_HI_IF, 385*0c0d06caSMauro Carvalho Chehab AFE_MODE_US_HI_IF, 386*0c0d06caSMauro Carvalho Chehab AFE_MODE_JAPAN_HI_IF 387*0c0d06caSMauro Carvalho Chehab }; 388*0c0d06caSMauro Carvalho Chehab 389*0c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT { 390*0c0d06caSMauro Carvalho Chehab AUDIO_INPUT_MUTE, 391*0c0d06caSMauro Carvalho Chehab AUDIO_INPUT_LINE, 392*0c0d06caSMauro Carvalho Chehab AUDIO_INPUT_TUNER_TV, 393*0c0d06caSMauro Carvalho Chehab AUDIO_INPUT_SPDIF, 394*0c0d06caSMauro Carvalho Chehab AUDIO_INPUT_TUNER_FM 395*0c0d06caSMauro Carvalho Chehab }; 396*0c0d06caSMauro Carvalho Chehab 397*0c0d06caSMauro Carvalho Chehab #define CX231XX_AUDIO_BUFS 5 398*0c0d06caSMauro Carvalho Chehab #define CX231XX_NUM_AUDIO_PACKETS 16 399*0c0d06caSMauro Carvalho Chehab #define CX231XX_ISO_NUM_AUDIO_PACKETS 64 400*0c0d06caSMauro Carvalho Chehab 401*0c0d06caSMauro Carvalho Chehab /* cx231xx extensions */ 402*0c0d06caSMauro Carvalho Chehab #define CX231XX_AUDIO 0x10 403*0c0d06caSMauro Carvalho Chehab #define CX231XX_DVB 0x20 404*0c0d06caSMauro Carvalho Chehab 405*0c0d06caSMauro Carvalho Chehab struct cx231xx_audio { 406*0c0d06caSMauro Carvalho Chehab char name[50]; 407*0c0d06caSMauro Carvalho Chehab char *transfer_buffer[CX231XX_AUDIO_BUFS]; 408*0c0d06caSMauro Carvalho Chehab struct urb *urb[CX231XX_AUDIO_BUFS]; 409*0c0d06caSMauro Carvalho Chehab struct usb_device *udev; 410*0c0d06caSMauro Carvalho Chehab unsigned int capture_transfer_done; 411*0c0d06caSMauro Carvalho Chehab struct snd_pcm_substream *capture_pcm_substream; 412*0c0d06caSMauro Carvalho Chehab 413*0c0d06caSMauro Carvalho Chehab unsigned int hwptr_done_capture; 414*0c0d06caSMauro Carvalho Chehab struct snd_card *sndcard; 415*0c0d06caSMauro Carvalho Chehab 416*0c0d06caSMauro Carvalho Chehab int users, shutdown; 417*0c0d06caSMauro Carvalho Chehab /* locks */ 418*0c0d06caSMauro Carvalho Chehab spinlock_t slock; 419*0c0d06caSMauro Carvalho Chehab 420*0c0d06caSMauro Carvalho Chehab int alt; /* alternate */ 421*0c0d06caSMauro Carvalho Chehab int max_pkt_size; /* max packet size of isoc transaction */ 422*0c0d06caSMauro Carvalho Chehab int num_alt; /* Number of alternative settings */ 423*0c0d06caSMauro Carvalho Chehab unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ 424*0c0d06caSMauro Carvalho Chehab u16 end_point_addr; 425*0c0d06caSMauro Carvalho Chehab }; 426*0c0d06caSMauro Carvalho Chehab 427*0c0d06caSMauro Carvalho Chehab struct cx231xx; 428*0c0d06caSMauro Carvalho Chehab 429*0c0d06caSMauro Carvalho Chehab struct cx231xx_fh { 430*0c0d06caSMauro Carvalho Chehab struct cx231xx *dev; 431*0c0d06caSMauro Carvalho Chehab unsigned int stream_on:1; /* Locks streams */ 432*0c0d06caSMauro Carvalho Chehab int radio; 433*0c0d06caSMauro Carvalho Chehab 434*0c0d06caSMauro Carvalho Chehab struct videobuf_queue vb_vidq; 435*0c0d06caSMauro Carvalho Chehab 436*0c0d06caSMauro Carvalho Chehab enum v4l2_buf_type type; 437*0c0d06caSMauro Carvalho Chehab 438*0c0d06caSMauro Carvalho Chehab 439*0c0d06caSMauro Carvalho Chehab 440*0c0d06caSMauro Carvalho Chehab /*following is copyed from cx23885.h*/ 441*0c0d06caSMauro Carvalho Chehab u32 resources; 442*0c0d06caSMauro Carvalho Chehab 443*0c0d06caSMauro Carvalho Chehab /* video overlay */ 444*0c0d06caSMauro Carvalho Chehab struct v4l2_window win; 445*0c0d06caSMauro Carvalho Chehab struct v4l2_clip *clips; 446*0c0d06caSMauro Carvalho Chehab unsigned int nclips; 447*0c0d06caSMauro Carvalho Chehab 448*0c0d06caSMauro Carvalho Chehab /* video capture */ 449*0c0d06caSMauro Carvalho Chehab struct cx23417_fmt *fmt; 450*0c0d06caSMauro Carvalho Chehab unsigned int width, height; 451*0c0d06caSMauro Carvalho Chehab 452*0c0d06caSMauro Carvalho Chehab /* vbi capture */ 453*0c0d06caSMauro Carvalho Chehab struct videobuf_queue vidq; 454*0c0d06caSMauro Carvalho Chehab struct videobuf_queue vbiq; 455*0c0d06caSMauro Carvalho Chehab 456*0c0d06caSMauro Carvalho Chehab /* MPEG Encoder specifics ONLY */ 457*0c0d06caSMauro Carvalho Chehab 458*0c0d06caSMauro Carvalho Chehab atomic_t v4l_reading; 459*0c0d06caSMauro Carvalho Chehab }; 460*0c0d06caSMauro Carvalho Chehab 461*0c0d06caSMauro Carvalho Chehab /*****************************************************************/ 462*0c0d06caSMauro Carvalho Chehab /* set/get i2c */ 463*0c0d06caSMauro Carvalho Chehab /* 00--1Mb/s, 01-400kb/s, 10--100kb/s, 11--5Mb/s */ 464*0c0d06caSMauro Carvalho Chehab #define I2C_SPEED_1M 0x0 465*0c0d06caSMauro Carvalho Chehab #define I2C_SPEED_400K 0x1 466*0c0d06caSMauro Carvalho Chehab #define I2C_SPEED_100K 0x2 467*0c0d06caSMauro Carvalho Chehab #define I2C_SPEED_5M 0x3 468*0c0d06caSMauro Carvalho Chehab 469*0c0d06caSMauro Carvalho Chehab /* 0-- STOP transaction */ 470*0c0d06caSMauro Carvalho Chehab #define I2C_STOP 0x0 471*0c0d06caSMauro Carvalho Chehab /* 1-- do not transmit STOP at end of transaction */ 472*0c0d06caSMauro Carvalho Chehab #define I2C_NOSTOP 0x1 473*0c0d06caSMauro Carvalho Chehab /* 1--allow slave to insert clock wait states */ 474*0c0d06caSMauro Carvalho Chehab #define I2C_SYNC 0x1 475*0c0d06caSMauro Carvalho Chehab 476*0c0d06caSMauro Carvalho Chehab struct cx231xx_i2c { 477*0c0d06caSMauro Carvalho Chehab struct cx231xx *dev; 478*0c0d06caSMauro Carvalho Chehab 479*0c0d06caSMauro Carvalho Chehab int nr; 480*0c0d06caSMauro Carvalho Chehab 481*0c0d06caSMauro Carvalho Chehab /* i2c i/o */ 482*0c0d06caSMauro Carvalho Chehab struct i2c_adapter i2c_adap; 483*0c0d06caSMauro Carvalho Chehab struct i2c_client i2c_client; 484*0c0d06caSMauro Carvalho Chehab u32 i2c_rc; 485*0c0d06caSMauro Carvalho Chehab 486*0c0d06caSMauro Carvalho Chehab /* different settings for each bus */ 487*0c0d06caSMauro Carvalho Chehab u8 i2c_period; 488*0c0d06caSMauro Carvalho Chehab u8 i2c_nostop; 489*0c0d06caSMauro Carvalho Chehab u8 i2c_reserve; 490*0c0d06caSMauro Carvalho Chehab }; 491*0c0d06caSMauro Carvalho Chehab 492*0c0d06caSMauro Carvalho Chehab struct cx231xx_i2c_xfer_data { 493*0c0d06caSMauro Carvalho Chehab u8 dev_addr; 494*0c0d06caSMauro Carvalho Chehab u8 direction; /* 1 - IN, 0 - OUT */ 495*0c0d06caSMauro Carvalho Chehab u8 saddr_len; /* sub address len */ 496*0c0d06caSMauro Carvalho Chehab u16 saddr_dat; /* sub addr data */ 497*0c0d06caSMauro Carvalho Chehab u8 buf_size; /* buffer size */ 498*0c0d06caSMauro Carvalho Chehab u8 *p_buffer; /* pointer to the buffer */ 499*0c0d06caSMauro Carvalho Chehab }; 500*0c0d06caSMauro Carvalho Chehab 501*0c0d06caSMauro Carvalho Chehab struct VENDOR_REQUEST_IN { 502*0c0d06caSMauro Carvalho Chehab u8 bRequest; 503*0c0d06caSMauro Carvalho Chehab u16 wValue; 504*0c0d06caSMauro Carvalho Chehab u16 wIndex; 505*0c0d06caSMauro Carvalho Chehab u16 wLength; 506*0c0d06caSMauro Carvalho Chehab u8 direction; 507*0c0d06caSMauro Carvalho Chehab u8 bData; 508*0c0d06caSMauro Carvalho Chehab u8 *pBuff; 509*0c0d06caSMauro Carvalho Chehab }; 510*0c0d06caSMauro Carvalho Chehab 511*0c0d06caSMauro Carvalho Chehab struct cx231xx_tvnorm { 512*0c0d06caSMauro Carvalho Chehab char *name; 513*0c0d06caSMauro Carvalho Chehab v4l2_std_id id; 514*0c0d06caSMauro Carvalho Chehab u32 cxiformat; 515*0c0d06caSMauro Carvalho Chehab u32 cxoformat; 516*0c0d06caSMauro Carvalho Chehab }; 517*0c0d06caSMauro Carvalho Chehab 518*0c0d06caSMauro Carvalho Chehab struct cx231xx_ctrl { 519*0c0d06caSMauro Carvalho Chehab struct v4l2_queryctrl v; 520*0c0d06caSMauro Carvalho Chehab u32 off; 521*0c0d06caSMauro Carvalho Chehab u32 reg; 522*0c0d06caSMauro Carvalho Chehab u32 mask; 523*0c0d06caSMauro Carvalho Chehab u32 shift; 524*0c0d06caSMauro Carvalho Chehab }; 525*0c0d06caSMauro Carvalho Chehab 526*0c0d06caSMauro Carvalho Chehab enum TRANSFER_TYPE { 527*0c0d06caSMauro Carvalho Chehab Raw_Video = 0, 528*0c0d06caSMauro Carvalho Chehab Audio, 529*0c0d06caSMauro Carvalho Chehab Vbi, /* VANC */ 530*0c0d06caSMauro Carvalho Chehab Sliced_cc, /* HANC */ 531*0c0d06caSMauro Carvalho Chehab TS1_serial_mode, 532*0c0d06caSMauro Carvalho Chehab TS2, 533*0c0d06caSMauro Carvalho Chehab TS1_parallel_mode 534*0c0d06caSMauro Carvalho Chehab } ; 535*0c0d06caSMauro Carvalho Chehab 536*0c0d06caSMauro Carvalho Chehab struct cx231xx_video_mode { 537*0c0d06caSMauro Carvalho Chehab /* Isoc control struct */ 538*0c0d06caSMauro Carvalho Chehab struct cx231xx_dmaqueue vidq; 539*0c0d06caSMauro Carvalho Chehab struct cx231xx_isoc_ctl isoc_ctl; 540*0c0d06caSMauro Carvalho Chehab struct cx231xx_bulk_ctl bulk_ctl; 541*0c0d06caSMauro Carvalho Chehab /* locks */ 542*0c0d06caSMauro Carvalho Chehab spinlock_t slock; 543*0c0d06caSMauro Carvalho Chehab 544*0c0d06caSMauro Carvalho Chehab /* usb transfer */ 545*0c0d06caSMauro Carvalho Chehab int alt; /* alternate */ 546*0c0d06caSMauro Carvalho Chehab int max_pkt_size; /* max packet size of isoc transaction */ 547*0c0d06caSMauro Carvalho Chehab int num_alt; /* Number of alternative settings */ 548*0c0d06caSMauro Carvalho Chehab unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ 549*0c0d06caSMauro Carvalho Chehab u16 end_point_addr; 550*0c0d06caSMauro Carvalho Chehab }; 551*0c0d06caSMauro Carvalho Chehab /* 552*0c0d06caSMauro Carvalho Chehab struct cx23885_dmaqueue { 553*0c0d06caSMauro Carvalho Chehab struct list_head active; 554*0c0d06caSMauro Carvalho Chehab struct list_head queued; 555*0c0d06caSMauro Carvalho Chehab struct timer_list timeout; 556*0c0d06caSMauro Carvalho Chehab struct btcx_riscmem stopper; 557*0c0d06caSMauro Carvalho Chehab u32 count; 558*0c0d06caSMauro Carvalho Chehab }; 559*0c0d06caSMauro Carvalho Chehab */ 560*0c0d06caSMauro Carvalho Chehab struct cx231xx_tsport { 561*0c0d06caSMauro Carvalho Chehab struct cx231xx *dev; 562*0c0d06caSMauro Carvalho Chehab 563*0c0d06caSMauro Carvalho Chehab int nr; 564*0c0d06caSMauro Carvalho Chehab int sram_chno; 565*0c0d06caSMauro Carvalho Chehab 566*0c0d06caSMauro Carvalho Chehab struct videobuf_dvb_frontends frontends; 567*0c0d06caSMauro Carvalho Chehab 568*0c0d06caSMauro Carvalho Chehab /* dma queues */ 569*0c0d06caSMauro Carvalho Chehab 570*0c0d06caSMauro Carvalho Chehab u32 ts_packet_size; 571*0c0d06caSMauro Carvalho Chehab u32 ts_packet_count; 572*0c0d06caSMauro Carvalho Chehab 573*0c0d06caSMauro Carvalho Chehab int width; 574*0c0d06caSMauro Carvalho Chehab int height; 575*0c0d06caSMauro Carvalho Chehab 576*0c0d06caSMauro Carvalho Chehab /* locks */ 577*0c0d06caSMauro Carvalho Chehab spinlock_t slock; 578*0c0d06caSMauro Carvalho Chehab 579*0c0d06caSMauro Carvalho Chehab /* registers */ 580*0c0d06caSMauro Carvalho Chehab u32 reg_gpcnt; 581*0c0d06caSMauro Carvalho Chehab u32 reg_gpcnt_ctl; 582*0c0d06caSMauro Carvalho Chehab u32 reg_dma_ctl; 583*0c0d06caSMauro Carvalho Chehab u32 reg_lngth; 584*0c0d06caSMauro Carvalho Chehab u32 reg_hw_sop_ctrl; 585*0c0d06caSMauro Carvalho Chehab u32 reg_gen_ctrl; 586*0c0d06caSMauro Carvalho Chehab u32 reg_bd_pkt_status; 587*0c0d06caSMauro Carvalho Chehab u32 reg_sop_status; 588*0c0d06caSMauro Carvalho Chehab u32 reg_fifo_ovfl_stat; 589*0c0d06caSMauro Carvalho Chehab u32 reg_vld_misc; 590*0c0d06caSMauro Carvalho Chehab u32 reg_ts_clk_en; 591*0c0d06caSMauro Carvalho Chehab u32 reg_ts_int_msk; 592*0c0d06caSMauro Carvalho Chehab u32 reg_ts_int_stat; 593*0c0d06caSMauro Carvalho Chehab u32 reg_src_sel; 594*0c0d06caSMauro Carvalho Chehab 595*0c0d06caSMauro Carvalho Chehab /* Default register vals */ 596*0c0d06caSMauro Carvalho Chehab int pci_irqmask; 597*0c0d06caSMauro Carvalho Chehab u32 dma_ctl_val; 598*0c0d06caSMauro Carvalho Chehab u32 ts_int_msk_val; 599*0c0d06caSMauro Carvalho Chehab u32 gen_ctrl_val; 600*0c0d06caSMauro Carvalho Chehab u32 ts_clk_en_val; 601*0c0d06caSMauro Carvalho Chehab u32 src_sel_val; 602*0c0d06caSMauro Carvalho Chehab u32 vld_misc_val; 603*0c0d06caSMauro Carvalho Chehab u32 hw_sop_ctrl_val; 604*0c0d06caSMauro Carvalho Chehab 605*0c0d06caSMauro Carvalho Chehab /* Allow a single tsport to have multiple frontends */ 606*0c0d06caSMauro Carvalho Chehab u32 num_frontends; 607*0c0d06caSMauro Carvalho Chehab void *port_priv; 608*0c0d06caSMauro Carvalho Chehab }; 609*0c0d06caSMauro Carvalho Chehab 610*0c0d06caSMauro Carvalho Chehab /* main device struct */ 611*0c0d06caSMauro Carvalho Chehab struct cx231xx { 612*0c0d06caSMauro Carvalho Chehab /* generic device properties */ 613*0c0d06caSMauro Carvalho Chehab char name[30]; /* name (including minor) of the device */ 614*0c0d06caSMauro Carvalho Chehab int model; /* index in the device_data struct */ 615*0c0d06caSMauro Carvalho Chehab int devno; /* marks the number of this device */ 616*0c0d06caSMauro Carvalho Chehab 617*0c0d06caSMauro Carvalho Chehab struct cx231xx_board board; 618*0c0d06caSMauro Carvalho Chehab 619*0c0d06caSMauro Carvalho Chehab /* For I2C IR support */ 620*0c0d06caSMauro Carvalho Chehab struct IR_i2c_init_data init_data; 621*0c0d06caSMauro Carvalho Chehab struct i2c_client *ir_i2c_client; 622*0c0d06caSMauro Carvalho Chehab 623*0c0d06caSMauro Carvalho Chehab unsigned int stream_on:1; /* Locks streams */ 624*0c0d06caSMauro Carvalho Chehab unsigned int vbi_stream_on:1; /* Locks streams for VBI */ 625*0c0d06caSMauro Carvalho Chehab unsigned int has_audio_class:1; 626*0c0d06caSMauro Carvalho Chehab unsigned int has_alsa_audio:1; 627*0c0d06caSMauro Carvalho Chehab 628*0c0d06caSMauro Carvalho Chehab struct cx231xx_fmt *format; 629*0c0d06caSMauro Carvalho Chehab 630*0c0d06caSMauro Carvalho Chehab struct v4l2_device v4l2_dev; 631*0c0d06caSMauro Carvalho Chehab struct v4l2_subdev *sd_cx25840; 632*0c0d06caSMauro Carvalho Chehab struct v4l2_subdev *sd_tuner; 633*0c0d06caSMauro Carvalho Chehab 634*0c0d06caSMauro Carvalho Chehab struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */ 635*0c0d06caSMauro Carvalho Chehab atomic_t stream_started; /* stream should be running if true */ 636*0c0d06caSMauro Carvalho Chehab 637*0c0d06caSMauro Carvalho Chehab struct list_head devlist; 638*0c0d06caSMauro Carvalho Chehab 639*0c0d06caSMauro Carvalho Chehab int tuner_type; /* type of the tuner */ 640*0c0d06caSMauro Carvalho Chehab int tuner_addr; /* tuner address */ 641*0c0d06caSMauro Carvalho Chehab 642*0c0d06caSMauro Carvalho Chehab /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ 643*0c0d06caSMauro Carvalho Chehab struct cx231xx_i2c i2c_bus[3]; 644*0c0d06caSMauro Carvalho Chehab unsigned int xc_fw_load_done:1; 645*0c0d06caSMauro Carvalho Chehab /* locks */ 646*0c0d06caSMauro Carvalho Chehab struct mutex gpio_i2c_lock; 647*0c0d06caSMauro Carvalho Chehab struct mutex i2c_lock; 648*0c0d06caSMauro Carvalho Chehab 649*0c0d06caSMauro Carvalho Chehab /* video for linux */ 650*0c0d06caSMauro Carvalho Chehab int users; /* user count for exclusive use */ 651*0c0d06caSMauro Carvalho Chehab struct video_device *vdev; /* video for linux device struct */ 652*0c0d06caSMauro Carvalho Chehab v4l2_std_id norm; /* selected tv norm */ 653*0c0d06caSMauro Carvalho Chehab int ctl_freq; /* selected frequency */ 654*0c0d06caSMauro Carvalho Chehab unsigned int ctl_ainput; /* selected audio input */ 655*0c0d06caSMauro Carvalho Chehab int mute; 656*0c0d06caSMauro Carvalho Chehab int volume; 657*0c0d06caSMauro Carvalho Chehab 658*0c0d06caSMauro Carvalho Chehab /* frame properties */ 659*0c0d06caSMauro Carvalho Chehab int width; /* current frame width */ 660*0c0d06caSMauro Carvalho Chehab int height; /* current frame height */ 661*0c0d06caSMauro Carvalho Chehab int interlaced; /* 1=interlace fileds, 0=just top fileds */ 662*0c0d06caSMauro Carvalho Chehab 663*0c0d06caSMauro Carvalho Chehab struct cx231xx_audio adev; 664*0c0d06caSMauro Carvalho Chehab 665*0c0d06caSMauro Carvalho Chehab /* states */ 666*0c0d06caSMauro Carvalho Chehab enum cx231xx_dev_state state; 667*0c0d06caSMauro Carvalho Chehab 668*0c0d06caSMauro Carvalho Chehab struct work_struct request_module_wk; 669*0c0d06caSMauro Carvalho Chehab 670*0c0d06caSMauro Carvalho Chehab /* locks */ 671*0c0d06caSMauro Carvalho Chehab struct mutex lock; 672*0c0d06caSMauro Carvalho Chehab struct mutex ctrl_urb_lock; /* protects urb_buf */ 673*0c0d06caSMauro Carvalho Chehab struct list_head inqueue, outqueue; 674*0c0d06caSMauro Carvalho Chehab wait_queue_head_t open, wait_frame, wait_stream; 675*0c0d06caSMauro Carvalho Chehab struct video_device *vbi_dev; 676*0c0d06caSMauro Carvalho Chehab struct video_device *radio_dev; 677*0c0d06caSMauro Carvalho Chehab 678*0c0d06caSMauro Carvalho Chehab unsigned char eedata[256]; 679*0c0d06caSMauro Carvalho Chehab 680*0c0d06caSMauro Carvalho Chehab struct cx231xx_video_mode video_mode; 681*0c0d06caSMauro Carvalho Chehab struct cx231xx_video_mode vbi_mode; 682*0c0d06caSMauro Carvalho Chehab struct cx231xx_video_mode sliced_cc_mode; 683*0c0d06caSMauro Carvalho Chehab struct cx231xx_video_mode ts1_mode; 684*0c0d06caSMauro Carvalho Chehab 685*0c0d06caSMauro Carvalho Chehab atomic_t devlist_count; 686*0c0d06caSMauro Carvalho Chehab 687*0c0d06caSMauro Carvalho Chehab struct usb_device *udev; /* the usb device */ 688*0c0d06caSMauro Carvalho Chehab char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */ 689*0c0d06caSMauro Carvalho Chehab 690*0c0d06caSMauro Carvalho Chehab /* helper funcs that call usb_control_msg */ 691*0c0d06caSMauro Carvalho Chehab int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg, 692*0c0d06caSMauro Carvalho Chehab char *buf, int len); 693*0c0d06caSMauro Carvalho Chehab int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg, 694*0c0d06caSMauro Carvalho Chehab char *buf, int len); 695*0c0d06caSMauro Carvalho Chehab int (*cx231xx_send_usb_command) (struct cx231xx_i2c *i2c_bus, 696*0c0d06caSMauro Carvalho Chehab struct cx231xx_i2c_xfer_data *req_data); 697*0c0d06caSMauro Carvalho Chehab int (*cx231xx_gpio_i2c_read) (struct cx231xx *dev, u8 dev_addr, 698*0c0d06caSMauro Carvalho Chehab u8 *buf, u8 len); 699*0c0d06caSMauro Carvalho Chehab int (*cx231xx_gpio_i2c_write) (struct cx231xx *dev, u8 dev_addr, 700*0c0d06caSMauro Carvalho Chehab u8 *buf, u8 len); 701*0c0d06caSMauro Carvalho Chehab 702*0c0d06caSMauro Carvalho Chehab int (*cx231xx_set_analog_freq) (struct cx231xx *dev, u32 freq); 703*0c0d06caSMauro Carvalho Chehab int (*cx231xx_reset_analog_tuner) (struct cx231xx *dev); 704*0c0d06caSMauro Carvalho Chehab 705*0c0d06caSMauro Carvalho Chehab enum cx231xx_mode mode; 706*0c0d06caSMauro Carvalho Chehab 707*0c0d06caSMauro Carvalho Chehab struct cx231xx_dvb *dvb; 708*0c0d06caSMauro Carvalho Chehab 709*0c0d06caSMauro Carvalho Chehab /* Cx231xx supported PCB config's */ 710*0c0d06caSMauro Carvalho Chehab struct pcb_config current_pcb_config; 711*0c0d06caSMauro Carvalho Chehab u8 current_scenario_idx; 712*0c0d06caSMauro Carvalho Chehab u8 interface_count; 713*0c0d06caSMauro Carvalho Chehab u8 max_iad_interface_count; 714*0c0d06caSMauro Carvalho Chehab 715*0c0d06caSMauro Carvalho Chehab /* GPIO related register direction and values */ 716*0c0d06caSMauro Carvalho Chehab u32 gpio_dir; 717*0c0d06caSMauro Carvalho Chehab u32 gpio_val; 718*0c0d06caSMauro Carvalho Chehab 719*0c0d06caSMauro Carvalho Chehab /* Power Modes */ 720*0c0d06caSMauro Carvalho Chehab int power_mode; 721*0c0d06caSMauro Carvalho Chehab 722*0c0d06caSMauro Carvalho Chehab /* afe parameters */ 723*0c0d06caSMauro Carvalho Chehab enum AFE_MODE afe_mode; 724*0c0d06caSMauro Carvalho Chehab u32 afe_ref_count; 725*0c0d06caSMauro Carvalho Chehab 726*0c0d06caSMauro Carvalho Chehab /* video related parameters */ 727*0c0d06caSMauro Carvalho Chehab u32 video_input; 728*0c0d06caSMauro Carvalho Chehab u32 active_mode; 729*0c0d06caSMauro Carvalho Chehab u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */ 730*0c0d06caSMauro Carvalho Chehab enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */ 731*0c0d06caSMauro Carvalho Chehab 732*0c0d06caSMauro Carvalho Chehab /*mode: digital=1 or analog=0*/ 733*0c0d06caSMauro Carvalho Chehab u8 mode_tv; 734*0c0d06caSMauro Carvalho Chehab 735*0c0d06caSMauro Carvalho Chehab u8 USE_ISO; 736*0c0d06caSMauro Carvalho Chehab struct cx231xx_tvnorm encodernorm; 737*0c0d06caSMauro Carvalho Chehab struct cx231xx_tsport ts1, ts2; 738*0c0d06caSMauro Carvalho Chehab struct cx2341x_mpeg_params mpeg_params; 739*0c0d06caSMauro Carvalho Chehab struct video_device *v4l_device; 740*0c0d06caSMauro Carvalho Chehab atomic_t v4l_reader_count; 741*0c0d06caSMauro Carvalho Chehab u32 freq; 742*0c0d06caSMauro Carvalho Chehab unsigned int input; 743*0c0d06caSMauro Carvalho Chehab u32 cx23417_mailbox; 744*0c0d06caSMauro Carvalho Chehab u32 __iomem *lmmio; 745*0c0d06caSMauro Carvalho Chehab u8 __iomem *bmmio; 746*0c0d06caSMauro Carvalho Chehab }; 747*0c0d06caSMauro Carvalho Chehab 748*0c0d06caSMauro Carvalho Chehab extern struct list_head cx231xx_devlist; 749*0c0d06caSMauro Carvalho Chehab 750*0c0d06caSMauro Carvalho Chehab #define cx25840_call(cx231xx, o, f, args...) \ 751*0c0d06caSMauro Carvalho Chehab v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args) 752*0c0d06caSMauro Carvalho Chehab #define tuner_call(cx231xx, o, f, args...) \ 753*0c0d06caSMauro Carvalho Chehab v4l2_subdev_call(cx231xx->sd_tuner, o, f, ##args) 754*0c0d06caSMauro Carvalho Chehab #define call_all(dev, o, f, args...) \ 755*0c0d06caSMauro Carvalho Chehab v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args) 756*0c0d06caSMauro Carvalho Chehab 757*0c0d06caSMauro Carvalho Chehab struct cx231xx_ops { 758*0c0d06caSMauro Carvalho Chehab struct list_head next; 759*0c0d06caSMauro Carvalho Chehab char *name; 760*0c0d06caSMauro Carvalho Chehab int id; 761*0c0d06caSMauro Carvalho Chehab int (*init) (struct cx231xx *); 762*0c0d06caSMauro Carvalho Chehab int (*fini) (struct cx231xx *); 763*0c0d06caSMauro Carvalho Chehab }; 764*0c0d06caSMauro Carvalho Chehab 765*0c0d06caSMauro Carvalho Chehab /* call back functions in dvb module */ 766*0c0d06caSMauro Carvalho Chehab int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq); 767*0c0d06caSMauro Carvalho Chehab int cx231xx_reset_analog_tuner(struct cx231xx *dev); 768*0c0d06caSMauro Carvalho Chehab 769*0c0d06caSMauro Carvalho Chehab /* Provided by cx231xx-i2c.c */ 770*0c0d06caSMauro Carvalho Chehab void cx231xx_do_i2c_scan(struct cx231xx *dev, struct i2c_client *c); 771*0c0d06caSMauro Carvalho Chehab int cx231xx_i2c_register(struct cx231xx_i2c *bus); 772*0c0d06caSMauro Carvalho Chehab int cx231xx_i2c_unregister(struct cx231xx_i2c *bus); 773*0c0d06caSMauro Carvalho Chehab 774*0c0d06caSMauro Carvalho Chehab /* Internal block control functions */ 775*0c0d06caSMauro Carvalho Chehab int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr, 776*0c0d06caSMauro Carvalho Chehab u8 saddr_len, u32 *data, u8 data_len, int master); 777*0c0d06caSMauro Carvalho Chehab int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr, 778*0c0d06caSMauro Carvalho Chehab u8 saddr_len, u32 data, u8 data_len, int master); 779*0c0d06caSMauro Carvalho Chehab int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, 780*0c0d06caSMauro Carvalho Chehab u16 saddr, u8 saddr_len, u32 *data, u8 data_len); 781*0c0d06caSMauro Carvalho Chehab int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr, 782*0c0d06caSMauro Carvalho Chehab u16 saddr, u8 saddr_len, u32 data, u8 data_len); 783*0c0d06caSMauro Carvalho Chehab int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size, 784*0c0d06caSMauro Carvalho Chehab u16 register_address, u8 bit_start, u8 bit_end, 785*0c0d06caSMauro Carvalho Chehab u32 value); 786*0c0d06caSMauro Carvalho Chehab int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr, 787*0c0d06caSMauro Carvalho Chehab u16 saddr, u32 mask, u32 value); 788*0c0d06caSMauro Carvalho Chehab u32 cx231xx_set_field(u32 field_mask, u32 data); 789*0c0d06caSMauro Carvalho Chehab 790*0c0d06caSMauro Carvalho Chehab /*verve r/w*/ 791*0c0d06caSMauro Carvalho Chehab void initGPIO(struct cx231xx *dev); 792*0c0d06caSMauro Carvalho Chehab void uninitGPIO(struct cx231xx *dev); 793*0c0d06caSMauro Carvalho Chehab /* afe related functions */ 794*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count); 795*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_channels(struct cx231xx *dev); 796*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev); 797*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux); 798*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode); 799*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_update_power_control(struct cx231xx *dev, 800*0c0d06caSMauro Carvalho Chehab enum AV_MODE avmode); 801*0c0d06caSMauro Carvalho Chehab int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input); 802*0c0d06caSMauro Carvalho Chehab 803*0c0d06caSMauro Carvalho Chehab /* i2s block related functions */ 804*0c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_initialize(struct cx231xx *dev); 805*0c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 806*0c0d06caSMauro Carvalho Chehab enum AV_MODE avmode); 807*0c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input); 808*0c0d06caSMauro Carvalho Chehab 809*0c0d06caSMauro Carvalho Chehab /* DIF related functions */ 810*0c0d06caSMauro Carvalho Chehab int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 811*0c0d06caSMauro Carvalho Chehab u32 function_mode, u32 standard); 812*0c0d06caSMauro Carvalho Chehab void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 813*0c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode); 814*0c0d06caSMauro Carvalho Chehab u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd); 815*0c0d06caSMauro Carvalho Chehab void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 816*0c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode); 817*0c0d06caSMauro Carvalho Chehab void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev); 818*0c0d06caSMauro Carvalho Chehab void reset_s5h1432_demod(struct cx231xx *dev); 819*0c0d06caSMauro Carvalho Chehab void cx231xx_dump_HH_reg(struct cx231xx *dev); 820*0c0d06caSMauro Carvalho Chehab void update_HH_register_after_set_DIF(struct cx231xx *dev); 821*0c0d06caSMauro Carvalho Chehab void cx231xx_dump_SC_reg(struct cx231xx *dev); 822*0c0d06caSMauro Carvalho Chehab 823*0c0d06caSMauro Carvalho Chehab 824*0c0d06caSMauro Carvalho Chehab 825*0c0d06caSMauro Carvalho Chehab int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard); 826*0c0d06caSMauro Carvalho Chehab int cx231xx_tuner_pre_channel_change(struct cx231xx *dev); 827*0c0d06caSMauro Carvalho Chehab int cx231xx_tuner_post_channel_change(struct cx231xx *dev); 828*0c0d06caSMauro Carvalho Chehab 829*0c0d06caSMauro Carvalho Chehab /* video parser functions */ 830*0c0d06caSMauro Carvalho Chehab u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size, 831*0c0d06caSMauro Carvalho Chehab u32 *p_bytes_used); 832*0c0d06caSMauro Carvalho Chehab u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf, 833*0c0d06caSMauro Carvalho Chehab u32 *p_bytes_used); 834*0c0d06caSMauro Carvalho Chehab int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q, 835*0c0d06caSMauro Carvalho Chehab u8 *p_buffer, u32 bytes_to_copy); 836*0c0d06caSMauro Carvalho Chehab void cx231xx_reset_video_buffer(struct cx231xx *dev, 837*0c0d06caSMauro Carvalho Chehab struct cx231xx_dmaqueue *dma_q); 838*0c0d06caSMauro Carvalho Chehab u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q); 839*0c0d06caSMauro Carvalho Chehab u32 cx231xx_copy_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q, 840*0c0d06caSMauro Carvalho Chehab u8 *p_line, u32 length, int field_number); 841*0c0d06caSMauro Carvalho Chehab u32 cx231xx_get_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q, 842*0c0d06caSMauro Carvalho Chehab u8 sav_eav, u8 *p_buffer, u32 buffer_size); 843*0c0d06caSMauro Carvalho Chehab void cx231xx_swab(u16 *from, u16 *to, u16 len); 844*0c0d06caSMauro Carvalho Chehab 845*0c0d06caSMauro Carvalho Chehab /* Provided by cx231xx-core.c */ 846*0c0d06caSMauro Carvalho Chehab 847*0c0d06caSMauro Carvalho Chehab u32 cx231xx_request_buffers(struct cx231xx *dev, u32 count); 848*0c0d06caSMauro Carvalho Chehab void cx231xx_queue_unusedframes(struct cx231xx *dev); 849*0c0d06caSMauro Carvalho Chehab void cx231xx_release_buffers(struct cx231xx *dev); 850*0c0d06caSMauro Carvalho Chehab 851*0c0d06caSMauro Carvalho Chehab /* read from control pipe */ 852*0c0d06caSMauro Carvalho Chehab int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, 853*0c0d06caSMauro Carvalho Chehab char *buf, int len); 854*0c0d06caSMauro Carvalho Chehab 855*0c0d06caSMauro Carvalho Chehab /* write to control pipe */ 856*0c0d06caSMauro Carvalho Chehab int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, 857*0c0d06caSMauro Carvalho Chehab char *buf, int len); 858*0c0d06caSMauro Carvalho Chehab int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode); 859*0c0d06caSMauro Carvalho Chehab 860*0c0d06caSMauro Carvalho Chehab int cx231xx_send_vendor_cmd(struct cx231xx *dev, 861*0c0d06caSMauro Carvalho Chehab struct VENDOR_REQUEST_IN *ven_req); 862*0c0d06caSMauro Carvalho Chehab int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus, 863*0c0d06caSMauro Carvalho Chehab struct cx231xx_i2c_xfer_data *req_data); 864*0c0d06caSMauro Carvalho Chehab 865*0c0d06caSMauro Carvalho Chehab /* Gpio related functions */ 866*0c0d06caSMauro Carvalho Chehab int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val, 867*0c0d06caSMauro Carvalho Chehab u8 len, u8 request, u8 direction); 868*0c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val); 869*0c0d06caSMauro Carvalho Chehab int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val); 870*0c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value); 871*0c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_direction(struct cx231xx *dev, int pin_number, 872*0c0d06caSMauro Carvalho Chehab int pin_value); 873*0c0d06caSMauro Carvalho Chehab 874*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_start(struct cx231xx *dev); 875*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_end(struct cx231xx *dev); 876*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data); 877*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf); 878*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev); 879*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev); 880*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev); 881*0c0d06caSMauro Carvalho Chehab 882*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len); 883*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len); 884*0c0d06caSMauro Carvalho Chehab 885*0c0d06caSMauro Carvalho Chehab /* audio related functions */ 886*0c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 887*0c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT audio_input); 888*0c0d06caSMauro Carvalho Chehab 889*0c0d06caSMauro Carvalho Chehab int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type); 890*0c0d06caSMauro Carvalho Chehab int cx231xx_set_video_alternate(struct cx231xx *dev); 891*0c0d06caSMauro Carvalho Chehab int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt); 892*0c0d06caSMauro Carvalho Chehab int is_fw_load(struct cx231xx *dev); 893*0c0d06caSMauro Carvalho Chehab int cx231xx_check_fw(struct cx231xx *dev); 894*0c0d06caSMauro Carvalho Chehab int cx231xx_init_isoc(struct cx231xx *dev, int max_packets, 895*0c0d06caSMauro Carvalho Chehab int num_bufs, int max_pkt_size, 896*0c0d06caSMauro Carvalho Chehab int (*isoc_copy) (struct cx231xx *dev, 897*0c0d06caSMauro Carvalho Chehab struct urb *urb)); 898*0c0d06caSMauro Carvalho Chehab int cx231xx_init_bulk(struct cx231xx *dev, int max_packets, 899*0c0d06caSMauro Carvalho Chehab int num_bufs, int max_pkt_size, 900*0c0d06caSMauro Carvalho Chehab int (*bulk_copy) (struct cx231xx *dev, 901*0c0d06caSMauro Carvalho Chehab struct urb *urb)); 902*0c0d06caSMauro Carvalho Chehab void cx231xx_stop_TS1(struct cx231xx *dev); 903*0c0d06caSMauro Carvalho Chehab void cx231xx_start_TS1(struct cx231xx *dev); 904*0c0d06caSMauro Carvalho Chehab void cx231xx_uninit_isoc(struct cx231xx *dev); 905*0c0d06caSMauro Carvalho Chehab void cx231xx_uninit_bulk(struct cx231xx *dev); 906*0c0d06caSMauro Carvalho Chehab int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode); 907*0c0d06caSMauro Carvalho Chehab int cx231xx_unmute_audio(struct cx231xx *dev); 908*0c0d06caSMauro Carvalho Chehab int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size); 909*0c0d06caSMauro Carvalho Chehab void cx231xx_disable656(struct cx231xx *dev); 910*0c0d06caSMauro Carvalho Chehab void cx231xx_enable656(struct cx231xx *dev); 911*0c0d06caSMauro Carvalho Chehab int cx231xx_demod_reset(struct cx231xx *dev); 912*0c0d06caSMauro Carvalho Chehab int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio); 913*0c0d06caSMauro Carvalho Chehab 914*0c0d06caSMauro Carvalho Chehab /* Device list functions */ 915*0c0d06caSMauro Carvalho Chehab void cx231xx_release_resources(struct cx231xx *dev); 916*0c0d06caSMauro Carvalho Chehab void cx231xx_release_analog_resources(struct cx231xx *dev); 917*0c0d06caSMauro Carvalho Chehab int cx231xx_register_analog_devices(struct cx231xx *dev); 918*0c0d06caSMauro Carvalho Chehab void cx231xx_remove_from_devlist(struct cx231xx *dev); 919*0c0d06caSMauro Carvalho Chehab void cx231xx_add_into_devlist(struct cx231xx *dev); 920*0c0d06caSMauro Carvalho Chehab void cx231xx_init_extension(struct cx231xx *dev); 921*0c0d06caSMauro Carvalho Chehab void cx231xx_close_extension(struct cx231xx *dev); 922*0c0d06caSMauro Carvalho Chehab 923*0c0d06caSMauro Carvalho Chehab /* hardware init functions */ 924*0c0d06caSMauro Carvalho Chehab int cx231xx_dev_init(struct cx231xx *dev); 925*0c0d06caSMauro Carvalho Chehab void cx231xx_dev_uninit(struct cx231xx *dev); 926*0c0d06caSMauro Carvalho Chehab void cx231xx_config_i2c(struct cx231xx *dev); 927*0c0d06caSMauro Carvalho Chehab int cx231xx_config(struct cx231xx *dev); 928*0c0d06caSMauro Carvalho Chehab 929*0c0d06caSMauro Carvalho Chehab /* Stream control functions */ 930*0c0d06caSMauro Carvalho Chehab int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask); 931*0c0d06caSMauro Carvalho Chehab int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask); 932*0c0d06caSMauro Carvalho Chehab 933*0c0d06caSMauro Carvalho Chehab int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type); 934*0c0d06caSMauro Carvalho Chehab 935*0c0d06caSMauro Carvalho Chehab /* Power control functions */ 936*0c0d06caSMauro Carvalho Chehab int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode); 937*0c0d06caSMauro Carvalho Chehab int cx231xx_power_suspend(struct cx231xx *dev); 938*0c0d06caSMauro Carvalho Chehab 939*0c0d06caSMauro Carvalho Chehab /* chip specific control functions */ 940*0c0d06caSMauro Carvalho Chehab int cx231xx_init_ctrl_pin_status(struct cx231xx *dev); 941*0c0d06caSMauro Carvalho Chehab int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 942*0c0d06caSMauro Carvalho Chehab u8 analog_or_digital); 943*0c0d06caSMauro Carvalho Chehab int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3); 944*0c0d06caSMauro Carvalho Chehab 945*0c0d06caSMauro Carvalho Chehab /* video audio decoder related functions */ 946*0c0d06caSMauro Carvalho Chehab void video_mux(struct cx231xx *dev, int index); 947*0c0d06caSMauro Carvalho Chehab int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input); 948*0c0d06caSMauro Carvalho Chehab int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input); 949*0c0d06caSMauro Carvalho Chehab int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev); 950*0c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_input(struct cx231xx *dev, u8 input); 951*0c0d06caSMauro Carvalho Chehab 952*0c0d06caSMauro Carvalho Chehab /* Provided by cx231xx-video.c */ 953*0c0d06caSMauro Carvalho Chehab int cx231xx_register_extension(struct cx231xx_ops *dev); 954*0c0d06caSMauro Carvalho Chehab void cx231xx_unregister_extension(struct cx231xx_ops *dev); 955*0c0d06caSMauro Carvalho Chehab void cx231xx_init_extension(struct cx231xx *dev); 956*0c0d06caSMauro Carvalho Chehab void cx231xx_close_extension(struct cx231xx *dev); 957*0c0d06caSMauro Carvalho Chehab 958*0c0d06caSMauro Carvalho Chehab /* Provided by cx231xx-cards.c */ 959*0c0d06caSMauro Carvalho Chehab extern void cx231xx_pre_card_setup(struct cx231xx *dev); 960*0c0d06caSMauro Carvalho Chehab extern void cx231xx_card_setup(struct cx231xx *dev); 961*0c0d06caSMauro Carvalho Chehab extern struct cx231xx_board cx231xx_boards[]; 962*0c0d06caSMauro Carvalho Chehab extern struct usb_device_id cx231xx_id_table[]; 963*0c0d06caSMauro Carvalho Chehab extern const unsigned int cx231xx_bcount; 964*0c0d06caSMauro Carvalho Chehab int cx231xx_tuner_callback(void *ptr, int component, int command, int arg); 965*0c0d06caSMauro Carvalho Chehab 966*0c0d06caSMauro Carvalho Chehab /* cx23885-417.c */ 967*0c0d06caSMauro Carvalho Chehab extern int cx231xx_417_register(struct cx231xx *dev); 968*0c0d06caSMauro Carvalho Chehab extern void cx231xx_417_unregister(struct cx231xx *dev); 969*0c0d06caSMauro Carvalho Chehab 970*0c0d06caSMauro Carvalho Chehab /* cx23885-input.c */ 971*0c0d06caSMauro Carvalho Chehab 972*0c0d06caSMauro Carvalho Chehab #if defined(CONFIG_VIDEO_CX231XX_RC) 973*0c0d06caSMauro Carvalho Chehab int cx231xx_ir_init(struct cx231xx *dev); 974*0c0d06caSMauro Carvalho Chehab void cx231xx_ir_exit(struct cx231xx *dev); 975*0c0d06caSMauro Carvalho Chehab #else 976*0c0d06caSMauro Carvalho Chehab #define cx231xx_ir_init(dev) (0) 977*0c0d06caSMauro Carvalho Chehab #define cx231xx_ir_exit(dev) (0) 978*0c0d06caSMauro Carvalho Chehab #endif 979*0c0d06caSMauro Carvalho Chehab 980*0c0d06caSMauro Carvalho Chehab 981*0c0d06caSMauro Carvalho Chehab /* printk macros */ 982*0c0d06caSMauro Carvalho Chehab 983*0c0d06caSMauro Carvalho Chehab #define cx231xx_err(fmt, arg...) do {\ 984*0c0d06caSMauro Carvalho Chehab printk(KERN_ERR fmt , ##arg); } while (0) 985*0c0d06caSMauro Carvalho Chehab 986*0c0d06caSMauro Carvalho Chehab #define cx231xx_errdev(fmt, arg...) do {\ 987*0c0d06caSMauro Carvalho Chehab printk(KERN_ERR "%s: "fmt,\ 988*0c0d06caSMauro Carvalho Chehab dev->name , ##arg); } while (0) 989*0c0d06caSMauro Carvalho Chehab 990*0c0d06caSMauro Carvalho Chehab #define cx231xx_info(fmt, arg...) do {\ 991*0c0d06caSMauro Carvalho Chehab printk(KERN_INFO "%s: "fmt,\ 992*0c0d06caSMauro Carvalho Chehab dev->name , ##arg); } while (0) 993*0c0d06caSMauro Carvalho Chehab #define cx231xx_warn(fmt, arg...) do {\ 994*0c0d06caSMauro Carvalho Chehab printk(KERN_WARNING "%s: "fmt,\ 995*0c0d06caSMauro Carvalho Chehab dev->name , ##arg); } while (0) 996*0c0d06caSMauro Carvalho Chehab 997*0c0d06caSMauro Carvalho Chehab static inline unsigned int norm_maxw(struct cx231xx *dev) 998*0c0d06caSMauro Carvalho Chehab { 999*0c0d06caSMauro Carvalho Chehab if (dev->board.max_range_640_480) 1000*0c0d06caSMauro Carvalho Chehab return 640; 1001*0c0d06caSMauro Carvalho Chehab else 1002*0c0d06caSMauro Carvalho Chehab return 720; 1003*0c0d06caSMauro Carvalho Chehab } 1004*0c0d06caSMauro Carvalho Chehab 1005*0c0d06caSMauro Carvalho Chehab static inline unsigned int norm_maxh(struct cx231xx *dev) 1006*0c0d06caSMauro Carvalho Chehab { 1007*0c0d06caSMauro Carvalho Chehab if (dev->board.max_range_640_480) 1008*0c0d06caSMauro Carvalho Chehab return 480; 1009*0c0d06caSMauro Carvalho Chehab else 1010*0c0d06caSMauro Carvalho Chehab return (dev->norm & V4L2_STD_625_50) ? 576 : 480; 1011*0c0d06caSMauro Carvalho Chehab } 1012*0c0d06caSMauro Carvalho Chehab #endif 1013