1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Hantro VPU codec driver 4 * 5 * Copyright 2018 Google LLC. 6 * Tomasz Figa <tfiga@chromium.org> 7 */ 8 9 #ifndef HANTRO_HW_H_ 10 #define HANTRO_HW_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/v4l2-controls.h> 14 #include <media/v4l2-ctrls.h> 15 #include <media/v4l2-vp9.h> 16 #include <media/videobuf2-core.h> 17 18 #include "rockchip_av1_entropymode.h" 19 20 #define DEC_8190_ALIGN_MASK 0x07U 21 22 #define MB_DIM 16 23 #define TILE_MB_DIM 4 24 #define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM) 25 #define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM) 26 27 #define FMT_MIN_WIDTH 48 28 #define FMT_MIN_HEIGHT 48 29 #define FMT_HD_WIDTH 1280 30 #define FMT_HD_HEIGHT 720 31 #define FMT_FHD_WIDTH 1920 32 #define FMT_FHD_HEIGHT 1088 33 #define FMT_UHD_WIDTH 3840 34 #define FMT_UHD_HEIGHT 2160 35 #define FMT_4K_WIDTH 4096 36 #define FMT_4K_HEIGHT 2304 37 38 #define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1) 39 40 struct hantro_dev; 41 struct hantro_ctx; 42 struct hantro_buf; 43 struct hantro_variant; 44 45 /** 46 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data 47 * 48 * @cpu: CPU pointer to the buffer. 49 * @dma: DMA address of the buffer. 50 * @size: Size of the buffer. 51 * @attrs: Attributes of the DMA mapping. 52 */ 53 struct hantro_aux_buf { 54 void *cpu; 55 dma_addr_t dma; 56 size_t size; 57 unsigned long attrs; 58 }; 59 60 /* Max. number of entries in the DPB (HW limitation). */ 61 #define HANTRO_H264_DPB_SIZE 16 62 63 /** 64 * struct hantro_h264_dec_ctrls 65 * 66 * @decode: Decode params 67 * @scaling: Scaling info 68 * @sps: SPS info 69 * @pps: PPS info 70 */ 71 struct hantro_h264_dec_ctrls { 72 const struct v4l2_ctrl_h264_decode_params *decode; 73 const struct v4l2_ctrl_h264_scaling_matrix *scaling; 74 const struct v4l2_ctrl_h264_sps *sps; 75 const struct v4l2_ctrl_h264_pps *pps; 76 }; 77 78 /** 79 * struct hantro_h264_dec_reflists 80 * 81 * @p: P reflist 82 * @b0: B0 reflist 83 * @b1: B1 reflist 84 */ 85 struct hantro_h264_dec_reflists { 86 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; 87 struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; 88 struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; 89 }; 90 91 /** 92 * struct hantro_h264_dec_hw_ctx 93 * 94 * @priv: Private auxiliary buffer for hardware. 95 * @dpb: DPB 96 * @reflists: P/B0/B1 reflists 97 * @ctrls: V4L2 controls attached to a run 98 * @dpb_longterm: DPB long-term 99 * @dpb_valid: DPB valid 100 * @cur_poc: Current picture order count 101 */ 102 struct hantro_h264_dec_hw_ctx { 103 struct hantro_aux_buf priv; 104 struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; 105 struct hantro_h264_dec_reflists reflists; 106 struct hantro_h264_dec_ctrls ctrls; 107 u32 dpb_longterm; 108 u32 dpb_valid; 109 s32 cur_poc; 110 }; 111 112 /** 113 * struct hantro_hevc_dec_ctrls 114 * @decode_params: Decode params 115 * @scaling: Scaling matrix 116 * @sps: SPS info 117 * @pps: PPS info 118 * @hevc_hdr_skip_length: the number of data (in bits) to skip in the 119 * slice segment header syntax after 'slice type' 120 * token 121 */ 122 struct hantro_hevc_dec_ctrls { 123 const struct v4l2_ctrl_hevc_decode_params *decode_params; 124 const struct v4l2_ctrl_hevc_scaling_matrix *scaling; 125 const struct v4l2_ctrl_hevc_sps *sps; 126 const struct v4l2_ctrl_hevc_pps *pps; 127 u32 hevc_hdr_skip_length; 128 }; 129 130 /** 131 * struct hantro_hevc_dec_hw_ctx 132 * @tile_sizes: Tile sizes buffer 133 * @tile_filter: Tile vertical filter buffer 134 * @tile_sao: Tile SAO buffer 135 * @tile_bsd: Tile BSD control buffer 136 * @ref_bufs: Internal reference buffers 137 * @scaling_lists: Scaling lists buffer 138 * @ref_bufs_poc: Internal reference buffers picture order count 139 * @ref_bufs_used: Bitfield of used reference buffers 140 * @ctrls: V4L2 controls attached to a run 141 * @num_tile_cols_allocated: number of allocated tiles 142 */ 143 struct hantro_hevc_dec_hw_ctx { 144 struct hantro_aux_buf tile_sizes; 145 struct hantro_aux_buf tile_filter; 146 struct hantro_aux_buf tile_sao; 147 struct hantro_aux_buf tile_bsd; 148 struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES]; 149 struct hantro_aux_buf scaling_lists; 150 s32 ref_bufs_poc[NUM_REF_PICTURES]; 151 u32 ref_bufs_used; 152 struct hantro_hevc_dec_ctrls ctrls; 153 unsigned int num_tile_cols_allocated; 154 }; 155 156 /** 157 * struct hantro_mpeg2_dec_hw_ctx 158 * 159 * @qtable: Quantization table 160 */ 161 struct hantro_mpeg2_dec_hw_ctx { 162 struct hantro_aux_buf qtable; 163 }; 164 165 /** 166 * struct hantro_vp8_dec_hw_ctx 167 * 168 * @segment_map: Segment map buffer. 169 * @prob_tbl: Probability table buffer. 170 */ 171 struct hantro_vp8_dec_hw_ctx { 172 struct hantro_aux_buf segment_map; 173 struct hantro_aux_buf prob_tbl; 174 }; 175 176 /** 177 * struct hantro_vp9_frame_info 178 * 179 * @valid: frame info valid flag 180 * @frame_context_idx: index of frame context 181 * @reference_mode: inter prediction type 182 * @tx_mode: transform mode 183 * @interpolation_filter: filter selection for inter prediction 184 * @flags: frame flags 185 * @timestamp: frame timestamp 186 */ 187 struct hantro_vp9_frame_info { 188 u32 valid : 1; 189 u32 frame_context_idx : 2; 190 u32 reference_mode : 2; 191 u32 tx_mode : 3; 192 u32 interpolation_filter : 3; 193 u32 flags; 194 u64 timestamp; 195 }; 196 197 #define MAX_SB_COLS 64 198 #define MAX_SB_ROWS 34 199 200 /** 201 * struct hantro_vp9_dec_hw_ctx 202 * 203 * @tile_edge: auxiliary DMA buffer for tile edge processing 204 * @segment_map: auxiliary DMA buffer for segment map 205 * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters 206 * @cnts: vp9 library struct for abstracting hw counters access 207 * @probability_tables: VP9 probability tables implied by the spec 208 * @frame_context: VP9 frame contexts 209 * @cur: current frame information 210 * @last: last frame information 211 * @bsd_ctrl_offset: bsd offset into tile_edge 212 * @segment_map_size: size of segment map 213 * @ctx_counters_offset: hw counters offset into misc 214 * @tile_info_offset: tile info offset into misc 215 * @tile_r_info: per-tile information array 216 * @tile_c_info: per-tile information array 217 * @last_tile_r: last number of tile rows 218 * @last_tile_c: last number of tile cols 219 * @last_sbs_r: last number of superblock rows 220 * @last_sbs_c: last number of superblock cols 221 * @active_segment: number of active segment (alternating between 0 and 1) 222 * @feature_enabled: segmentation feature enabled flags 223 * @feature_data: segmentation feature data 224 */ 225 struct hantro_vp9_dec_hw_ctx { 226 struct hantro_aux_buf tile_edge; 227 struct hantro_aux_buf segment_map; 228 struct hantro_aux_buf misc; 229 struct v4l2_vp9_frame_symbol_counts cnts; 230 struct v4l2_vp9_frame_context probability_tables; 231 struct v4l2_vp9_frame_context frame_context[4]; 232 struct hantro_vp9_frame_info cur; 233 struct hantro_vp9_frame_info last; 234 235 unsigned int bsd_ctrl_offset; 236 unsigned int segment_map_size; 237 unsigned int ctx_counters_offset; 238 unsigned int tile_info_offset; 239 240 unsigned short tile_r_info[MAX_SB_ROWS]; 241 unsigned short tile_c_info[MAX_SB_COLS]; 242 unsigned int last_tile_r; 243 unsigned int last_tile_c; 244 unsigned int last_sbs_r; 245 unsigned int last_sbs_c; 246 247 unsigned int active_segment; 248 u8 feature_enabled[8]; 249 s16 feature_data[8][4]; 250 }; 251 252 /** 253 * hantro_av1_dec_hw_ctx 254 * @cdfs: current probabilities structure 255 * @cdfs_ndvc: current mv probabilities structure 256 * @default_cdfs: default probabilities structure 257 * @default_cdfs_ndvc: default mv probabilties structure 258 * @cdfs_last: stored probabilities structures 259 * @cdfs_last_ndvc: stored mv probabilities structures 260 */ 261 struct hantro_av1_dec_hw_ctx { 262 struct av1cdfs *cdfs; 263 struct mvcdfs *cdfs_ndvc; 264 struct av1cdfs default_cdfs; 265 struct mvcdfs default_cdfs_ndvc; 266 struct av1cdfs cdfs_last[NUM_REF_FRAMES]; 267 struct mvcdfs cdfs_last_ndvc[NUM_REF_FRAMES]; 268 }; 269 270 /** 271 * struct hantro_postproc_ctx 272 * 273 * @dec_q: References buffers, in decoder format. 274 */ 275 struct hantro_postproc_ctx { 276 struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; 277 }; 278 279 /** 280 * struct hantro_postproc_ops - post-processor operations 281 * 282 * @enable: Enable the post-processor block. Optional. 283 * @disable: Disable the post-processor block. Optional. 284 * @enum_framesizes: Enumerate possible scaled output formats. 285 * Returns zero if OK, a negative value in error cases. 286 * Optional. 287 */ 288 struct hantro_postproc_ops { 289 void (*enable)(struct hantro_ctx *ctx); 290 void (*disable)(struct hantro_ctx *ctx); 291 int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize); 292 }; 293 294 /** 295 * struct hantro_codec_ops - codec mode specific operations 296 * 297 * @init: If needed, can be used for initialization. 298 * Optional and called from process context. 299 * @exit: If needed, can be used to undo the .init phase. 300 * Optional and called from process context. 301 * @run: Start single {en,de)coding job. Called from atomic context 302 * to indicate that a pair of buffers is ready and the hardware 303 * should be programmed and started. Returns zero if OK, a 304 * negative value in error cases. 305 * @done: Read back processing results and additional data from hardware. 306 * @reset: Reset the hardware in case of a timeout. 307 */ 308 struct hantro_codec_ops { 309 int (*init)(struct hantro_ctx *ctx); 310 void (*exit)(struct hantro_ctx *ctx); 311 int (*run)(struct hantro_ctx *ctx); 312 void (*done)(struct hantro_ctx *ctx); 313 void (*reset)(struct hantro_ctx *ctx); 314 }; 315 316 /** 317 * enum hantro_enc_fmt - source format ID for hardware registers. 318 * 319 * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format 320 * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format 321 * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV) 322 * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY) 323 */ 324 enum hantro_enc_fmt { 325 ROCKCHIP_VPU_ENC_FMT_YUV420P = 0, 326 ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1, 327 ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2, 328 ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, 329 }; 330 331 extern const struct hantro_variant imx8mm_vpu_g1_variant; 332 extern const struct hantro_variant imx8mq_vpu_g1_variant; 333 extern const struct hantro_variant imx8mq_vpu_g2_variant; 334 extern const struct hantro_variant imx8mq_vpu_variant; 335 extern const struct hantro_variant px30_vpu_variant; 336 extern const struct hantro_variant rk3036_vpu_variant; 337 extern const struct hantro_variant rk3066_vpu_variant; 338 extern const struct hantro_variant rk3288_vpu_variant; 339 extern const struct hantro_variant rk3328_vpu_variant; 340 extern const struct hantro_variant rk3399_vpu_variant; 341 extern const struct hantro_variant rk3568_vepu_variant; 342 extern const struct hantro_variant rk3568_vpu_variant; 343 extern const struct hantro_variant sama5d4_vdec_variant; 344 extern const struct hantro_variant sunxi_vpu_variant; 345 346 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; 347 extern const struct hantro_postproc_ops hantro_g2_postproc_ops; 348 349 extern const u32 hantro_vp8_dec_mc_filter[8][6]; 350 351 void hantro_watchdog(struct work_struct *work); 352 void hantro_run(struct hantro_ctx *ctx); 353 void hantro_irq_done(struct hantro_dev *vpu, 354 enum vb2_buffer_state result); 355 void hantro_start_prepare_run(struct hantro_ctx *ctx); 356 void hantro_end_prepare_run(struct hantro_ctx *ctx); 357 358 irqreturn_t hantro_g1_irq(int irq, void *dev_id); 359 void hantro_g1_reset(struct hantro_ctx *ctx); 360 361 int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx); 362 int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx); 363 void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx); 364 void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx); 365 366 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, 367 unsigned int dpb_idx); 368 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, 369 unsigned int dpb_idx); 370 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); 371 int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); 372 int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); 373 int hantro_h264_dec_init(struct hantro_ctx *ctx); 374 void hantro_h264_dec_exit(struct hantro_ctx *ctx); 375 376 int hantro_hevc_dec_init(struct hantro_ctx *ctx); 377 void hantro_hevc_dec_exit(struct hantro_ctx *ctx); 378 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx); 379 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); 380 void hantro_hevc_ref_init(struct hantro_ctx *ctx); 381 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc); 382 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); 383 384 385 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) 386 { 387 return (dimension + 63) / 64; 388 } 389 390 static inline size_t 391 hantro_vp9_mv_size(unsigned int width, unsigned int height) 392 { 393 int num_ctbs; 394 395 /* 396 * There can be up to (CTBs x 64) number of blocks, 397 * and the motion vector for each block needs 16 bytes. 398 */ 399 num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); 400 return (num_ctbs * 64) * 16; 401 } 402 403 static inline size_t 404 hantro_h264_mv_size(unsigned int width, unsigned int height) 405 { 406 /* 407 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to 408 * 448 bytes per macroblock with additional 32 bytes on 409 * multi-core variants. 410 * 411 * The H264 decoder needs extra space on the output buffers 412 * to store motion vectors. This is needed for reference 413 * frames and only if the format is non-post-processed NV12. 414 * 415 * Memory layout is as follow: 416 * 417 * +---------------------------+ 418 * | Y-plane 256 bytes x MBs | 419 * +---------------------------+ 420 * | UV-plane 128 bytes x MBs | 421 * +---------------------------+ 422 * | MV buffer 64 bytes x MBs | 423 * +---------------------------+ 424 * | MC sync 32 bytes | 425 * +---------------------------+ 426 */ 427 return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32; 428 } 429 430 static inline size_t 431 hantro_hevc_mv_size(unsigned int width, unsigned int height) 432 { 433 /* 434 * A CTB can be 64x64, 32x32 or 16x16. 435 * Allocated memory for the "worse" case: 16x16 436 */ 437 return width * height / 16; 438 } 439 440 static inline unsigned short hantro_av1_num_sbs(unsigned short dimension) 441 { 442 return DIV_ROUND_UP(dimension, 64); 443 } 444 445 static inline size_t 446 hantro_av1_mv_size(unsigned int width, unsigned int height) 447 { 448 size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height); 449 450 return ALIGN(num_sbs * 384, 16) * 2 + 512; 451 } 452 453 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); 454 int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); 455 void hantro_mpeg2_dec_copy_qtable(u8 *qtable, 456 const struct v4l2_ctrl_mpeg2_quantisation *ctrl); 457 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx); 458 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx); 459 460 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx); 461 int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx); 462 int hantro_vp8_dec_init(struct hantro_ctx *ctx); 463 void hantro_vp8_dec_exit(struct hantro_ctx *ctx); 464 void hantro_vp8_prob_update(struct hantro_ctx *ctx, 465 const struct v4l2_ctrl_vp8_frame *hdr); 466 467 int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); 468 void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); 469 int hantro_vp9_dec_init(struct hantro_ctx *ctx); 470 void hantro_vp9_dec_exit(struct hantro_ctx *ctx); 471 void hantro_g2_check_idle(struct hantro_dev *vpu); 472 irqreturn_t hantro_g2_irq(int irq, void *dev_id); 473 474 #endif /* HANTRO_HW_H_ */ 475