1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Hantro VPU codec driver 4 * 5 * Copyright 2018 Google LLC. 6 * Tomasz Figa <tfiga@chromium.org> 7 */ 8 9 #ifndef HANTRO_HW_H_ 10 #define HANTRO_HW_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/v4l2-controls.h> 14 #include <media/v4l2-ctrls.h> 15 #include <media/v4l2-vp9.h> 16 #include <media/videobuf2-core.h> 17 18 #include "rockchip_av1_entropymode.h" 19 20 #define DEC_8190_ALIGN_MASK 0x07U 21 22 #define MB_DIM 16 23 #define TILE_MB_DIM 4 24 #define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM) 25 #define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM) 26 27 #define FMT_MIN_WIDTH 48 28 #define FMT_MIN_HEIGHT 48 29 #define FMT_HD_WIDTH 1280 30 #define FMT_HD_HEIGHT 720 31 #define FMT_FHD_WIDTH 1920 32 #define FMT_FHD_HEIGHT 1088 33 #define FMT_UHD_WIDTH 3840 34 #define FMT_UHD_HEIGHT 2160 35 #define FMT_4K_WIDTH 4096 36 #define FMT_4K_HEIGHT 2304 37 38 #define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1) 39 40 #define AV1_MAX_FRAME_BUF_COUNT (V4L2_AV1_TOTAL_REFS_PER_FRAME + 1) 41 42 struct hantro_dev; 43 struct hantro_ctx; 44 struct hantro_buf; 45 struct hantro_variant; 46 47 /** 48 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data 49 * 50 * @cpu: CPU pointer to the buffer. 51 * @dma: DMA address of the buffer. 52 * @size: Size of the buffer. 53 * @attrs: Attributes of the DMA mapping. 54 */ 55 struct hantro_aux_buf { 56 void *cpu; 57 dma_addr_t dma; 58 size_t size; 59 unsigned long attrs; 60 }; 61 62 /* Max. number of entries in the DPB (HW limitation). */ 63 #define HANTRO_H264_DPB_SIZE 16 64 65 /** 66 * struct hantro_h264_dec_ctrls 67 * 68 * @decode: Decode params 69 * @scaling: Scaling info 70 * @sps: SPS info 71 * @pps: PPS info 72 */ 73 struct hantro_h264_dec_ctrls { 74 const struct v4l2_ctrl_h264_decode_params *decode; 75 const struct v4l2_ctrl_h264_scaling_matrix *scaling; 76 const struct v4l2_ctrl_h264_sps *sps; 77 const struct v4l2_ctrl_h264_pps *pps; 78 }; 79 80 /** 81 * struct hantro_h264_dec_reflists 82 * 83 * @p: P reflist 84 * @b0: B0 reflist 85 * @b1: B1 reflist 86 */ 87 struct hantro_h264_dec_reflists { 88 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; 89 struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; 90 struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; 91 }; 92 93 /** 94 * struct hantro_h264_dec_hw_ctx 95 * 96 * @priv: Private auxiliary buffer for hardware. 97 * @dpb: DPB 98 * @reflists: P/B0/B1 reflists 99 * @ctrls: V4L2 controls attached to a run 100 * @dpb_longterm: DPB long-term 101 * @dpb_valid: DPB valid 102 * @cur_poc: Current picture order count 103 */ 104 struct hantro_h264_dec_hw_ctx { 105 struct hantro_aux_buf priv; 106 struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; 107 struct hantro_h264_dec_reflists reflists; 108 struct hantro_h264_dec_ctrls ctrls; 109 u32 dpb_longterm; 110 u32 dpb_valid; 111 s32 cur_poc; 112 }; 113 114 /** 115 * struct hantro_hevc_dec_ctrls 116 * @decode_params: Decode params 117 * @scaling: Scaling matrix 118 * @sps: SPS info 119 * @pps: PPS info 120 * @hevc_hdr_skip_length: the number of data (in bits) to skip in the 121 * slice segment header syntax after 'slice type' 122 * token 123 */ 124 struct hantro_hevc_dec_ctrls { 125 const struct v4l2_ctrl_hevc_decode_params *decode_params; 126 const struct v4l2_ctrl_hevc_scaling_matrix *scaling; 127 const struct v4l2_ctrl_hevc_sps *sps; 128 const struct v4l2_ctrl_hevc_pps *pps; 129 u32 hevc_hdr_skip_length; 130 }; 131 132 /** 133 * struct hantro_hevc_dec_hw_ctx 134 * @tile_sizes: Tile sizes buffer 135 * @tile_filter: Tile vertical filter buffer 136 * @tile_sao: Tile SAO buffer 137 * @tile_bsd: Tile BSD control buffer 138 * @ref_bufs: Internal reference buffers 139 * @scaling_lists: Scaling lists buffer 140 * @ref_bufs_poc: Internal reference buffers picture order count 141 * @ref_bufs_used: Bitfield of used reference buffers 142 * @ctrls: V4L2 controls attached to a run 143 * @num_tile_cols_allocated: number of allocated tiles 144 */ 145 struct hantro_hevc_dec_hw_ctx { 146 struct hantro_aux_buf tile_sizes; 147 struct hantro_aux_buf tile_filter; 148 struct hantro_aux_buf tile_sao; 149 struct hantro_aux_buf tile_bsd; 150 struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES]; 151 struct hantro_aux_buf scaling_lists; 152 s32 ref_bufs_poc[NUM_REF_PICTURES]; 153 u32 ref_bufs_used; 154 struct hantro_hevc_dec_ctrls ctrls; 155 unsigned int num_tile_cols_allocated; 156 }; 157 158 /** 159 * struct hantro_mpeg2_dec_hw_ctx 160 * 161 * @qtable: Quantization table 162 */ 163 struct hantro_mpeg2_dec_hw_ctx { 164 struct hantro_aux_buf qtable; 165 }; 166 167 /** 168 * struct hantro_vp8_dec_hw_ctx 169 * 170 * @segment_map: Segment map buffer. 171 * @prob_tbl: Probability table buffer. 172 */ 173 struct hantro_vp8_dec_hw_ctx { 174 struct hantro_aux_buf segment_map; 175 struct hantro_aux_buf prob_tbl; 176 }; 177 178 /** 179 * struct hantro_vp9_frame_info 180 * 181 * @valid: frame info valid flag 182 * @frame_context_idx: index of frame context 183 * @reference_mode: inter prediction type 184 * @tx_mode: transform mode 185 * @interpolation_filter: filter selection for inter prediction 186 * @flags: frame flags 187 * @timestamp: frame timestamp 188 */ 189 struct hantro_vp9_frame_info { 190 u32 valid : 1; 191 u32 frame_context_idx : 2; 192 u32 reference_mode : 2; 193 u32 tx_mode : 3; 194 u32 interpolation_filter : 3; 195 u32 flags; 196 u64 timestamp; 197 }; 198 199 #define MAX_SB_COLS 64 200 #define MAX_SB_ROWS 34 201 202 /** 203 * struct hantro_vp9_dec_hw_ctx 204 * 205 * @tile_edge: auxiliary DMA buffer for tile edge processing 206 * @segment_map: auxiliary DMA buffer for segment map 207 * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters 208 * @cnts: vp9 library struct for abstracting hw counters access 209 * @probability_tables: VP9 probability tables implied by the spec 210 * @frame_context: VP9 frame contexts 211 * @cur: current frame information 212 * @last: last frame information 213 * @bsd_ctrl_offset: bsd offset into tile_edge 214 * @segment_map_size: size of segment map 215 * @ctx_counters_offset: hw counters offset into misc 216 * @tile_info_offset: tile info offset into misc 217 * @tile_r_info: per-tile information array 218 * @tile_c_info: per-tile information array 219 * @last_tile_r: last number of tile rows 220 * @last_tile_c: last number of tile cols 221 * @last_sbs_r: last number of superblock rows 222 * @last_sbs_c: last number of superblock cols 223 * @active_segment: number of active segment (alternating between 0 and 1) 224 * @feature_enabled: segmentation feature enabled flags 225 * @feature_data: segmentation feature data 226 */ 227 struct hantro_vp9_dec_hw_ctx { 228 struct hantro_aux_buf tile_edge; 229 struct hantro_aux_buf segment_map; 230 struct hantro_aux_buf misc; 231 struct v4l2_vp9_frame_symbol_counts cnts; 232 struct v4l2_vp9_frame_context probability_tables; 233 struct v4l2_vp9_frame_context frame_context[4]; 234 struct hantro_vp9_frame_info cur; 235 struct hantro_vp9_frame_info last; 236 237 unsigned int bsd_ctrl_offset; 238 unsigned int segment_map_size; 239 unsigned int ctx_counters_offset; 240 unsigned int tile_info_offset; 241 242 unsigned short tile_r_info[MAX_SB_ROWS]; 243 unsigned short tile_c_info[MAX_SB_COLS]; 244 unsigned int last_tile_r; 245 unsigned int last_tile_c; 246 unsigned int last_sbs_r; 247 unsigned int last_sbs_c; 248 249 unsigned int active_segment; 250 u8 feature_enabled[8]; 251 s16 feature_data[8][4]; 252 }; 253 254 /** 255 * struct hantro_av1_dec_ctrls 256 * @sequence: AV1 Sequence 257 * @tile_group_entry: AV1 Tile Group entry 258 * @frame: AV1 Frame Header OBU 259 * @film_grain: AV1 Film Grain 260 */ 261 struct hantro_av1_dec_ctrls { 262 const struct v4l2_ctrl_av1_sequence *sequence; 263 const struct v4l2_ctrl_av1_tile_group_entry *tile_group_entry; 264 const struct v4l2_ctrl_av1_frame *frame; 265 const struct v4l2_ctrl_av1_film_grain *film_grain; 266 }; 267 268 struct hantro_av1_frame_ref { 269 int width; 270 int height; 271 int mi_cols; 272 int mi_rows; 273 u64 timestamp; 274 enum v4l2_av1_frame_type frame_type; 275 bool used; 276 u32 order_hint; 277 u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME]; 278 struct vb2_v4l2_buffer *vb2_ref; 279 }; 280 281 /** 282 * struct hantro_av1_dec_hw_ctx 283 * @db_data_col: db tile col data buffer 284 * @db_ctrl_col: db tile col ctrl buffer 285 * @cdef_col: cdef tile col buffer 286 * @sr_col: sr tile col buffer 287 * @lr_col: lr tile col buffer 288 * @global_model: global model buffer 289 * @tile_info: tile info buffer 290 * @segment: segmentation info buffer 291 * @prob_tbl: probability table 292 * @prob_tbl_out: probability table output 293 * @tile_buf: tile buffer 294 * @ctrls: V4L2 controls attached to a run 295 * @frame_refs: reference frames info slots 296 * @ref_frame_sign_bias: array of sign bias 297 * @num_tile_cols_allocated: number of allocated tiles 298 * @cdfs: current probabilities structure 299 * @cdfs_ndvc: current mv probabilities structure 300 * @default_cdfs: default probabilities structure 301 * @default_cdfs_ndvc: default mv probabilties structure 302 * @cdfs_last: stored probabilities structures 303 * @cdfs_last_ndvc: stored mv probabilities structures 304 * @current_frame_index: index of the current in frame_refs array 305 */ 306 struct hantro_av1_dec_hw_ctx { 307 struct hantro_aux_buf db_data_col; 308 struct hantro_aux_buf db_ctrl_col; 309 struct hantro_aux_buf cdef_col; 310 struct hantro_aux_buf sr_col; 311 struct hantro_aux_buf lr_col; 312 struct hantro_aux_buf global_model; 313 struct hantro_aux_buf tile_info; 314 struct hantro_aux_buf segment; 315 struct hantro_aux_buf prob_tbl; 316 struct hantro_aux_buf prob_tbl_out; 317 struct hantro_aux_buf tile_buf; 318 struct hantro_av1_dec_ctrls ctrls; 319 struct hantro_av1_frame_ref frame_refs[AV1_MAX_FRAME_BUF_COUNT]; 320 u32 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME]; 321 unsigned int num_tile_cols_allocated; 322 struct av1cdfs *cdfs; 323 struct mvcdfs *cdfs_ndvc; 324 struct av1cdfs default_cdfs; 325 struct mvcdfs default_cdfs_ndvc; 326 struct av1cdfs cdfs_last[NUM_REF_FRAMES]; 327 struct mvcdfs cdfs_last_ndvc[NUM_REF_FRAMES]; 328 int current_frame_index; 329 }; 330 /** 331 * struct hantro_postproc_ctx 332 * 333 * @dec_q: References buffers, in decoder format. 334 */ 335 struct hantro_postproc_ctx { 336 struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; 337 }; 338 339 /** 340 * struct hantro_postproc_ops - post-processor operations 341 * 342 * @enable: Enable the post-processor block. Optional. 343 * @disable: Disable the post-processor block. Optional. 344 * @enum_framesizes: Enumerate possible scaled output formats. 345 * Returns zero if OK, a negative value in error cases. 346 * Optional. 347 */ 348 struct hantro_postproc_ops { 349 void (*enable)(struct hantro_ctx *ctx); 350 void (*disable)(struct hantro_ctx *ctx); 351 int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize); 352 }; 353 354 /** 355 * struct hantro_codec_ops - codec mode specific operations 356 * 357 * @init: If needed, can be used for initialization. 358 * Optional and called from process context. 359 * @exit: If needed, can be used to undo the .init phase. 360 * Optional and called from process context. 361 * @run: Start single {en,de)coding job. Called from atomic context 362 * to indicate that a pair of buffers is ready and the hardware 363 * should be programmed and started. Returns zero if OK, a 364 * negative value in error cases. 365 * @done: Read back processing results and additional data from hardware. 366 * @reset: Reset the hardware in case of a timeout. 367 */ 368 struct hantro_codec_ops { 369 int (*init)(struct hantro_ctx *ctx); 370 void (*exit)(struct hantro_ctx *ctx); 371 int (*run)(struct hantro_ctx *ctx); 372 void (*done)(struct hantro_ctx *ctx); 373 void (*reset)(struct hantro_ctx *ctx); 374 }; 375 376 /** 377 * enum hantro_enc_fmt - source format ID for hardware registers. 378 * 379 * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format 380 * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format 381 * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV) 382 * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY) 383 */ 384 enum hantro_enc_fmt { 385 ROCKCHIP_VPU_ENC_FMT_YUV420P = 0, 386 ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1, 387 ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2, 388 ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, 389 }; 390 391 extern const struct hantro_variant imx8mm_vpu_g1_variant; 392 extern const struct hantro_variant imx8mq_vpu_g1_variant; 393 extern const struct hantro_variant imx8mq_vpu_g2_variant; 394 extern const struct hantro_variant imx8mq_vpu_variant; 395 extern const struct hantro_variant px30_vpu_variant; 396 extern const struct hantro_variant rk3036_vpu_variant; 397 extern const struct hantro_variant rk3066_vpu_variant; 398 extern const struct hantro_variant rk3288_vpu_variant; 399 extern const struct hantro_variant rk3328_vpu_variant; 400 extern const struct hantro_variant rk3399_vpu_variant; 401 extern const struct hantro_variant rk3568_vepu_variant; 402 extern const struct hantro_variant rk3568_vpu_variant; 403 extern const struct hantro_variant sama5d4_vdec_variant; 404 extern const struct hantro_variant sunxi_vpu_variant; 405 406 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; 407 extern const struct hantro_postproc_ops hantro_g2_postproc_ops; 408 409 extern const u32 hantro_vp8_dec_mc_filter[8][6]; 410 411 void hantro_watchdog(struct work_struct *work); 412 void hantro_run(struct hantro_ctx *ctx); 413 void hantro_irq_done(struct hantro_dev *vpu, 414 enum vb2_buffer_state result); 415 void hantro_start_prepare_run(struct hantro_ctx *ctx); 416 void hantro_end_prepare_run(struct hantro_ctx *ctx); 417 418 irqreturn_t hantro_g1_irq(int irq, void *dev_id); 419 void hantro_g1_reset(struct hantro_ctx *ctx); 420 421 int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx); 422 int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx); 423 void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx); 424 void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx); 425 426 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, 427 unsigned int dpb_idx); 428 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, 429 unsigned int dpb_idx); 430 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); 431 int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); 432 int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); 433 int hantro_h264_dec_init(struct hantro_ctx *ctx); 434 void hantro_h264_dec_exit(struct hantro_ctx *ctx); 435 436 int hantro_hevc_dec_init(struct hantro_ctx *ctx); 437 void hantro_hevc_dec_exit(struct hantro_ctx *ctx); 438 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx); 439 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); 440 void hantro_hevc_ref_init(struct hantro_ctx *ctx); 441 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc); 442 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); 443 444 int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx); 445 void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx); 446 int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx); 447 void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx); 448 449 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) 450 { 451 return (dimension + 63) / 64; 452 } 453 454 static inline size_t 455 hantro_vp9_mv_size(unsigned int width, unsigned int height) 456 { 457 int num_ctbs; 458 459 /* 460 * There can be up to (CTBs x 64) number of blocks, 461 * and the motion vector for each block needs 16 bytes. 462 */ 463 num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); 464 return (num_ctbs * 64) * 16; 465 } 466 467 static inline size_t 468 hantro_h264_mv_size(unsigned int width, unsigned int height) 469 { 470 /* 471 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to 472 * 448 bytes per macroblock with additional 32 bytes on 473 * multi-core variants. 474 * 475 * The H264 decoder needs extra space on the output buffers 476 * to store motion vectors. This is needed for reference 477 * frames and only if the format is non-post-processed NV12. 478 * 479 * Memory layout is as follow: 480 * 481 * +---------------------------+ 482 * | Y-plane 256 bytes x MBs | 483 * +---------------------------+ 484 * | UV-plane 128 bytes x MBs | 485 * +---------------------------+ 486 * | MV buffer 64 bytes x MBs | 487 * +---------------------------+ 488 * | MC sync 32 bytes | 489 * +---------------------------+ 490 */ 491 return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32; 492 } 493 494 static inline size_t 495 hantro_hevc_mv_size(unsigned int width, unsigned int height) 496 { 497 /* 498 * A CTB can be 64x64, 32x32 or 16x16. 499 * Allocated memory for the "worse" case: 16x16 500 */ 501 return width * height / 16; 502 } 503 504 static inline unsigned short hantro_av1_num_sbs(unsigned short dimension) 505 { 506 return DIV_ROUND_UP(dimension, 64); 507 } 508 509 static inline size_t 510 hantro_av1_mv_size(unsigned int width, unsigned int height) 511 { 512 size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height); 513 514 return ALIGN(num_sbs * 384, 16) * 2 + 512; 515 } 516 517 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); 518 int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); 519 void hantro_mpeg2_dec_copy_qtable(u8 *qtable, 520 const struct v4l2_ctrl_mpeg2_quantisation *ctrl); 521 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx); 522 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx); 523 524 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx); 525 int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx); 526 int hantro_vp8_dec_init(struct hantro_ctx *ctx); 527 void hantro_vp8_dec_exit(struct hantro_ctx *ctx); 528 void hantro_vp8_prob_update(struct hantro_ctx *ctx, 529 const struct v4l2_ctrl_vp8_frame *hdr); 530 531 int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); 532 void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); 533 int hantro_vp9_dec_init(struct hantro_ctx *ctx); 534 void hantro_vp9_dec_exit(struct hantro_ctx *ctx); 535 void hantro_g2_check_idle(struct hantro_dev *vpu); 536 irqreturn_t hantro_g2_irq(int irq, void *dev_id); 537 538 #endif /* HANTRO_HW_H_ */ 539