1*ceafdaacSMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0-only
2*ceafdaacSMauro Carvalho Chehab /*
3*ceafdaacSMauro Carvalho Chehab * ispstat.c
4*ceafdaacSMauro Carvalho Chehab *
5*ceafdaacSMauro Carvalho Chehab * TI OMAP3 ISP - Statistics core
6*ceafdaacSMauro Carvalho Chehab *
7*ceafdaacSMauro Carvalho Chehab * Copyright (C) 2010 Nokia Corporation
8*ceafdaacSMauro Carvalho Chehab * Copyright (C) 2009 Texas Instruments, Inc
9*ceafdaacSMauro Carvalho Chehab *
10*ceafdaacSMauro Carvalho Chehab * Contacts: David Cohen <dacohen@gmail.com>
11*ceafdaacSMauro Carvalho Chehab * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12*ceafdaacSMauro Carvalho Chehab * Sakari Ailus <sakari.ailus@iki.fi>
13*ceafdaacSMauro Carvalho Chehab */
14*ceafdaacSMauro Carvalho Chehab
15*ceafdaacSMauro Carvalho Chehab #include <linux/dma-mapping.h>
16*ceafdaacSMauro Carvalho Chehab #include <linux/slab.h>
17*ceafdaacSMauro Carvalho Chehab #include <linux/timekeeping.h>
18*ceafdaacSMauro Carvalho Chehab #include <linux/uaccess.h>
19*ceafdaacSMauro Carvalho Chehab
20*ceafdaacSMauro Carvalho Chehab #include "isp.h"
21*ceafdaacSMauro Carvalho Chehab
22*ceafdaacSMauro Carvalho Chehab #define ISP_STAT_USES_DMAENGINE(stat) ((stat)->dma_ch != NULL)
23*ceafdaacSMauro Carvalho Chehab
24*ceafdaacSMauro Carvalho Chehab /*
25*ceafdaacSMauro Carvalho Chehab * MAGIC_SIZE must always be the greatest common divisor of
26*ceafdaacSMauro Carvalho Chehab * AEWB_PACKET_SIZE and AF_PAXEL_SIZE.
27*ceafdaacSMauro Carvalho Chehab */
28*ceafdaacSMauro Carvalho Chehab #define MAGIC_SIZE 16
29*ceafdaacSMauro Carvalho Chehab #define MAGIC_NUM 0x55
30*ceafdaacSMauro Carvalho Chehab
31*ceafdaacSMauro Carvalho Chehab /* HACK: AF module seems to be writing one more paxel data than it should. */
32*ceafdaacSMauro Carvalho Chehab #define AF_EXTRA_DATA OMAP3ISP_AF_PAXEL_SIZE
33*ceafdaacSMauro Carvalho Chehab
34*ceafdaacSMauro Carvalho Chehab /*
35*ceafdaacSMauro Carvalho Chehab * HACK: H3A modules go to an invalid state after have a SBL overflow. It makes
36*ceafdaacSMauro Carvalho Chehab * the next buffer to start to be written in the same point where the overflow
37*ceafdaacSMauro Carvalho Chehab * occurred instead of the configured address. The only known way to make it to
38*ceafdaacSMauro Carvalho Chehab * go back to a valid state is having a valid buffer processing. Of course it
39*ceafdaacSMauro Carvalho Chehab * requires at least a doubled buffer size to avoid an access to invalid memory
40*ceafdaacSMauro Carvalho Chehab * region. But it does not fix everything. It may happen more than one
41*ceafdaacSMauro Carvalho Chehab * consecutive SBL overflows. In that case, it might be unpredictable how many
42*ceafdaacSMauro Carvalho Chehab * buffers the allocated memory should fit. For that case, a recover
43*ceafdaacSMauro Carvalho Chehab * configuration was created. It produces the minimum buffer size for each H3A
44*ceafdaacSMauro Carvalho Chehab * module and decrease the change for more SBL overflows. This recover state
45*ceafdaacSMauro Carvalho Chehab * will be enabled every time a SBL overflow occur. As the output buffer size
46*ceafdaacSMauro Carvalho Chehab * isn't big, it's possible to have an extra size able to fit many recover
47*ceafdaacSMauro Carvalho Chehab * buffers making it extreamily unlikely to have an access to invalid memory
48*ceafdaacSMauro Carvalho Chehab * region.
49*ceafdaacSMauro Carvalho Chehab */
50*ceafdaacSMauro Carvalho Chehab #define NUM_H3A_RECOVER_BUFS 10
51*ceafdaacSMauro Carvalho Chehab
52*ceafdaacSMauro Carvalho Chehab /*
53*ceafdaacSMauro Carvalho Chehab * HACK: Because of HW issues the generic layer sometimes need to have
54*ceafdaacSMauro Carvalho Chehab * different behaviour for different statistic modules.
55*ceafdaacSMauro Carvalho Chehab */
56*ceafdaacSMauro Carvalho Chehab #define IS_H3A_AF(stat) ((stat) == &(stat)->isp->isp_af)
57*ceafdaacSMauro Carvalho Chehab #define IS_H3A_AEWB(stat) ((stat) == &(stat)->isp->isp_aewb)
58*ceafdaacSMauro Carvalho Chehab #define IS_H3A(stat) (IS_H3A_AF(stat) || IS_H3A_AEWB(stat))
59*ceafdaacSMauro Carvalho Chehab
__isp_stat_buf_sync_magic(struct ispstat * stat,struct ispstat_buffer * buf,u32 buf_size,enum dma_data_direction dir,void (* dma_sync)(struct device *,dma_addr_t,unsigned long,size_t,enum dma_data_direction))60*ceafdaacSMauro Carvalho Chehab static void __isp_stat_buf_sync_magic(struct ispstat *stat,
61*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf,
62*ceafdaacSMauro Carvalho Chehab u32 buf_size, enum dma_data_direction dir,
63*ceafdaacSMauro Carvalho Chehab void (*dma_sync)(struct device *,
64*ceafdaacSMauro Carvalho Chehab dma_addr_t, unsigned long, size_t,
65*ceafdaacSMauro Carvalho Chehab enum dma_data_direction))
66*ceafdaacSMauro Carvalho Chehab {
67*ceafdaacSMauro Carvalho Chehab /* Sync the initial and final magic words. */
68*ceafdaacSMauro Carvalho Chehab dma_sync(stat->isp->dev, buf->dma_addr, 0, MAGIC_SIZE, dir);
69*ceafdaacSMauro Carvalho Chehab dma_sync(stat->isp->dev, buf->dma_addr + (buf_size & PAGE_MASK),
70*ceafdaacSMauro Carvalho Chehab buf_size & ~PAGE_MASK, MAGIC_SIZE, dir);
71*ceafdaacSMauro Carvalho Chehab }
72*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_sync_magic_for_device(struct ispstat * stat,struct ispstat_buffer * buf,u32 buf_size,enum dma_data_direction dir)73*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_sync_magic_for_device(struct ispstat *stat,
74*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf,
75*ceafdaacSMauro Carvalho Chehab u32 buf_size,
76*ceafdaacSMauro Carvalho Chehab enum dma_data_direction dir)
77*ceafdaacSMauro Carvalho Chehab {
78*ceafdaacSMauro Carvalho Chehab if (ISP_STAT_USES_DMAENGINE(stat))
79*ceafdaacSMauro Carvalho Chehab return;
80*ceafdaacSMauro Carvalho Chehab
81*ceafdaacSMauro Carvalho Chehab __isp_stat_buf_sync_magic(stat, buf, buf_size, dir,
82*ceafdaacSMauro Carvalho Chehab dma_sync_single_range_for_device);
83*ceafdaacSMauro Carvalho Chehab }
84*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_sync_magic_for_cpu(struct ispstat * stat,struct ispstat_buffer * buf,u32 buf_size,enum dma_data_direction dir)85*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_sync_magic_for_cpu(struct ispstat *stat,
86*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf,
87*ceafdaacSMauro Carvalho Chehab u32 buf_size,
88*ceafdaacSMauro Carvalho Chehab enum dma_data_direction dir)
89*ceafdaacSMauro Carvalho Chehab {
90*ceafdaacSMauro Carvalho Chehab if (ISP_STAT_USES_DMAENGINE(stat))
91*ceafdaacSMauro Carvalho Chehab return;
92*ceafdaacSMauro Carvalho Chehab
93*ceafdaacSMauro Carvalho Chehab __isp_stat_buf_sync_magic(stat, buf, buf_size, dir,
94*ceafdaacSMauro Carvalho Chehab dma_sync_single_range_for_cpu);
95*ceafdaacSMauro Carvalho Chehab }
96*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_check_magic(struct ispstat * stat,struct ispstat_buffer * buf)97*ceafdaacSMauro Carvalho Chehab static int isp_stat_buf_check_magic(struct ispstat *stat,
98*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf)
99*ceafdaacSMauro Carvalho Chehab {
100*ceafdaacSMauro Carvalho Chehab const u32 buf_size = IS_H3A_AF(stat) ?
101*ceafdaacSMauro Carvalho Chehab buf->buf_size + AF_EXTRA_DATA : buf->buf_size;
102*ceafdaacSMauro Carvalho Chehab u8 *w;
103*ceafdaacSMauro Carvalho Chehab u8 *end;
104*ceafdaacSMauro Carvalho Chehab int ret = -EINVAL;
105*ceafdaacSMauro Carvalho Chehab
106*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_magic_for_cpu(stat, buf, buf_size, DMA_FROM_DEVICE);
107*ceafdaacSMauro Carvalho Chehab
108*ceafdaacSMauro Carvalho Chehab /* Checking initial magic numbers. They shouldn't be here anymore. */
109*ceafdaacSMauro Carvalho Chehab for (w = buf->virt_addr, end = w + MAGIC_SIZE; w < end; w++)
110*ceafdaacSMauro Carvalho Chehab if (likely(*w != MAGIC_NUM))
111*ceafdaacSMauro Carvalho Chehab ret = 0;
112*ceafdaacSMauro Carvalho Chehab
113*ceafdaacSMauro Carvalho Chehab if (ret) {
114*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
115*ceafdaacSMauro Carvalho Chehab "%s: beginning magic check does not match.\n",
116*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
117*ceafdaacSMauro Carvalho Chehab return ret;
118*ceafdaacSMauro Carvalho Chehab }
119*ceafdaacSMauro Carvalho Chehab
120*ceafdaacSMauro Carvalho Chehab /* Checking magic numbers at the end. They must be still here. */
121*ceafdaacSMauro Carvalho Chehab for (w = buf->virt_addr + buf_size, end = w + MAGIC_SIZE;
122*ceafdaacSMauro Carvalho Chehab w < end; w++) {
123*ceafdaacSMauro Carvalho Chehab if (unlikely(*w != MAGIC_NUM)) {
124*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
125*ceafdaacSMauro Carvalho Chehab "%s: ending magic check does not match.\n",
126*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
127*ceafdaacSMauro Carvalho Chehab return -EINVAL;
128*ceafdaacSMauro Carvalho Chehab }
129*ceafdaacSMauro Carvalho Chehab }
130*ceafdaacSMauro Carvalho Chehab
131*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_magic_for_device(stat, buf, buf_size,
132*ceafdaacSMauro Carvalho Chehab DMA_FROM_DEVICE);
133*ceafdaacSMauro Carvalho Chehab
134*ceafdaacSMauro Carvalho Chehab return 0;
135*ceafdaacSMauro Carvalho Chehab }
136*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_insert_magic(struct ispstat * stat,struct ispstat_buffer * buf)137*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_insert_magic(struct ispstat *stat,
138*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf)
139*ceafdaacSMauro Carvalho Chehab {
140*ceafdaacSMauro Carvalho Chehab const u32 buf_size = IS_H3A_AF(stat) ?
141*ceafdaacSMauro Carvalho Chehab stat->buf_size + AF_EXTRA_DATA : stat->buf_size;
142*ceafdaacSMauro Carvalho Chehab
143*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_magic_for_cpu(stat, buf, buf_size, DMA_FROM_DEVICE);
144*ceafdaacSMauro Carvalho Chehab
145*ceafdaacSMauro Carvalho Chehab /*
146*ceafdaacSMauro Carvalho Chehab * Inserting MAGIC_NUM at the beginning and end of the buffer.
147*ceafdaacSMauro Carvalho Chehab * buf->buf_size is set only after the buffer is queued. For now the
148*ceafdaacSMauro Carvalho Chehab * right buf_size for the current configuration is pointed by
149*ceafdaacSMauro Carvalho Chehab * stat->buf_size.
150*ceafdaacSMauro Carvalho Chehab */
151*ceafdaacSMauro Carvalho Chehab memset(buf->virt_addr, MAGIC_NUM, MAGIC_SIZE);
152*ceafdaacSMauro Carvalho Chehab memset(buf->virt_addr + buf_size, MAGIC_NUM, MAGIC_SIZE);
153*ceafdaacSMauro Carvalho Chehab
154*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_magic_for_device(stat, buf, buf_size,
155*ceafdaacSMauro Carvalho Chehab DMA_BIDIRECTIONAL);
156*ceafdaacSMauro Carvalho Chehab }
157*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_sync_for_device(struct ispstat * stat,struct ispstat_buffer * buf)158*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_sync_for_device(struct ispstat *stat,
159*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf)
160*ceafdaacSMauro Carvalho Chehab {
161*ceafdaacSMauro Carvalho Chehab if (ISP_STAT_USES_DMAENGINE(stat))
162*ceafdaacSMauro Carvalho Chehab return;
163*ceafdaacSMauro Carvalho Chehab
164*ceafdaacSMauro Carvalho Chehab dma_sync_sg_for_device(stat->isp->dev, buf->sgt.sgl,
165*ceafdaacSMauro Carvalho Chehab buf->sgt.nents, DMA_FROM_DEVICE);
166*ceafdaacSMauro Carvalho Chehab }
167*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_sync_for_cpu(struct ispstat * stat,struct ispstat_buffer * buf)168*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_sync_for_cpu(struct ispstat *stat,
169*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf)
170*ceafdaacSMauro Carvalho Chehab {
171*ceafdaacSMauro Carvalho Chehab if (ISP_STAT_USES_DMAENGINE(stat))
172*ceafdaacSMauro Carvalho Chehab return;
173*ceafdaacSMauro Carvalho Chehab
174*ceafdaacSMauro Carvalho Chehab dma_sync_sg_for_cpu(stat->isp->dev, buf->sgt.sgl,
175*ceafdaacSMauro Carvalho Chehab buf->sgt.nents, DMA_FROM_DEVICE);
176*ceafdaacSMauro Carvalho Chehab }
177*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_clear(struct ispstat * stat)178*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_clear(struct ispstat *stat)
179*ceafdaacSMauro Carvalho Chehab {
180*ceafdaacSMauro Carvalho Chehab int i;
181*ceafdaacSMauro Carvalho Chehab
182*ceafdaacSMauro Carvalho Chehab for (i = 0; i < STAT_MAX_BUFS; i++)
183*ceafdaacSMauro Carvalho Chehab stat->buf[i].empty = 1;
184*ceafdaacSMauro Carvalho Chehab }
185*ceafdaacSMauro Carvalho Chehab
186*ceafdaacSMauro Carvalho Chehab static struct ispstat_buffer *
__isp_stat_buf_find(struct ispstat * stat,int look_empty)187*ceafdaacSMauro Carvalho Chehab __isp_stat_buf_find(struct ispstat *stat, int look_empty)
188*ceafdaacSMauro Carvalho Chehab {
189*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *found = NULL;
190*ceafdaacSMauro Carvalho Chehab int i;
191*ceafdaacSMauro Carvalho Chehab
192*ceafdaacSMauro Carvalho Chehab for (i = 0; i < STAT_MAX_BUFS; i++) {
193*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *curr = &stat->buf[i];
194*ceafdaacSMauro Carvalho Chehab
195*ceafdaacSMauro Carvalho Chehab /*
196*ceafdaacSMauro Carvalho Chehab * Don't select the buffer which is being copied to
197*ceafdaacSMauro Carvalho Chehab * userspace or used by the module.
198*ceafdaacSMauro Carvalho Chehab */
199*ceafdaacSMauro Carvalho Chehab if (curr == stat->locked_buf || curr == stat->active_buf)
200*ceafdaacSMauro Carvalho Chehab continue;
201*ceafdaacSMauro Carvalho Chehab
202*ceafdaacSMauro Carvalho Chehab /* Don't select uninitialised buffers if it's not required */
203*ceafdaacSMauro Carvalho Chehab if (!look_empty && curr->empty)
204*ceafdaacSMauro Carvalho Chehab continue;
205*ceafdaacSMauro Carvalho Chehab
206*ceafdaacSMauro Carvalho Chehab /* Pick uninitialised buffer over anything else if look_empty */
207*ceafdaacSMauro Carvalho Chehab if (curr->empty) {
208*ceafdaacSMauro Carvalho Chehab found = curr;
209*ceafdaacSMauro Carvalho Chehab break;
210*ceafdaacSMauro Carvalho Chehab }
211*ceafdaacSMauro Carvalho Chehab
212*ceafdaacSMauro Carvalho Chehab /* Choose the oldest buffer */
213*ceafdaacSMauro Carvalho Chehab if (!found ||
214*ceafdaacSMauro Carvalho Chehab (s32)curr->frame_number - (s32)found->frame_number < 0)
215*ceafdaacSMauro Carvalho Chehab found = curr;
216*ceafdaacSMauro Carvalho Chehab }
217*ceafdaacSMauro Carvalho Chehab
218*ceafdaacSMauro Carvalho Chehab return found;
219*ceafdaacSMauro Carvalho Chehab }
220*ceafdaacSMauro Carvalho Chehab
221*ceafdaacSMauro Carvalho Chehab static inline struct ispstat_buffer *
isp_stat_buf_find_oldest(struct ispstat * stat)222*ceafdaacSMauro Carvalho Chehab isp_stat_buf_find_oldest(struct ispstat *stat)
223*ceafdaacSMauro Carvalho Chehab {
224*ceafdaacSMauro Carvalho Chehab return __isp_stat_buf_find(stat, 0);
225*ceafdaacSMauro Carvalho Chehab }
226*ceafdaacSMauro Carvalho Chehab
227*ceafdaacSMauro Carvalho Chehab static inline struct ispstat_buffer *
isp_stat_buf_find_oldest_or_empty(struct ispstat * stat)228*ceafdaacSMauro Carvalho Chehab isp_stat_buf_find_oldest_or_empty(struct ispstat *stat)
229*ceafdaacSMauro Carvalho Chehab {
230*ceafdaacSMauro Carvalho Chehab return __isp_stat_buf_find(stat, 1);
231*ceafdaacSMauro Carvalho Chehab }
232*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_queue(struct ispstat * stat)233*ceafdaacSMauro Carvalho Chehab static int isp_stat_buf_queue(struct ispstat *stat)
234*ceafdaacSMauro Carvalho Chehab {
235*ceafdaacSMauro Carvalho Chehab if (!stat->active_buf)
236*ceafdaacSMauro Carvalho Chehab return STAT_NO_BUF;
237*ceafdaacSMauro Carvalho Chehab
238*ceafdaacSMauro Carvalho Chehab ktime_get_ts64(&stat->active_buf->ts);
239*ceafdaacSMauro Carvalho Chehab
240*ceafdaacSMauro Carvalho Chehab stat->active_buf->buf_size = stat->buf_size;
241*ceafdaacSMauro Carvalho Chehab if (isp_stat_buf_check_magic(stat, stat->active_buf)) {
242*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: data wasn't properly written.\n",
243*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
244*ceafdaacSMauro Carvalho Chehab return STAT_NO_BUF;
245*ceafdaacSMauro Carvalho Chehab }
246*ceafdaacSMauro Carvalho Chehab stat->active_buf->config_counter = stat->config_counter;
247*ceafdaacSMauro Carvalho Chehab stat->active_buf->frame_number = stat->frame_number;
248*ceafdaacSMauro Carvalho Chehab stat->active_buf->empty = 0;
249*ceafdaacSMauro Carvalho Chehab stat->active_buf = NULL;
250*ceafdaacSMauro Carvalho Chehab
251*ceafdaacSMauro Carvalho Chehab return STAT_BUF_DONE;
252*ceafdaacSMauro Carvalho Chehab }
253*ceafdaacSMauro Carvalho Chehab
254*ceafdaacSMauro Carvalho Chehab /* Get next free buffer to write the statistics to and mark it active. */
isp_stat_buf_next(struct ispstat * stat)255*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_next(struct ispstat *stat)
256*ceafdaacSMauro Carvalho Chehab {
257*ceafdaacSMauro Carvalho Chehab if (unlikely(stat->active_buf))
258*ceafdaacSMauro Carvalho Chehab /* Overwriting unused active buffer */
259*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
260*ceafdaacSMauro Carvalho Chehab "%s: new buffer requested without queuing active one.\n",
261*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
262*ceafdaacSMauro Carvalho Chehab else
263*ceafdaacSMauro Carvalho Chehab stat->active_buf = isp_stat_buf_find_oldest_or_empty(stat);
264*ceafdaacSMauro Carvalho Chehab }
265*ceafdaacSMauro Carvalho Chehab
isp_stat_buf_release(struct ispstat * stat)266*ceafdaacSMauro Carvalho Chehab static void isp_stat_buf_release(struct ispstat *stat)
267*ceafdaacSMauro Carvalho Chehab {
268*ceafdaacSMauro Carvalho Chehab unsigned long flags;
269*ceafdaacSMauro Carvalho Chehab
270*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_for_device(stat, stat->locked_buf);
271*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, flags);
272*ceafdaacSMauro Carvalho Chehab stat->locked_buf = NULL;
273*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
274*ceafdaacSMauro Carvalho Chehab }
275*ceafdaacSMauro Carvalho Chehab
276*ceafdaacSMauro Carvalho Chehab /* Get buffer to userspace. */
isp_stat_buf_get(struct ispstat * stat,struct omap3isp_stat_data * data)277*ceafdaacSMauro Carvalho Chehab static struct ispstat_buffer *isp_stat_buf_get(struct ispstat *stat,
278*ceafdaacSMauro Carvalho Chehab struct omap3isp_stat_data *data)
279*ceafdaacSMauro Carvalho Chehab {
280*ceafdaacSMauro Carvalho Chehab int rval = 0;
281*ceafdaacSMauro Carvalho Chehab unsigned long flags;
282*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf;
283*ceafdaacSMauro Carvalho Chehab
284*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, flags);
285*ceafdaacSMauro Carvalho Chehab
286*ceafdaacSMauro Carvalho Chehab while (1) {
287*ceafdaacSMauro Carvalho Chehab buf = isp_stat_buf_find_oldest(stat);
288*ceafdaacSMauro Carvalho Chehab if (!buf) {
289*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
290*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: cannot find a buffer.\n",
291*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
292*ceafdaacSMauro Carvalho Chehab return ERR_PTR(-EBUSY);
293*ceafdaacSMauro Carvalho Chehab }
294*ceafdaacSMauro Carvalho Chehab if (isp_stat_buf_check_magic(stat, buf)) {
295*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
296*ceafdaacSMauro Carvalho Chehab "%s: current buffer has corrupted data\n.",
297*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
298*ceafdaacSMauro Carvalho Chehab /* Mark empty because it doesn't have valid data. */
299*ceafdaacSMauro Carvalho Chehab buf->empty = 1;
300*ceafdaacSMauro Carvalho Chehab } else {
301*ceafdaacSMauro Carvalho Chehab /* Buffer isn't corrupted. */
302*ceafdaacSMauro Carvalho Chehab break;
303*ceafdaacSMauro Carvalho Chehab }
304*ceafdaacSMauro Carvalho Chehab }
305*ceafdaacSMauro Carvalho Chehab
306*ceafdaacSMauro Carvalho Chehab stat->locked_buf = buf;
307*ceafdaacSMauro Carvalho Chehab
308*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
309*ceafdaacSMauro Carvalho Chehab
310*ceafdaacSMauro Carvalho Chehab if (buf->buf_size > data->buf_size) {
311*ceafdaacSMauro Carvalho Chehab dev_warn(stat->isp->dev,
312*ceafdaacSMauro Carvalho Chehab "%s: userspace's buffer size is not enough.\n",
313*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
314*ceafdaacSMauro Carvalho Chehab isp_stat_buf_release(stat);
315*ceafdaacSMauro Carvalho Chehab return ERR_PTR(-EINVAL);
316*ceafdaacSMauro Carvalho Chehab }
317*ceafdaacSMauro Carvalho Chehab
318*ceafdaacSMauro Carvalho Chehab isp_stat_buf_sync_for_cpu(stat, buf);
319*ceafdaacSMauro Carvalho Chehab
320*ceafdaacSMauro Carvalho Chehab rval = copy_to_user(data->buf,
321*ceafdaacSMauro Carvalho Chehab buf->virt_addr,
322*ceafdaacSMauro Carvalho Chehab buf->buf_size);
323*ceafdaacSMauro Carvalho Chehab
324*ceafdaacSMauro Carvalho Chehab if (rval) {
325*ceafdaacSMauro Carvalho Chehab dev_info(stat->isp->dev,
326*ceafdaacSMauro Carvalho Chehab "%s: failed copying %d bytes of stat data\n",
327*ceafdaacSMauro Carvalho Chehab stat->subdev.name, rval);
328*ceafdaacSMauro Carvalho Chehab buf = ERR_PTR(-EFAULT);
329*ceafdaacSMauro Carvalho Chehab isp_stat_buf_release(stat);
330*ceafdaacSMauro Carvalho Chehab }
331*ceafdaacSMauro Carvalho Chehab
332*ceafdaacSMauro Carvalho Chehab return buf;
333*ceafdaacSMauro Carvalho Chehab }
334*ceafdaacSMauro Carvalho Chehab
isp_stat_bufs_free(struct ispstat * stat)335*ceafdaacSMauro Carvalho Chehab static void isp_stat_bufs_free(struct ispstat *stat)
336*ceafdaacSMauro Carvalho Chehab {
337*ceafdaacSMauro Carvalho Chehab struct device *dev = ISP_STAT_USES_DMAENGINE(stat)
338*ceafdaacSMauro Carvalho Chehab ? NULL : stat->isp->dev;
339*ceafdaacSMauro Carvalho Chehab unsigned int i;
340*ceafdaacSMauro Carvalho Chehab
341*ceafdaacSMauro Carvalho Chehab for (i = 0; i < STAT_MAX_BUFS; i++) {
342*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf = &stat->buf[i];
343*ceafdaacSMauro Carvalho Chehab
344*ceafdaacSMauro Carvalho Chehab if (!buf->virt_addr)
345*ceafdaacSMauro Carvalho Chehab continue;
346*ceafdaacSMauro Carvalho Chehab
347*ceafdaacSMauro Carvalho Chehab sg_free_table(&buf->sgt);
348*ceafdaacSMauro Carvalho Chehab
349*ceafdaacSMauro Carvalho Chehab dma_free_coherent(dev, stat->buf_alloc_size, buf->virt_addr,
350*ceafdaacSMauro Carvalho Chehab buf->dma_addr);
351*ceafdaacSMauro Carvalho Chehab
352*ceafdaacSMauro Carvalho Chehab buf->dma_addr = 0;
353*ceafdaacSMauro Carvalho Chehab buf->virt_addr = NULL;
354*ceafdaacSMauro Carvalho Chehab buf->empty = 1;
355*ceafdaacSMauro Carvalho Chehab }
356*ceafdaacSMauro Carvalho Chehab
357*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: all buffers were freed.\n",
358*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
359*ceafdaacSMauro Carvalho Chehab
360*ceafdaacSMauro Carvalho Chehab stat->buf_alloc_size = 0;
361*ceafdaacSMauro Carvalho Chehab stat->active_buf = NULL;
362*ceafdaacSMauro Carvalho Chehab }
363*ceafdaacSMauro Carvalho Chehab
isp_stat_bufs_alloc_one(struct device * dev,struct ispstat_buffer * buf,unsigned int size)364*ceafdaacSMauro Carvalho Chehab static int isp_stat_bufs_alloc_one(struct device *dev,
365*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf,
366*ceafdaacSMauro Carvalho Chehab unsigned int size)
367*ceafdaacSMauro Carvalho Chehab {
368*ceafdaacSMauro Carvalho Chehab int ret;
369*ceafdaacSMauro Carvalho Chehab
370*ceafdaacSMauro Carvalho Chehab buf->virt_addr = dma_alloc_coherent(dev, size, &buf->dma_addr,
371*ceafdaacSMauro Carvalho Chehab GFP_KERNEL);
372*ceafdaacSMauro Carvalho Chehab if (!buf->virt_addr)
373*ceafdaacSMauro Carvalho Chehab return -ENOMEM;
374*ceafdaacSMauro Carvalho Chehab
375*ceafdaacSMauro Carvalho Chehab ret = dma_get_sgtable(dev, &buf->sgt, buf->virt_addr, buf->dma_addr,
376*ceafdaacSMauro Carvalho Chehab size);
377*ceafdaacSMauro Carvalho Chehab if (ret < 0) {
378*ceafdaacSMauro Carvalho Chehab dma_free_coherent(dev, size, buf->virt_addr, buf->dma_addr);
379*ceafdaacSMauro Carvalho Chehab buf->virt_addr = NULL;
380*ceafdaacSMauro Carvalho Chehab buf->dma_addr = 0;
381*ceafdaacSMauro Carvalho Chehab return ret;
382*ceafdaacSMauro Carvalho Chehab }
383*ceafdaacSMauro Carvalho Chehab
384*ceafdaacSMauro Carvalho Chehab return 0;
385*ceafdaacSMauro Carvalho Chehab }
386*ceafdaacSMauro Carvalho Chehab
387*ceafdaacSMauro Carvalho Chehab /*
388*ceafdaacSMauro Carvalho Chehab * The device passed to the DMA API depends on whether the statistics block uses
389*ceafdaacSMauro Carvalho Chehab * ISP DMA, external DMA or PIO to transfer data.
390*ceafdaacSMauro Carvalho Chehab *
391*ceafdaacSMauro Carvalho Chehab * The first case (for the AEWB and AF engines) passes the ISP device, resulting
392*ceafdaacSMauro Carvalho Chehab * in the DMA buffers being mapped through the ISP IOMMU.
393*ceafdaacSMauro Carvalho Chehab *
394*ceafdaacSMauro Carvalho Chehab * The second case (for the histogram engine) should pass the DMA engine device.
395*ceafdaacSMauro Carvalho Chehab * As that device isn't accessible through the OMAP DMA engine API the driver
396*ceafdaacSMauro Carvalho Chehab * passes NULL instead, resulting in the buffers being mapped directly as
397*ceafdaacSMauro Carvalho Chehab * physical pages.
398*ceafdaacSMauro Carvalho Chehab *
399*ceafdaacSMauro Carvalho Chehab * The third case (for the histogram engine) doesn't require any mapping. The
400*ceafdaacSMauro Carvalho Chehab * buffers could be allocated with kmalloc/vmalloc, but we still use
401*ceafdaacSMauro Carvalho Chehab * dma_alloc_coherent() for consistency purpose.
402*ceafdaacSMauro Carvalho Chehab */
isp_stat_bufs_alloc(struct ispstat * stat,u32 size)403*ceafdaacSMauro Carvalho Chehab static int isp_stat_bufs_alloc(struct ispstat *stat, u32 size)
404*ceafdaacSMauro Carvalho Chehab {
405*ceafdaacSMauro Carvalho Chehab struct device *dev = ISP_STAT_USES_DMAENGINE(stat)
406*ceafdaacSMauro Carvalho Chehab ? NULL : stat->isp->dev;
407*ceafdaacSMauro Carvalho Chehab unsigned long flags;
408*ceafdaacSMauro Carvalho Chehab unsigned int i;
409*ceafdaacSMauro Carvalho Chehab
410*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, flags);
411*ceafdaacSMauro Carvalho Chehab
412*ceafdaacSMauro Carvalho Chehab BUG_ON(stat->locked_buf != NULL);
413*ceafdaacSMauro Carvalho Chehab
414*ceafdaacSMauro Carvalho Chehab /* Are the old buffers big enough? */
415*ceafdaacSMauro Carvalho Chehab if (stat->buf_alloc_size >= size) {
416*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
417*ceafdaacSMauro Carvalho Chehab return 0;
418*ceafdaacSMauro Carvalho Chehab }
419*ceafdaacSMauro Carvalho Chehab
420*ceafdaacSMauro Carvalho Chehab if (stat->state != ISPSTAT_DISABLED || stat->buf_processing) {
421*ceafdaacSMauro Carvalho Chehab dev_info(stat->isp->dev,
422*ceafdaacSMauro Carvalho Chehab "%s: trying to allocate memory when busy\n",
423*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
424*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
425*ceafdaacSMauro Carvalho Chehab return -EBUSY;
426*ceafdaacSMauro Carvalho Chehab }
427*ceafdaacSMauro Carvalho Chehab
428*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
429*ceafdaacSMauro Carvalho Chehab
430*ceafdaacSMauro Carvalho Chehab isp_stat_bufs_free(stat);
431*ceafdaacSMauro Carvalho Chehab
432*ceafdaacSMauro Carvalho Chehab stat->buf_alloc_size = size;
433*ceafdaacSMauro Carvalho Chehab
434*ceafdaacSMauro Carvalho Chehab for (i = 0; i < STAT_MAX_BUFS; i++) {
435*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf = &stat->buf[i];
436*ceafdaacSMauro Carvalho Chehab int ret;
437*ceafdaacSMauro Carvalho Chehab
438*ceafdaacSMauro Carvalho Chehab ret = isp_stat_bufs_alloc_one(dev, buf, size);
439*ceafdaacSMauro Carvalho Chehab if (ret < 0) {
440*ceafdaacSMauro Carvalho Chehab dev_err(stat->isp->dev,
441*ceafdaacSMauro Carvalho Chehab "%s: Failed to allocate DMA buffer %u\n",
442*ceafdaacSMauro Carvalho Chehab stat->subdev.name, i);
443*ceafdaacSMauro Carvalho Chehab isp_stat_bufs_free(stat);
444*ceafdaacSMauro Carvalho Chehab return ret;
445*ceafdaacSMauro Carvalho Chehab }
446*ceafdaacSMauro Carvalho Chehab
447*ceafdaacSMauro Carvalho Chehab buf->empty = 1;
448*ceafdaacSMauro Carvalho Chehab
449*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
450*ceafdaacSMauro Carvalho Chehab "%s: buffer[%u] allocated. dma=%pad virt=%p",
451*ceafdaacSMauro Carvalho Chehab stat->subdev.name, i, &buf->dma_addr, buf->virt_addr);
452*ceafdaacSMauro Carvalho Chehab }
453*ceafdaacSMauro Carvalho Chehab
454*ceafdaacSMauro Carvalho Chehab return 0;
455*ceafdaacSMauro Carvalho Chehab }
456*ceafdaacSMauro Carvalho Chehab
isp_stat_queue_event(struct ispstat * stat,int err)457*ceafdaacSMauro Carvalho Chehab static void isp_stat_queue_event(struct ispstat *stat, int err)
458*ceafdaacSMauro Carvalho Chehab {
459*ceafdaacSMauro Carvalho Chehab struct video_device *vdev = stat->subdev.devnode;
460*ceafdaacSMauro Carvalho Chehab struct v4l2_event event;
461*ceafdaacSMauro Carvalho Chehab struct omap3isp_stat_event_status *status = (void *)event.u.data;
462*ceafdaacSMauro Carvalho Chehab
463*ceafdaacSMauro Carvalho Chehab memset(&event, 0, sizeof(event));
464*ceafdaacSMauro Carvalho Chehab if (!err) {
465*ceafdaacSMauro Carvalho Chehab status->frame_number = stat->frame_number;
466*ceafdaacSMauro Carvalho Chehab status->config_counter = stat->config_counter;
467*ceafdaacSMauro Carvalho Chehab } else {
468*ceafdaacSMauro Carvalho Chehab status->buf_err = 1;
469*ceafdaacSMauro Carvalho Chehab }
470*ceafdaacSMauro Carvalho Chehab event.type = stat->event_type;
471*ceafdaacSMauro Carvalho Chehab v4l2_event_queue(vdev, &event);
472*ceafdaacSMauro Carvalho Chehab }
473*ceafdaacSMauro Carvalho Chehab
474*ceafdaacSMauro Carvalho Chehab
475*ceafdaacSMauro Carvalho Chehab /*
476*ceafdaacSMauro Carvalho Chehab * omap3isp_stat_request_statistics - Request statistics.
477*ceafdaacSMauro Carvalho Chehab * @data: Pointer to return statistics data.
478*ceafdaacSMauro Carvalho Chehab *
479*ceafdaacSMauro Carvalho Chehab * Returns 0 if successful.
480*ceafdaacSMauro Carvalho Chehab */
omap3isp_stat_request_statistics(struct ispstat * stat,struct omap3isp_stat_data * data)481*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_request_statistics(struct ispstat *stat,
482*ceafdaacSMauro Carvalho Chehab struct omap3isp_stat_data *data)
483*ceafdaacSMauro Carvalho Chehab {
484*ceafdaacSMauro Carvalho Chehab struct ispstat_buffer *buf;
485*ceafdaacSMauro Carvalho Chehab
486*ceafdaacSMauro Carvalho Chehab if (stat->state != ISPSTAT_ENABLED) {
487*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: engine not enabled.\n",
488*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
489*ceafdaacSMauro Carvalho Chehab return -EINVAL;
490*ceafdaacSMauro Carvalho Chehab }
491*ceafdaacSMauro Carvalho Chehab
492*ceafdaacSMauro Carvalho Chehab mutex_lock(&stat->ioctl_lock);
493*ceafdaacSMauro Carvalho Chehab buf = isp_stat_buf_get(stat, data);
494*ceafdaacSMauro Carvalho Chehab if (IS_ERR(buf)) {
495*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
496*ceafdaacSMauro Carvalho Chehab return PTR_ERR(buf);
497*ceafdaacSMauro Carvalho Chehab }
498*ceafdaacSMauro Carvalho Chehab
499*ceafdaacSMauro Carvalho Chehab data->ts.tv_sec = buf->ts.tv_sec;
500*ceafdaacSMauro Carvalho Chehab data->ts.tv_usec = buf->ts.tv_nsec / NSEC_PER_USEC;
501*ceafdaacSMauro Carvalho Chehab data->config_counter = buf->config_counter;
502*ceafdaacSMauro Carvalho Chehab data->frame_number = buf->frame_number;
503*ceafdaacSMauro Carvalho Chehab data->buf_size = buf->buf_size;
504*ceafdaacSMauro Carvalho Chehab
505*ceafdaacSMauro Carvalho Chehab buf->empty = 1;
506*ceafdaacSMauro Carvalho Chehab isp_stat_buf_release(stat);
507*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
508*ceafdaacSMauro Carvalho Chehab
509*ceafdaacSMauro Carvalho Chehab return 0;
510*ceafdaacSMauro Carvalho Chehab }
511*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_request_statistics_time32(struct ispstat * stat,struct omap3isp_stat_data_time32 * data)512*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_request_statistics_time32(struct ispstat *stat,
513*ceafdaacSMauro Carvalho Chehab struct omap3isp_stat_data_time32 *data)
514*ceafdaacSMauro Carvalho Chehab {
515*ceafdaacSMauro Carvalho Chehab struct omap3isp_stat_data data64 = { };
516*ceafdaacSMauro Carvalho Chehab int ret;
517*ceafdaacSMauro Carvalho Chehab
518*ceafdaacSMauro Carvalho Chehab ret = omap3isp_stat_request_statistics(stat, &data64);
519*ceafdaacSMauro Carvalho Chehab if (ret)
520*ceafdaacSMauro Carvalho Chehab return ret;
521*ceafdaacSMauro Carvalho Chehab
522*ceafdaacSMauro Carvalho Chehab data->ts.tv_sec = data64.ts.tv_sec;
523*ceafdaacSMauro Carvalho Chehab data->ts.tv_usec = data64.ts.tv_usec;
524*ceafdaacSMauro Carvalho Chehab data->buf = (uintptr_t)data64.buf;
525*ceafdaacSMauro Carvalho Chehab memcpy(&data->frame, &data64.frame, sizeof(data->frame));
526*ceafdaacSMauro Carvalho Chehab
527*ceafdaacSMauro Carvalho Chehab return 0;
528*ceafdaacSMauro Carvalho Chehab }
529*ceafdaacSMauro Carvalho Chehab
530*ceafdaacSMauro Carvalho Chehab /*
531*ceafdaacSMauro Carvalho Chehab * omap3isp_stat_config - Receives new statistic engine configuration.
532*ceafdaacSMauro Carvalho Chehab * @new_conf: Pointer to config structure.
533*ceafdaacSMauro Carvalho Chehab *
534*ceafdaacSMauro Carvalho Chehab * Returns 0 if successful, -EINVAL if new_conf pointer is NULL, -ENOMEM if
535*ceafdaacSMauro Carvalho Chehab * was unable to allocate memory for the buffer, or other errors if parameters
536*ceafdaacSMauro Carvalho Chehab * are invalid.
537*ceafdaacSMauro Carvalho Chehab */
omap3isp_stat_config(struct ispstat * stat,void * new_conf)538*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_config(struct ispstat *stat, void *new_conf)
539*ceafdaacSMauro Carvalho Chehab {
540*ceafdaacSMauro Carvalho Chehab int ret;
541*ceafdaacSMauro Carvalho Chehab unsigned long irqflags;
542*ceafdaacSMauro Carvalho Chehab struct ispstat_generic_config *user_cfg = new_conf;
543*ceafdaacSMauro Carvalho Chehab u32 buf_size = user_cfg->buf_size;
544*ceafdaacSMauro Carvalho Chehab
545*ceafdaacSMauro Carvalho Chehab mutex_lock(&stat->ioctl_lock);
546*ceafdaacSMauro Carvalho Chehab
547*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
548*ceafdaacSMauro Carvalho Chehab "%s: configuring module with buffer size=0x%08lx\n",
549*ceafdaacSMauro Carvalho Chehab stat->subdev.name, (unsigned long)buf_size);
550*ceafdaacSMauro Carvalho Chehab
551*ceafdaacSMauro Carvalho Chehab ret = stat->ops->validate_params(stat, new_conf);
552*ceafdaacSMauro Carvalho Chehab if (ret) {
553*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
554*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: configuration values are invalid.\n",
555*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
556*ceafdaacSMauro Carvalho Chehab return ret;
557*ceafdaacSMauro Carvalho Chehab }
558*ceafdaacSMauro Carvalho Chehab
559*ceafdaacSMauro Carvalho Chehab if (buf_size != user_cfg->buf_size)
560*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
561*ceafdaacSMauro Carvalho Chehab "%s: driver has corrected buffer size request to 0x%08lx\n",
562*ceafdaacSMauro Carvalho Chehab stat->subdev.name,
563*ceafdaacSMauro Carvalho Chehab (unsigned long)user_cfg->buf_size);
564*ceafdaacSMauro Carvalho Chehab
565*ceafdaacSMauro Carvalho Chehab /*
566*ceafdaacSMauro Carvalho Chehab * Hack: H3A modules may need a doubled buffer size to avoid access
567*ceafdaacSMauro Carvalho Chehab * to a invalid memory address after a SBL overflow.
568*ceafdaacSMauro Carvalho Chehab * The buffer size is always PAGE_ALIGNED.
569*ceafdaacSMauro Carvalho Chehab * Hack 2: MAGIC_SIZE is added to buf_size so a magic word can be
570*ceafdaacSMauro Carvalho Chehab * inserted at the end to data integrity check purpose.
571*ceafdaacSMauro Carvalho Chehab * Hack 3: AF module writes one paxel data more than it should, so
572*ceafdaacSMauro Carvalho Chehab * the buffer allocation must consider it to avoid invalid memory
573*ceafdaacSMauro Carvalho Chehab * access.
574*ceafdaacSMauro Carvalho Chehab * Hack 4: H3A need to allocate extra space for the recover state.
575*ceafdaacSMauro Carvalho Chehab */
576*ceafdaacSMauro Carvalho Chehab if (IS_H3A(stat)) {
577*ceafdaacSMauro Carvalho Chehab buf_size = user_cfg->buf_size * 2 + MAGIC_SIZE;
578*ceafdaacSMauro Carvalho Chehab if (IS_H3A_AF(stat))
579*ceafdaacSMauro Carvalho Chehab /*
580*ceafdaacSMauro Carvalho Chehab * Adding one extra paxel data size for each recover
581*ceafdaacSMauro Carvalho Chehab * buffer + 2 regular ones.
582*ceafdaacSMauro Carvalho Chehab */
583*ceafdaacSMauro Carvalho Chehab buf_size += AF_EXTRA_DATA * (NUM_H3A_RECOVER_BUFS + 2);
584*ceafdaacSMauro Carvalho Chehab if (stat->recover_priv) {
585*ceafdaacSMauro Carvalho Chehab struct ispstat_generic_config *recover_cfg =
586*ceafdaacSMauro Carvalho Chehab stat->recover_priv;
587*ceafdaacSMauro Carvalho Chehab buf_size += recover_cfg->buf_size *
588*ceafdaacSMauro Carvalho Chehab NUM_H3A_RECOVER_BUFS;
589*ceafdaacSMauro Carvalho Chehab }
590*ceafdaacSMauro Carvalho Chehab buf_size = PAGE_ALIGN(buf_size);
591*ceafdaacSMauro Carvalho Chehab } else { /* Histogram */
592*ceafdaacSMauro Carvalho Chehab buf_size = PAGE_ALIGN(user_cfg->buf_size + MAGIC_SIZE);
593*ceafdaacSMauro Carvalho Chehab }
594*ceafdaacSMauro Carvalho Chehab
595*ceafdaacSMauro Carvalho Chehab ret = isp_stat_bufs_alloc(stat, buf_size);
596*ceafdaacSMauro Carvalho Chehab if (ret) {
597*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
598*ceafdaacSMauro Carvalho Chehab return ret;
599*ceafdaacSMauro Carvalho Chehab }
600*ceafdaacSMauro Carvalho Chehab
601*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
602*ceafdaacSMauro Carvalho Chehab stat->ops->set_params(stat, new_conf);
603*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
604*ceafdaacSMauro Carvalho Chehab
605*ceafdaacSMauro Carvalho Chehab /*
606*ceafdaacSMauro Carvalho Chehab * Returning the right future config_counter for this setup, so
607*ceafdaacSMauro Carvalho Chehab * userspace can *know* when it has been applied.
608*ceafdaacSMauro Carvalho Chehab */
609*ceafdaacSMauro Carvalho Chehab user_cfg->config_counter = stat->config_counter + stat->inc_config;
610*ceafdaacSMauro Carvalho Chehab
611*ceafdaacSMauro Carvalho Chehab /* Module has a valid configuration. */
612*ceafdaacSMauro Carvalho Chehab stat->configured = 1;
613*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
614*ceafdaacSMauro Carvalho Chehab "%s: module has been successfully configured.\n",
615*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
616*ceafdaacSMauro Carvalho Chehab
617*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
618*ceafdaacSMauro Carvalho Chehab
619*ceafdaacSMauro Carvalho Chehab return 0;
620*ceafdaacSMauro Carvalho Chehab }
621*ceafdaacSMauro Carvalho Chehab
622*ceafdaacSMauro Carvalho Chehab /*
623*ceafdaacSMauro Carvalho Chehab * isp_stat_buf_process - Process statistic buffers.
624*ceafdaacSMauro Carvalho Chehab * @buf_state: points out if buffer is ready to be processed. It's necessary
625*ceafdaacSMauro Carvalho Chehab * because histogram needs to copy the data from internal memory
626*ceafdaacSMauro Carvalho Chehab * before be able to process the buffer.
627*ceafdaacSMauro Carvalho Chehab */
isp_stat_buf_process(struct ispstat * stat,int buf_state)628*ceafdaacSMauro Carvalho Chehab static int isp_stat_buf_process(struct ispstat *stat, int buf_state)
629*ceafdaacSMauro Carvalho Chehab {
630*ceafdaacSMauro Carvalho Chehab int ret = STAT_NO_BUF;
631*ceafdaacSMauro Carvalho Chehab
632*ceafdaacSMauro Carvalho Chehab if (!atomic_add_unless(&stat->buf_err, -1, 0) &&
633*ceafdaacSMauro Carvalho Chehab buf_state == STAT_BUF_DONE && stat->state == ISPSTAT_ENABLED) {
634*ceafdaacSMauro Carvalho Chehab ret = isp_stat_buf_queue(stat);
635*ceafdaacSMauro Carvalho Chehab isp_stat_buf_next(stat);
636*ceafdaacSMauro Carvalho Chehab }
637*ceafdaacSMauro Carvalho Chehab
638*ceafdaacSMauro Carvalho Chehab return ret;
639*ceafdaacSMauro Carvalho Chehab }
640*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_pcr_busy(struct ispstat * stat)641*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_pcr_busy(struct ispstat *stat)
642*ceafdaacSMauro Carvalho Chehab {
643*ceafdaacSMauro Carvalho Chehab return stat->ops->busy(stat);
644*ceafdaacSMauro Carvalho Chehab }
645*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_busy(struct ispstat * stat)646*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_busy(struct ispstat *stat)
647*ceafdaacSMauro Carvalho Chehab {
648*ceafdaacSMauro Carvalho Chehab return omap3isp_stat_pcr_busy(stat) | stat->buf_processing |
649*ceafdaacSMauro Carvalho Chehab (stat->state != ISPSTAT_DISABLED);
650*ceafdaacSMauro Carvalho Chehab }
651*ceafdaacSMauro Carvalho Chehab
652*ceafdaacSMauro Carvalho Chehab /*
653*ceafdaacSMauro Carvalho Chehab * isp_stat_pcr_enable - Disables/Enables statistic engines.
654*ceafdaacSMauro Carvalho Chehab * @pcr_enable: 0/1 - Disables/Enables the engine.
655*ceafdaacSMauro Carvalho Chehab *
656*ceafdaacSMauro Carvalho Chehab * Must be called from ISP driver when the module is idle and synchronized
657*ceafdaacSMauro Carvalho Chehab * with CCDC.
658*ceafdaacSMauro Carvalho Chehab */
isp_stat_pcr_enable(struct ispstat * stat,u8 pcr_enable)659*ceafdaacSMauro Carvalho Chehab static void isp_stat_pcr_enable(struct ispstat *stat, u8 pcr_enable)
660*ceafdaacSMauro Carvalho Chehab {
661*ceafdaacSMauro Carvalho Chehab if ((stat->state != ISPSTAT_ENABLING &&
662*ceafdaacSMauro Carvalho Chehab stat->state != ISPSTAT_ENABLED) && pcr_enable)
663*ceafdaacSMauro Carvalho Chehab /* Userspace has disabled the module. Aborting. */
664*ceafdaacSMauro Carvalho Chehab return;
665*ceafdaacSMauro Carvalho Chehab
666*ceafdaacSMauro Carvalho Chehab stat->ops->enable(stat, pcr_enable);
667*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_DISABLING && !pcr_enable)
668*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_DISABLED;
669*ceafdaacSMauro Carvalho Chehab else if (stat->state == ISPSTAT_ENABLING && pcr_enable)
670*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_ENABLED;
671*ceafdaacSMauro Carvalho Chehab }
672*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_suspend(struct ispstat * stat)673*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_suspend(struct ispstat *stat)
674*ceafdaacSMauro Carvalho Chehab {
675*ceafdaacSMauro Carvalho Chehab unsigned long flags;
676*ceafdaacSMauro Carvalho Chehab
677*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, flags);
678*ceafdaacSMauro Carvalho Chehab
679*ceafdaacSMauro Carvalho Chehab if (stat->state != ISPSTAT_DISABLED)
680*ceafdaacSMauro Carvalho Chehab stat->ops->enable(stat, 0);
681*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_ENABLED)
682*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_SUSPENDED;
683*ceafdaacSMauro Carvalho Chehab
684*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
685*ceafdaacSMauro Carvalho Chehab }
686*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_resume(struct ispstat * stat)687*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_resume(struct ispstat *stat)
688*ceafdaacSMauro Carvalho Chehab {
689*ceafdaacSMauro Carvalho Chehab /* Module will be re-enabled with its pipeline */
690*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_SUSPENDED)
691*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_ENABLING;
692*ceafdaacSMauro Carvalho Chehab }
693*ceafdaacSMauro Carvalho Chehab
isp_stat_try_enable(struct ispstat * stat)694*ceafdaacSMauro Carvalho Chehab static void isp_stat_try_enable(struct ispstat *stat)
695*ceafdaacSMauro Carvalho Chehab {
696*ceafdaacSMauro Carvalho Chehab unsigned long irqflags;
697*ceafdaacSMauro Carvalho Chehab
698*ceafdaacSMauro Carvalho Chehab if (stat->priv == NULL)
699*ceafdaacSMauro Carvalho Chehab /* driver wasn't initialised */
700*ceafdaacSMauro Carvalho Chehab return;
701*ceafdaacSMauro Carvalho Chehab
702*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
703*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_ENABLING && !stat->buf_processing &&
704*ceafdaacSMauro Carvalho Chehab stat->buf_alloc_size) {
705*ceafdaacSMauro Carvalho Chehab /*
706*ceafdaacSMauro Carvalho Chehab * Userspace's requested to enable the engine but it wasn't yet.
707*ceafdaacSMauro Carvalho Chehab * Let's do that now.
708*ceafdaacSMauro Carvalho Chehab */
709*ceafdaacSMauro Carvalho Chehab stat->update = 1;
710*ceafdaacSMauro Carvalho Chehab isp_stat_buf_next(stat);
711*ceafdaacSMauro Carvalho Chehab stat->ops->setup_regs(stat, stat->priv);
712*ceafdaacSMauro Carvalho Chehab isp_stat_buf_insert_magic(stat, stat->active_buf);
713*ceafdaacSMauro Carvalho Chehab
714*ceafdaacSMauro Carvalho Chehab /*
715*ceafdaacSMauro Carvalho Chehab * H3A module has some hw issues which forces the driver to
716*ceafdaacSMauro Carvalho Chehab * ignore next buffers even if it was disabled in the meantime.
717*ceafdaacSMauro Carvalho Chehab * On the other hand, Histogram shouldn't ignore buffers anymore
718*ceafdaacSMauro Carvalho Chehab * if it's being enabled.
719*ceafdaacSMauro Carvalho Chehab */
720*ceafdaacSMauro Carvalho Chehab if (!IS_H3A(stat))
721*ceafdaacSMauro Carvalho Chehab atomic_set(&stat->buf_err, 0);
722*ceafdaacSMauro Carvalho Chehab
723*ceafdaacSMauro Carvalho Chehab isp_stat_pcr_enable(stat, 1);
724*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
725*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: module is enabled.\n",
726*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
727*ceafdaacSMauro Carvalho Chehab } else {
728*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
729*ceafdaacSMauro Carvalho Chehab }
730*ceafdaacSMauro Carvalho Chehab }
731*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_isr_frame_sync(struct ispstat * stat)732*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_isr_frame_sync(struct ispstat *stat)
733*ceafdaacSMauro Carvalho Chehab {
734*ceafdaacSMauro Carvalho Chehab isp_stat_try_enable(stat);
735*ceafdaacSMauro Carvalho Chehab }
736*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_sbl_overflow(struct ispstat * stat)737*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_sbl_overflow(struct ispstat *stat)
738*ceafdaacSMauro Carvalho Chehab {
739*ceafdaacSMauro Carvalho Chehab unsigned long irqflags;
740*ceafdaacSMauro Carvalho Chehab
741*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
742*ceafdaacSMauro Carvalho Chehab /*
743*ceafdaacSMauro Carvalho Chehab * Due to a H3A hw issue which prevents the next buffer to start from
744*ceafdaacSMauro Carvalho Chehab * the correct memory address, 2 buffers must be ignored.
745*ceafdaacSMauro Carvalho Chehab */
746*ceafdaacSMauro Carvalho Chehab atomic_set(&stat->buf_err, 2);
747*ceafdaacSMauro Carvalho Chehab
748*ceafdaacSMauro Carvalho Chehab /*
749*ceafdaacSMauro Carvalho Chehab * If more than one SBL overflow happen in a row, H3A module may access
750*ceafdaacSMauro Carvalho Chehab * invalid memory region.
751*ceafdaacSMauro Carvalho Chehab * stat->sbl_ovl_recover is set to tell to the driver to temporarily use
752*ceafdaacSMauro Carvalho Chehab * a soft configuration which helps to avoid consecutive overflows.
753*ceafdaacSMauro Carvalho Chehab */
754*ceafdaacSMauro Carvalho Chehab if (stat->recover_priv)
755*ceafdaacSMauro Carvalho Chehab stat->sbl_ovl_recover = 1;
756*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
757*ceafdaacSMauro Carvalho Chehab }
758*ceafdaacSMauro Carvalho Chehab
759*ceafdaacSMauro Carvalho Chehab /*
760*ceafdaacSMauro Carvalho Chehab * omap3isp_stat_enable - Disable/Enable statistic engine as soon as possible
761*ceafdaacSMauro Carvalho Chehab * @enable: 0/1 - Disables/Enables the engine.
762*ceafdaacSMauro Carvalho Chehab *
763*ceafdaacSMauro Carvalho Chehab * Client should configure all the module registers before this.
764*ceafdaacSMauro Carvalho Chehab * This function can be called from a userspace request.
765*ceafdaacSMauro Carvalho Chehab */
omap3isp_stat_enable(struct ispstat * stat,u8 enable)766*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_enable(struct ispstat *stat, u8 enable)
767*ceafdaacSMauro Carvalho Chehab {
768*ceafdaacSMauro Carvalho Chehab unsigned long irqflags;
769*ceafdaacSMauro Carvalho Chehab
770*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: user wants to %s module.\n",
771*ceafdaacSMauro Carvalho Chehab stat->subdev.name, enable ? "enable" : "disable");
772*ceafdaacSMauro Carvalho Chehab
773*ceafdaacSMauro Carvalho Chehab /* Prevent enabling while configuring */
774*ceafdaacSMauro Carvalho Chehab mutex_lock(&stat->ioctl_lock);
775*ceafdaacSMauro Carvalho Chehab
776*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
777*ceafdaacSMauro Carvalho Chehab
778*ceafdaacSMauro Carvalho Chehab if (!stat->configured && enable) {
779*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
780*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
781*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
782*ceafdaacSMauro Carvalho Chehab "%s: cannot enable module as it's never been successfully configured so far.\n",
783*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
784*ceafdaacSMauro Carvalho Chehab return -EINVAL;
785*ceafdaacSMauro Carvalho Chehab }
786*ceafdaacSMauro Carvalho Chehab
787*ceafdaacSMauro Carvalho Chehab if (enable) {
788*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_DISABLING)
789*ceafdaacSMauro Carvalho Chehab /* Previous disabling request wasn't done yet */
790*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_ENABLED;
791*ceafdaacSMauro Carvalho Chehab else if (stat->state == ISPSTAT_DISABLED)
792*ceafdaacSMauro Carvalho Chehab /* Module is now being enabled */
793*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_ENABLING;
794*ceafdaacSMauro Carvalho Chehab } else {
795*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_ENABLING) {
796*ceafdaacSMauro Carvalho Chehab /* Previous enabling request wasn't done yet */
797*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_DISABLED;
798*ceafdaacSMauro Carvalho Chehab } else if (stat->state == ISPSTAT_ENABLED) {
799*ceafdaacSMauro Carvalho Chehab /* Module is now being disabled */
800*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_DISABLING;
801*ceafdaacSMauro Carvalho Chehab isp_stat_buf_clear(stat);
802*ceafdaacSMauro Carvalho Chehab }
803*ceafdaacSMauro Carvalho Chehab }
804*ceafdaacSMauro Carvalho Chehab
805*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
806*ceafdaacSMauro Carvalho Chehab mutex_unlock(&stat->ioctl_lock);
807*ceafdaacSMauro Carvalho Chehab
808*ceafdaacSMauro Carvalho Chehab return 0;
809*ceafdaacSMauro Carvalho Chehab }
810*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_s_stream(struct v4l2_subdev * subdev,int enable)811*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable)
812*ceafdaacSMauro Carvalho Chehab {
813*ceafdaacSMauro Carvalho Chehab struct ispstat *stat = v4l2_get_subdevdata(subdev);
814*ceafdaacSMauro Carvalho Chehab
815*ceafdaacSMauro Carvalho Chehab if (enable) {
816*ceafdaacSMauro Carvalho Chehab /*
817*ceafdaacSMauro Carvalho Chehab * Only set enable PCR bit if the module was previously
818*ceafdaacSMauro Carvalho Chehab * enabled through ioctl.
819*ceafdaacSMauro Carvalho Chehab */
820*ceafdaacSMauro Carvalho Chehab isp_stat_try_enable(stat);
821*ceafdaacSMauro Carvalho Chehab } else {
822*ceafdaacSMauro Carvalho Chehab unsigned long flags;
823*ceafdaacSMauro Carvalho Chehab /* Disable PCR bit and config enable field */
824*ceafdaacSMauro Carvalho Chehab omap3isp_stat_enable(stat, 0);
825*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, flags);
826*ceafdaacSMauro Carvalho Chehab stat->ops->enable(stat, 0);
827*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, flags);
828*ceafdaacSMauro Carvalho Chehab
829*ceafdaacSMauro Carvalho Chehab /*
830*ceafdaacSMauro Carvalho Chehab * If module isn't busy, a new interrupt may come or not to
831*ceafdaacSMauro Carvalho Chehab * set the state to DISABLED. As Histogram needs to read its
832*ceafdaacSMauro Carvalho Chehab * internal memory to clear it, let interrupt handler
833*ceafdaacSMauro Carvalho Chehab * responsible of changing state to DISABLED. If the last
834*ceafdaacSMauro Carvalho Chehab * interrupt is coming, it's still safe as the handler will
835*ceafdaacSMauro Carvalho Chehab * ignore the second time when state is already set to DISABLED.
836*ceafdaacSMauro Carvalho Chehab * It's necessary to synchronize Histogram with streamoff, once
837*ceafdaacSMauro Carvalho Chehab * the module may be considered idle before last SDMA transfer
838*ceafdaacSMauro Carvalho Chehab * starts if we return here.
839*ceafdaacSMauro Carvalho Chehab */
840*ceafdaacSMauro Carvalho Chehab if (!omap3isp_stat_pcr_busy(stat))
841*ceafdaacSMauro Carvalho Chehab omap3isp_stat_isr(stat);
842*ceafdaacSMauro Carvalho Chehab
843*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev, "%s: module is being disabled\n",
844*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
845*ceafdaacSMauro Carvalho Chehab }
846*ceafdaacSMauro Carvalho Chehab
847*ceafdaacSMauro Carvalho Chehab return 0;
848*ceafdaacSMauro Carvalho Chehab }
849*ceafdaacSMauro Carvalho Chehab
850*ceafdaacSMauro Carvalho Chehab /*
851*ceafdaacSMauro Carvalho Chehab * __stat_isr - Interrupt handler for statistic drivers
852*ceafdaacSMauro Carvalho Chehab */
__stat_isr(struct ispstat * stat,int from_dma)853*ceafdaacSMauro Carvalho Chehab static void __stat_isr(struct ispstat *stat, int from_dma)
854*ceafdaacSMauro Carvalho Chehab {
855*ceafdaacSMauro Carvalho Chehab int ret = STAT_BUF_DONE;
856*ceafdaacSMauro Carvalho Chehab int buf_processing;
857*ceafdaacSMauro Carvalho Chehab unsigned long irqflags;
858*ceafdaacSMauro Carvalho Chehab struct isp_pipeline *pipe;
859*ceafdaacSMauro Carvalho Chehab
860*ceafdaacSMauro Carvalho Chehab /*
861*ceafdaacSMauro Carvalho Chehab * stat->buf_processing must be set before disable module. It's
862*ceafdaacSMauro Carvalho Chehab * necessary to not inform too early the buffers aren't busy in case
863*ceafdaacSMauro Carvalho Chehab * of SDMA is going to be used.
864*ceafdaacSMauro Carvalho Chehab */
865*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
866*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_DISABLED) {
867*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
868*ceafdaacSMauro Carvalho Chehab return;
869*ceafdaacSMauro Carvalho Chehab }
870*ceafdaacSMauro Carvalho Chehab buf_processing = stat->buf_processing;
871*ceafdaacSMauro Carvalho Chehab stat->buf_processing = 1;
872*ceafdaacSMauro Carvalho Chehab stat->ops->enable(stat, 0);
873*ceafdaacSMauro Carvalho Chehab
874*ceafdaacSMauro Carvalho Chehab if (buf_processing && !from_dma) {
875*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_ENABLED) {
876*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
877*ceafdaacSMauro Carvalho Chehab dev_err(stat->isp->dev,
878*ceafdaacSMauro Carvalho Chehab "%s: interrupt occurred when module was still processing a buffer.\n",
879*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
880*ceafdaacSMauro Carvalho Chehab ret = STAT_NO_BUF;
881*ceafdaacSMauro Carvalho Chehab goto out;
882*ceafdaacSMauro Carvalho Chehab } else {
883*ceafdaacSMauro Carvalho Chehab /*
884*ceafdaacSMauro Carvalho Chehab * Interrupt handler was called from streamoff when
885*ceafdaacSMauro Carvalho Chehab * the module wasn't busy anymore to ensure it is being
886*ceafdaacSMauro Carvalho Chehab * disabled after process last buffer. If such buffer
887*ceafdaacSMauro Carvalho Chehab * processing has already started, no need to do
888*ceafdaacSMauro Carvalho Chehab * anything else.
889*ceafdaacSMauro Carvalho Chehab */
890*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
891*ceafdaacSMauro Carvalho Chehab return;
892*ceafdaacSMauro Carvalho Chehab }
893*ceafdaacSMauro Carvalho Chehab }
894*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
895*ceafdaacSMauro Carvalho Chehab
896*ceafdaacSMauro Carvalho Chehab /* If it's busy we can't process this buffer anymore */
897*ceafdaacSMauro Carvalho Chehab if (!omap3isp_stat_pcr_busy(stat)) {
898*ceafdaacSMauro Carvalho Chehab if (!from_dma && stat->ops->buf_process)
899*ceafdaacSMauro Carvalho Chehab /* Module still need to copy data to buffer. */
900*ceafdaacSMauro Carvalho Chehab ret = stat->ops->buf_process(stat);
901*ceafdaacSMauro Carvalho Chehab if (ret == STAT_BUF_WAITING_DMA)
902*ceafdaacSMauro Carvalho Chehab /* Buffer is not ready yet */
903*ceafdaacSMauro Carvalho Chehab return;
904*ceafdaacSMauro Carvalho Chehab
905*ceafdaacSMauro Carvalho Chehab spin_lock_irqsave(&stat->isp->stat_lock, irqflags);
906*ceafdaacSMauro Carvalho Chehab
907*ceafdaacSMauro Carvalho Chehab /*
908*ceafdaacSMauro Carvalho Chehab * Histogram needs to read its internal memory to clear it
909*ceafdaacSMauro Carvalho Chehab * before be disabled. For that reason, common statistic layer
910*ceafdaacSMauro Carvalho Chehab * can return only after call stat's buf_process() operator.
911*ceafdaacSMauro Carvalho Chehab */
912*ceafdaacSMauro Carvalho Chehab if (stat->state == ISPSTAT_DISABLING) {
913*ceafdaacSMauro Carvalho Chehab stat->state = ISPSTAT_DISABLED;
914*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
915*ceafdaacSMauro Carvalho Chehab stat->buf_processing = 0;
916*ceafdaacSMauro Carvalho Chehab return;
917*ceafdaacSMauro Carvalho Chehab }
918*ceafdaacSMauro Carvalho Chehab pipe = to_isp_pipeline(&stat->subdev.entity);
919*ceafdaacSMauro Carvalho Chehab stat->frame_number = atomic_read(&pipe->frame_number);
920*ceafdaacSMauro Carvalho Chehab
921*ceafdaacSMauro Carvalho Chehab /*
922*ceafdaacSMauro Carvalho Chehab * Before this point, 'ret' stores the buffer's status if it's
923*ceafdaacSMauro Carvalho Chehab * ready to be processed. Afterwards, it holds the status if
924*ceafdaacSMauro Carvalho Chehab * it was processed successfully.
925*ceafdaacSMauro Carvalho Chehab */
926*ceafdaacSMauro Carvalho Chehab ret = isp_stat_buf_process(stat, ret);
927*ceafdaacSMauro Carvalho Chehab
928*ceafdaacSMauro Carvalho Chehab if (likely(!stat->sbl_ovl_recover)) {
929*ceafdaacSMauro Carvalho Chehab stat->ops->setup_regs(stat, stat->priv);
930*ceafdaacSMauro Carvalho Chehab } else {
931*ceafdaacSMauro Carvalho Chehab /*
932*ceafdaacSMauro Carvalho Chehab * Using recover config to increase the chance to have
933*ceafdaacSMauro Carvalho Chehab * a good buffer processing and make the H3A module to
934*ceafdaacSMauro Carvalho Chehab * go back to a valid state.
935*ceafdaacSMauro Carvalho Chehab */
936*ceafdaacSMauro Carvalho Chehab stat->update = 1;
937*ceafdaacSMauro Carvalho Chehab stat->ops->setup_regs(stat, stat->recover_priv);
938*ceafdaacSMauro Carvalho Chehab stat->sbl_ovl_recover = 0;
939*ceafdaacSMauro Carvalho Chehab
940*ceafdaacSMauro Carvalho Chehab /*
941*ceafdaacSMauro Carvalho Chehab * Set 'update' in case of the module needs to use
942*ceafdaacSMauro Carvalho Chehab * regular configuration after next buffer.
943*ceafdaacSMauro Carvalho Chehab */
944*ceafdaacSMauro Carvalho Chehab stat->update = 1;
945*ceafdaacSMauro Carvalho Chehab }
946*ceafdaacSMauro Carvalho Chehab
947*ceafdaacSMauro Carvalho Chehab isp_stat_buf_insert_magic(stat, stat->active_buf);
948*ceafdaacSMauro Carvalho Chehab
949*ceafdaacSMauro Carvalho Chehab /*
950*ceafdaacSMauro Carvalho Chehab * Hack: H3A modules may access invalid memory address or send
951*ceafdaacSMauro Carvalho Chehab * corrupted data to userspace if more than 1 SBL overflow
952*ceafdaacSMauro Carvalho Chehab * happens in a row without re-writing its buffer's start memory
953*ceafdaacSMauro Carvalho Chehab * address in the meantime. Such situation is avoided if the
954*ceafdaacSMauro Carvalho Chehab * module is not immediately re-enabled when the ISR misses the
955*ceafdaacSMauro Carvalho Chehab * timing to process the buffer and to setup the registers.
956*ceafdaacSMauro Carvalho Chehab * Because of that, pcr_enable(1) was moved to inside this 'if'
957*ceafdaacSMauro Carvalho Chehab * block. But the next interruption will still happen as during
958*ceafdaacSMauro Carvalho Chehab * pcr_enable(0) the module was busy.
959*ceafdaacSMauro Carvalho Chehab */
960*ceafdaacSMauro Carvalho Chehab isp_stat_pcr_enable(stat, 1);
961*ceafdaacSMauro Carvalho Chehab spin_unlock_irqrestore(&stat->isp->stat_lock, irqflags);
962*ceafdaacSMauro Carvalho Chehab } else {
963*ceafdaacSMauro Carvalho Chehab /*
964*ceafdaacSMauro Carvalho Chehab * If a SBL overflow occurs and the H3A driver misses the timing
965*ceafdaacSMauro Carvalho Chehab * to process the buffer, stat->buf_err is set and won't be
966*ceafdaacSMauro Carvalho Chehab * cleared now. So the next buffer will be correctly ignored.
967*ceafdaacSMauro Carvalho Chehab * It's necessary due to a hw issue which makes the next H3A
968*ceafdaacSMauro Carvalho Chehab * buffer to start from the memory address where the previous
969*ceafdaacSMauro Carvalho Chehab * one stopped, instead of start where it was configured to.
970*ceafdaacSMauro Carvalho Chehab * Do not "stat->buf_err = 0" here.
971*ceafdaacSMauro Carvalho Chehab */
972*ceafdaacSMauro Carvalho Chehab
973*ceafdaacSMauro Carvalho Chehab if (stat->ops->buf_process)
974*ceafdaacSMauro Carvalho Chehab /*
975*ceafdaacSMauro Carvalho Chehab * Driver may need to erase current data prior to
976*ceafdaacSMauro Carvalho Chehab * process a new buffer. If it misses the timing, the
977*ceafdaacSMauro Carvalho Chehab * next buffer might be wrong. So should be ignored.
978*ceafdaacSMauro Carvalho Chehab * It happens only for Histogram.
979*ceafdaacSMauro Carvalho Chehab */
980*ceafdaacSMauro Carvalho Chehab atomic_set(&stat->buf_err, 1);
981*ceafdaacSMauro Carvalho Chehab
982*ceafdaacSMauro Carvalho Chehab ret = STAT_NO_BUF;
983*ceafdaacSMauro Carvalho Chehab dev_dbg(stat->isp->dev,
984*ceafdaacSMauro Carvalho Chehab "%s: cannot process buffer, device is busy.\n",
985*ceafdaacSMauro Carvalho Chehab stat->subdev.name);
986*ceafdaacSMauro Carvalho Chehab }
987*ceafdaacSMauro Carvalho Chehab
988*ceafdaacSMauro Carvalho Chehab out:
989*ceafdaacSMauro Carvalho Chehab stat->buf_processing = 0;
990*ceafdaacSMauro Carvalho Chehab isp_stat_queue_event(stat, ret != STAT_BUF_DONE);
991*ceafdaacSMauro Carvalho Chehab }
992*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_isr(struct ispstat * stat)993*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_isr(struct ispstat *stat)
994*ceafdaacSMauro Carvalho Chehab {
995*ceafdaacSMauro Carvalho Chehab __stat_isr(stat, 0);
996*ceafdaacSMauro Carvalho Chehab }
997*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_dma_isr(struct ispstat * stat)998*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_dma_isr(struct ispstat *stat)
999*ceafdaacSMauro Carvalho Chehab {
1000*ceafdaacSMauro Carvalho Chehab __stat_isr(stat, 1);
1001*ceafdaacSMauro Carvalho Chehab }
1002*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_subscribe_event(struct v4l2_subdev * subdev,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1003*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_subscribe_event(struct v4l2_subdev *subdev,
1004*ceafdaacSMauro Carvalho Chehab struct v4l2_fh *fh,
1005*ceafdaacSMauro Carvalho Chehab struct v4l2_event_subscription *sub)
1006*ceafdaacSMauro Carvalho Chehab {
1007*ceafdaacSMauro Carvalho Chehab struct ispstat *stat = v4l2_get_subdevdata(subdev);
1008*ceafdaacSMauro Carvalho Chehab
1009*ceafdaacSMauro Carvalho Chehab if (sub->type != stat->event_type)
1010*ceafdaacSMauro Carvalho Chehab return -EINVAL;
1011*ceafdaacSMauro Carvalho Chehab
1012*ceafdaacSMauro Carvalho Chehab return v4l2_event_subscribe(fh, sub, STAT_NEVENTS, NULL);
1013*ceafdaacSMauro Carvalho Chehab }
1014*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_unsubscribe_event(struct v4l2_subdev * subdev,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1015*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_unsubscribe_event(struct v4l2_subdev *subdev,
1016*ceafdaacSMauro Carvalho Chehab struct v4l2_fh *fh,
1017*ceafdaacSMauro Carvalho Chehab struct v4l2_event_subscription *sub)
1018*ceafdaacSMauro Carvalho Chehab {
1019*ceafdaacSMauro Carvalho Chehab return v4l2_event_unsubscribe(fh, sub);
1020*ceafdaacSMauro Carvalho Chehab }
1021*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_unregister_entities(struct ispstat * stat)1022*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_unregister_entities(struct ispstat *stat)
1023*ceafdaacSMauro Carvalho Chehab {
1024*ceafdaacSMauro Carvalho Chehab v4l2_device_unregister_subdev(&stat->subdev);
1025*ceafdaacSMauro Carvalho Chehab }
1026*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_register_entities(struct ispstat * stat,struct v4l2_device * vdev)1027*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_register_entities(struct ispstat *stat,
1028*ceafdaacSMauro Carvalho Chehab struct v4l2_device *vdev)
1029*ceafdaacSMauro Carvalho Chehab {
1030*ceafdaacSMauro Carvalho Chehab stat->subdev.dev = vdev->mdev->dev;
1031*ceafdaacSMauro Carvalho Chehab
1032*ceafdaacSMauro Carvalho Chehab return v4l2_device_register_subdev(vdev, &stat->subdev);
1033*ceafdaacSMauro Carvalho Chehab }
1034*ceafdaacSMauro Carvalho Chehab
isp_stat_init_entities(struct ispstat * stat,const char * name,const struct v4l2_subdev_ops * sd_ops)1035*ceafdaacSMauro Carvalho Chehab static int isp_stat_init_entities(struct ispstat *stat, const char *name,
1036*ceafdaacSMauro Carvalho Chehab const struct v4l2_subdev_ops *sd_ops)
1037*ceafdaacSMauro Carvalho Chehab {
1038*ceafdaacSMauro Carvalho Chehab struct v4l2_subdev *subdev = &stat->subdev;
1039*ceafdaacSMauro Carvalho Chehab struct media_entity *me = &subdev->entity;
1040*ceafdaacSMauro Carvalho Chehab
1041*ceafdaacSMauro Carvalho Chehab v4l2_subdev_init(subdev, sd_ops);
1042*ceafdaacSMauro Carvalho Chehab snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "OMAP3 ISP %s", name);
1043*ceafdaacSMauro Carvalho Chehab subdev->grp_id = BIT(16); /* group ID for isp subdevs */
1044*ceafdaacSMauro Carvalho Chehab subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
1045*ceafdaacSMauro Carvalho Chehab v4l2_set_subdevdata(subdev, stat);
1046*ceafdaacSMauro Carvalho Chehab
1047*ceafdaacSMauro Carvalho Chehab stat->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
1048*ceafdaacSMauro Carvalho Chehab me->ops = NULL;
1049*ceafdaacSMauro Carvalho Chehab
1050*ceafdaacSMauro Carvalho Chehab return media_entity_pads_init(me, 1, &stat->pad);
1051*ceafdaacSMauro Carvalho Chehab }
1052*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_init(struct ispstat * stat,const char * name,const struct v4l2_subdev_ops * sd_ops)1053*ceafdaacSMauro Carvalho Chehab int omap3isp_stat_init(struct ispstat *stat, const char *name,
1054*ceafdaacSMauro Carvalho Chehab const struct v4l2_subdev_ops *sd_ops)
1055*ceafdaacSMauro Carvalho Chehab {
1056*ceafdaacSMauro Carvalho Chehab int ret;
1057*ceafdaacSMauro Carvalho Chehab
1058*ceafdaacSMauro Carvalho Chehab stat->buf = kcalloc(STAT_MAX_BUFS, sizeof(*stat->buf), GFP_KERNEL);
1059*ceafdaacSMauro Carvalho Chehab if (!stat->buf)
1060*ceafdaacSMauro Carvalho Chehab return -ENOMEM;
1061*ceafdaacSMauro Carvalho Chehab
1062*ceafdaacSMauro Carvalho Chehab isp_stat_buf_clear(stat);
1063*ceafdaacSMauro Carvalho Chehab mutex_init(&stat->ioctl_lock);
1064*ceafdaacSMauro Carvalho Chehab atomic_set(&stat->buf_err, 0);
1065*ceafdaacSMauro Carvalho Chehab
1066*ceafdaacSMauro Carvalho Chehab ret = isp_stat_init_entities(stat, name, sd_ops);
1067*ceafdaacSMauro Carvalho Chehab if (ret < 0) {
1068*ceafdaacSMauro Carvalho Chehab mutex_destroy(&stat->ioctl_lock);
1069*ceafdaacSMauro Carvalho Chehab kfree(stat->buf);
1070*ceafdaacSMauro Carvalho Chehab }
1071*ceafdaacSMauro Carvalho Chehab
1072*ceafdaacSMauro Carvalho Chehab return ret;
1073*ceafdaacSMauro Carvalho Chehab }
1074*ceafdaacSMauro Carvalho Chehab
omap3isp_stat_cleanup(struct ispstat * stat)1075*ceafdaacSMauro Carvalho Chehab void omap3isp_stat_cleanup(struct ispstat *stat)
1076*ceafdaacSMauro Carvalho Chehab {
1077*ceafdaacSMauro Carvalho Chehab media_entity_cleanup(&stat->subdev.entity);
1078*ceafdaacSMauro Carvalho Chehab mutex_destroy(&stat->ioctl_lock);
1079*ceafdaacSMauro Carvalho Chehab isp_stat_bufs_free(stat);
1080*ceafdaacSMauro Carvalho Chehab kfree(stat->buf);
1081*ceafdaacSMauro Carvalho Chehab kfree(stat->priv);
1082*ceafdaacSMauro Carvalho Chehab kfree(stat->recover_priv);
1083*ceafdaacSMauro Carvalho Chehab }
1084