1*238c84f7SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */
2*238c84f7SMauro Carvalho Chehab /*
3*238c84f7SMauro Carvalho Chehab * Copyright (C) 2012 Samsung Electronics Co., Ltd.
4*238c84f7SMauro Carvalho Chehab */
5*238c84f7SMauro Carvalho Chehab
6*238c84f7SMauro Carvalho Chehab #ifndef FIMC_LITE_H_
7*238c84f7SMauro Carvalho Chehab #define FIMC_LITE_H_
8*238c84f7SMauro Carvalho Chehab
9*238c84f7SMauro Carvalho Chehab #include <linux/sizes.h>
10*238c84f7SMauro Carvalho Chehab #include <linux/io.h>
11*238c84f7SMauro Carvalho Chehab #include <linux/irqreturn.h>
12*238c84f7SMauro Carvalho Chehab #include <linux/platform_device.h>
13*238c84f7SMauro Carvalho Chehab #include <linux/sched.h>
14*238c84f7SMauro Carvalho Chehab #include <linux/spinlock.h>
15*238c84f7SMauro Carvalho Chehab #include <linux/types.h>
16*238c84f7SMauro Carvalho Chehab #include <linux/videodev2.h>
17*238c84f7SMauro Carvalho Chehab
18*238c84f7SMauro Carvalho Chehab #include <media/media-entity.h>
19*238c84f7SMauro Carvalho Chehab #include <media/videobuf2-v4l2.h>
20*238c84f7SMauro Carvalho Chehab #include <media/v4l2-ctrls.h>
21*238c84f7SMauro Carvalho Chehab #include <media/v4l2-device.h>
22*238c84f7SMauro Carvalho Chehab #include <media/v4l2-mediabus.h>
23*238c84f7SMauro Carvalho Chehab #include <media/drv-intf/exynos-fimc.h>
24*238c84f7SMauro Carvalho Chehab
25*238c84f7SMauro Carvalho Chehab #define FIMC_LITE_DRV_NAME "exynos-fimc-lite"
26*238c84f7SMauro Carvalho Chehab #define FLITE_CLK_NAME "flite"
27*238c84f7SMauro Carvalho Chehab #define FIMC_LITE_MAX_DEVS 3
28*238c84f7SMauro Carvalho Chehab #define FLITE_REQ_BUFS_MIN 2
29*238c84f7SMauro Carvalho Chehab #define FLITE_DEFAULT_WIDTH 640
30*238c84f7SMauro Carvalho Chehab #define FLITE_DEFAULT_HEIGHT 480
31*238c84f7SMauro Carvalho Chehab
32*238c84f7SMauro Carvalho Chehab /* Bit index definitions for struct fimc_lite::state */
33*238c84f7SMauro Carvalho Chehab enum {
34*238c84f7SMauro Carvalho Chehab ST_FLITE_LPM,
35*238c84f7SMauro Carvalho Chehab ST_FLITE_PENDING,
36*238c84f7SMauro Carvalho Chehab ST_FLITE_RUN,
37*238c84f7SMauro Carvalho Chehab ST_FLITE_STREAM,
38*238c84f7SMauro Carvalho Chehab ST_FLITE_SUSPENDED,
39*238c84f7SMauro Carvalho Chehab ST_FLITE_OFF,
40*238c84f7SMauro Carvalho Chehab ST_FLITE_IN_USE,
41*238c84f7SMauro Carvalho Chehab ST_FLITE_CONFIG,
42*238c84f7SMauro Carvalho Chehab ST_SENSOR_STREAM,
43*238c84f7SMauro Carvalho Chehab };
44*238c84f7SMauro Carvalho Chehab
45*238c84f7SMauro Carvalho Chehab #define FLITE_SD_PAD_SINK 0
46*238c84f7SMauro Carvalho Chehab #define FLITE_SD_PAD_SOURCE_DMA 1
47*238c84f7SMauro Carvalho Chehab #define FLITE_SD_PAD_SOURCE_ISP 2
48*238c84f7SMauro Carvalho Chehab #define FLITE_SD_PADS_NUM 3
49*238c84f7SMauro Carvalho Chehab
50*238c84f7SMauro Carvalho Chehab /**
51*238c84f7SMauro Carvalho Chehab * struct flite_drvdata - FIMC-LITE IP variant data structure
52*238c84f7SMauro Carvalho Chehab * @max_width: maximum camera interface input width in pixels
53*238c84f7SMauro Carvalho Chehab * @max_height: maximum camera interface input height in pixels
54*238c84f7SMauro Carvalho Chehab * @out_width_align: minimum output width alignment in pixels
55*238c84f7SMauro Carvalho Chehab * @win_hor_offs_align: minimum camera interface crop window horizontal
56*238c84f7SMauro Carvalho Chehab * offset alignment in pixels
57*238c84f7SMauro Carvalho Chehab * @out_hor_offs_align: minimum output DMA compose rectangle horizontal
58*238c84f7SMauro Carvalho Chehab * offset alignment in pixels
59*238c84f7SMauro Carvalho Chehab * @max_dma_bufs: number of output DMA buffer start address registers
60*238c84f7SMauro Carvalho Chehab * @num_instances: total number of FIMC-LITE IP instances available
61*238c84f7SMauro Carvalho Chehab */
62*238c84f7SMauro Carvalho Chehab struct flite_drvdata {
63*238c84f7SMauro Carvalho Chehab unsigned short max_width;
64*238c84f7SMauro Carvalho Chehab unsigned short max_height;
65*238c84f7SMauro Carvalho Chehab unsigned short out_width_align;
66*238c84f7SMauro Carvalho Chehab unsigned short win_hor_offs_align;
67*238c84f7SMauro Carvalho Chehab unsigned short out_hor_offs_align;
68*238c84f7SMauro Carvalho Chehab unsigned short max_dma_bufs;
69*238c84f7SMauro Carvalho Chehab unsigned short num_instances;
70*238c84f7SMauro Carvalho Chehab };
71*238c84f7SMauro Carvalho Chehab
72*238c84f7SMauro Carvalho Chehab struct fimc_lite_events {
73*238c84f7SMauro Carvalho Chehab unsigned int data_overflow;
74*238c84f7SMauro Carvalho Chehab };
75*238c84f7SMauro Carvalho Chehab
76*238c84f7SMauro Carvalho Chehab #define FLITE_MAX_PLANES 1
77*238c84f7SMauro Carvalho Chehab
78*238c84f7SMauro Carvalho Chehab /**
79*238c84f7SMauro Carvalho Chehab * struct flite_frame - source/target frame properties
80*238c84f7SMauro Carvalho Chehab * @f_width: full pixel width
81*238c84f7SMauro Carvalho Chehab * @f_height: full pixel height
82*238c84f7SMauro Carvalho Chehab * @rect: crop/composition rectangle
83*238c84f7SMauro Carvalho Chehab * @fmt: pointer to pixel format description data structure
84*238c84f7SMauro Carvalho Chehab */
85*238c84f7SMauro Carvalho Chehab struct flite_frame {
86*238c84f7SMauro Carvalho Chehab u16 f_width;
87*238c84f7SMauro Carvalho Chehab u16 f_height;
88*238c84f7SMauro Carvalho Chehab struct v4l2_rect rect;
89*238c84f7SMauro Carvalho Chehab const struct fimc_fmt *fmt;
90*238c84f7SMauro Carvalho Chehab };
91*238c84f7SMauro Carvalho Chehab
92*238c84f7SMauro Carvalho Chehab /**
93*238c84f7SMauro Carvalho Chehab * struct flite_buffer - video buffer structure
94*238c84f7SMauro Carvalho Chehab * @vb: vb2 buffer
95*238c84f7SMauro Carvalho Chehab * @list: list head for the buffers queue
96*238c84f7SMauro Carvalho Chehab * @addr: DMA buffer start address
97*238c84f7SMauro Carvalho Chehab * @index: DMA start address register's index
98*238c84f7SMauro Carvalho Chehab */
99*238c84f7SMauro Carvalho Chehab struct flite_buffer {
100*238c84f7SMauro Carvalho Chehab struct vb2_v4l2_buffer vb;
101*238c84f7SMauro Carvalho Chehab struct list_head list;
102*238c84f7SMauro Carvalho Chehab dma_addr_t addr;
103*238c84f7SMauro Carvalho Chehab unsigned short index;
104*238c84f7SMauro Carvalho Chehab };
105*238c84f7SMauro Carvalho Chehab
106*238c84f7SMauro Carvalho Chehab /**
107*238c84f7SMauro Carvalho Chehab * struct fimc_lite - fimc lite structure
108*238c84f7SMauro Carvalho Chehab * @pdev: pointer to FIMC-LITE platform device
109*238c84f7SMauro Carvalho Chehab * @dd: SoC specific driver data structure
110*238c84f7SMauro Carvalho Chehab * @ve: exynos video device entity structure
111*238c84f7SMauro Carvalho Chehab * @v4l2_dev: pointer to top the level v4l2_device
112*238c84f7SMauro Carvalho Chehab * @fh: v4l2 file handle
113*238c84f7SMauro Carvalho Chehab * @subdev: FIMC-LITE subdev
114*238c84f7SMauro Carvalho Chehab * @vd_pad: media (sink) pad for the capture video node
115*238c84f7SMauro Carvalho Chehab * @subdev_pads: the subdev media pads
116*238c84f7SMauro Carvalho Chehab * @sensor: sensor subdev attached to FIMC-LITE directly or through MIPI-CSIS
117*238c84f7SMauro Carvalho Chehab * @ctrl_handler: v4l2 control handler
118*238c84f7SMauro Carvalho Chehab * @test_pattern: test pattern controls
119*238c84f7SMauro Carvalho Chehab * @index: FIMC-LITE platform device index
120*238c84f7SMauro Carvalho Chehab * @pipeline: video capture pipeline data structure
121*238c84f7SMauro Carvalho Chehab * @pipeline_ops: media pipeline ops for the video node driver
122*238c84f7SMauro Carvalho Chehab * @slock: spinlock protecting this data structure and the hw registers
123*238c84f7SMauro Carvalho Chehab * @lock: mutex serializing video device and the subdev operations
124*238c84f7SMauro Carvalho Chehab * @clock: FIMC-LITE gate clock
125*238c84f7SMauro Carvalho Chehab * @regs: memory mapped io registers
126*238c84f7SMauro Carvalho Chehab * @irq_queue: interrupt handler waitqueue
127*238c84f7SMauro Carvalho Chehab * @payload: image size in bytes (w x h x bpp)
128*238c84f7SMauro Carvalho Chehab * @inp_frame: camera input frame structure
129*238c84f7SMauro Carvalho Chehab * @out_frame: DMA output frame structure
130*238c84f7SMauro Carvalho Chehab * @out_path: output data path (DMA or FIFO)
131*238c84f7SMauro Carvalho Chehab * @source_subdev_grp_id: source subdev group id
132*238c84f7SMauro Carvalho Chehab * @state: driver state flags
133*238c84f7SMauro Carvalho Chehab * @pending_buf_q: pending buffers queue head
134*238c84f7SMauro Carvalho Chehab * @active_buf_q: the queue head of buffers scheduled in hardware
135*238c84f7SMauro Carvalho Chehab * @vb_queue: vb2 buffers queue
136*238c84f7SMauro Carvalho Chehab * @buf_index: helps to keep track of the DMA start address register index
137*238c84f7SMauro Carvalho Chehab * @active_buf_count: number of video buffers scheduled in hardware
138*238c84f7SMauro Carvalho Chehab * @frame_count: the captured frames counter
139*238c84f7SMauro Carvalho Chehab * @reqbufs_count: the number of buffers requested with REQBUFS ioctl
140*238c84f7SMauro Carvalho Chehab * @events: event info
141*238c84f7SMauro Carvalho Chehab * @streaming: is streaming in progress?
142*238c84f7SMauro Carvalho Chehab */
143*238c84f7SMauro Carvalho Chehab struct fimc_lite {
144*238c84f7SMauro Carvalho Chehab struct platform_device *pdev;
145*238c84f7SMauro Carvalho Chehab struct flite_drvdata *dd;
146*238c84f7SMauro Carvalho Chehab struct exynos_video_entity ve;
147*238c84f7SMauro Carvalho Chehab struct v4l2_device *v4l2_dev;
148*238c84f7SMauro Carvalho Chehab struct v4l2_fh fh;
149*238c84f7SMauro Carvalho Chehab struct v4l2_subdev subdev;
150*238c84f7SMauro Carvalho Chehab struct media_pad vd_pad;
151*238c84f7SMauro Carvalho Chehab struct media_pad subdev_pads[FLITE_SD_PADS_NUM];
152*238c84f7SMauro Carvalho Chehab struct v4l2_subdev *sensor;
153*238c84f7SMauro Carvalho Chehab struct v4l2_ctrl_handler ctrl_handler;
154*238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *test_pattern;
155*238c84f7SMauro Carvalho Chehab int index;
156*238c84f7SMauro Carvalho Chehab
157*238c84f7SMauro Carvalho Chehab struct mutex lock;
158*238c84f7SMauro Carvalho Chehab spinlock_t slock;
159*238c84f7SMauro Carvalho Chehab
160*238c84f7SMauro Carvalho Chehab struct clk *clock;
161*238c84f7SMauro Carvalho Chehab void __iomem *regs;
162*238c84f7SMauro Carvalho Chehab wait_queue_head_t irq_queue;
163*238c84f7SMauro Carvalho Chehab
164*238c84f7SMauro Carvalho Chehab unsigned long payload[FLITE_MAX_PLANES];
165*238c84f7SMauro Carvalho Chehab struct flite_frame inp_frame;
166*238c84f7SMauro Carvalho Chehab struct flite_frame out_frame;
167*238c84f7SMauro Carvalho Chehab atomic_t out_path;
168*238c84f7SMauro Carvalho Chehab unsigned int source_subdev_grp_id;
169*238c84f7SMauro Carvalho Chehab
170*238c84f7SMauro Carvalho Chehab unsigned long state;
171*238c84f7SMauro Carvalho Chehab struct list_head pending_buf_q;
172*238c84f7SMauro Carvalho Chehab struct list_head active_buf_q;
173*238c84f7SMauro Carvalho Chehab struct vb2_queue vb_queue;
174*238c84f7SMauro Carvalho Chehab unsigned short buf_index;
175*238c84f7SMauro Carvalho Chehab unsigned int frame_count;
176*238c84f7SMauro Carvalho Chehab unsigned int reqbufs_count;
177*238c84f7SMauro Carvalho Chehab
178*238c84f7SMauro Carvalho Chehab struct fimc_lite_events events;
179*238c84f7SMauro Carvalho Chehab bool streaming;
180*238c84f7SMauro Carvalho Chehab };
181*238c84f7SMauro Carvalho Chehab
fimc_lite_active(struct fimc_lite * fimc)182*238c84f7SMauro Carvalho Chehab static inline bool fimc_lite_active(struct fimc_lite *fimc)
183*238c84f7SMauro Carvalho Chehab {
184*238c84f7SMauro Carvalho Chehab unsigned long flags;
185*238c84f7SMauro Carvalho Chehab bool ret;
186*238c84f7SMauro Carvalho Chehab
187*238c84f7SMauro Carvalho Chehab spin_lock_irqsave(&fimc->slock, flags);
188*238c84f7SMauro Carvalho Chehab ret = fimc->state & (1 << ST_FLITE_RUN) ||
189*238c84f7SMauro Carvalho Chehab fimc->state & (1 << ST_FLITE_PENDING);
190*238c84f7SMauro Carvalho Chehab spin_unlock_irqrestore(&fimc->slock, flags);
191*238c84f7SMauro Carvalho Chehab return ret;
192*238c84f7SMauro Carvalho Chehab }
193*238c84f7SMauro Carvalho Chehab
fimc_lite_active_queue_add(struct fimc_lite * dev,struct flite_buffer * buf)194*238c84f7SMauro Carvalho Chehab static inline void fimc_lite_active_queue_add(struct fimc_lite *dev,
195*238c84f7SMauro Carvalho Chehab struct flite_buffer *buf)
196*238c84f7SMauro Carvalho Chehab {
197*238c84f7SMauro Carvalho Chehab list_add_tail(&buf->list, &dev->active_buf_q);
198*238c84f7SMauro Carvalho Chehab }
199*238c84f7SMauro Carvalho Chehab
fimc_lite_active_queue_pop(struct fimc_lite * dev)200*238c84f7SMauro Carvalho Chehab static inline struct flite_buffer *fimc_lite_active_queue_pop(
201*238c84f7SMauro Carvalho Chehab struct fimc_lite *dev)
202*238c84f7SMauro Carvalho Chehab {
203*238c84f7SMauro Carvalho Chehab struct flite_buffer *buf = list_entry(dev->active_buf_q.next,
204*238c84f7SMauro Carvalho Chehab struct flite_buffer, list);
205*238c84f7SMauro Carvalho Chehab list_del(&buf->list);
206*238c84f7SMauro Carvalho Chehab return buf;
207*238c84f7SMauro Carvalho Chehab }
208*238c84f7SMauro Carvalho Chehab
fimc_lite_pending_queue_add(struct fimc_lite * dev,struct flite_buffer * buf)209*238c84f7SMauro Carvalho Chehab static inline void fimc_lite_pending_queue_add(struct fimc_lite *dev,
210*238c84f7SMauro Carvalho Chehab struct flite_buffer *buf)
211*238c84f7SMauro Carvalho Chehab {
212*238c84f7SMauro Carvalho Chehab list_add_tail(&buf->list, &dev->pending_buf_q);
213*238c84f7SMauro Carvalho Chehab }
214*238c84f7SMauro Carvalho Chehab
fimc_lite_pending_queue_pop(struct fimc_lite * dev)215*238c84f7SMauro Carvalho Chehab static inline struct flite_buffer *fimc_lite_pending_queue_pop(
216*238c84f7SMauro Carvalho Chehab struct fimc_lite *dev)
217*238c84f7SMauro Carvalho Chehab {
218*238c84f7SMauro Carvalho Chehab struct flite_buffer *buf = list_entry(dev->pending_buf_q.next,
219*238c84f7SMauro Carvalho Chehab struct flite_buffer, list);
220*238c84f7SMauro Carvalho Chehab list_del(&buf->list);
221*238c84f7SMauro Carvalho Chehab return buf;
222*238c84f7SMauro Carvalho Chehab }
223*238c84f7SMauro Carvalho Chehab
224*238c84f7SMauro Carvalho Chehab #endif /* FIMC_LITE_H_ */
225