1*238c84f7SMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0-only
2*238c84f7SMauro Carvalho Chehab /*
3*238c84f7SMauro Carvalho Chehab * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4*238c84f7SMauro Carvalho Chehab *
5*238c84f7SMauro Carvalho Chehab * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6*238c84f7SMauro Carvalho Chehab *
7*238c84f7SMauro Carvalho Chehab * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
8*238c84f7SMauro Carvalho Chehab * Younghwan Joo <yhwan.joo@samsung.com>
9*238c84f7SMauro Carvalho Chehab */
10*238c84f7SMauro Carvalho Chehab #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
11*238c84f7SMauro Carvalho Chehab
12*238c84f7SMauro Carvalho Chehab #include <linux/device.h>
13*238c84f7SMauro Carvalho Chehab #include <linux/errno.h>
14*238c84f7SMauro Carvalho Chehab #include <linux/kernel.h>
15*238c84f7SMauro Carvalho Chehab #include <linux/list.h>
16*238c84f7SMauro Carvalho Chehab #include <linux/module.h>
17*238c84f7SMauro Carvalho Chehab #include <linux/platform_device.h>
18*238c84f7SMauro Carvalho Chehab #include <linux/printk.h>
19*238c84f7SMauro Carvalho Chehab #include <linux/pm_runtime.h>
20*238c84f7SMauro Carvalho Chehab #include <linux/slab.h>
21*238c84f7SMauro Carvalho Chehab #include <linux/types.h>
22*238c84f7SMauro Carvalho Chehab #include <media/v4l2-device.h>
23*238c84f7SMauro Carvalho Chehab
24*238c84f7SMauro Carvalho Chehab #include "media-dev.h"
25*238c84f7SMauro Carvalho Chehab #include "fimc-isp-video.h"
26*238c84f7SMauro Carvalho Chehab #include "fimc-is-command.h"
27*238c84f7SMauro Carvalho Chehab #include "fimc-is-param.h"
28*238c84f7SMauro Carvalho Chehab #include "fimc-is-regs.h"
29*238c84f7SMauro Carvalho Chehab #include "fimc-is.h"
30*238c84f7SMauro Carvalho Chehab
31*238c84f7SMauro Carvalho Chehab int fimc_isp_debug;
32*238c84f7SMauro Carvalho Chehab module_param_named(debug_isp, fimc_isp_debug, int, S_IRUGO | S_IWUSR);
33*238c84f7SMauro Carvalho Chehab
34*238c84f7SMauro Carvalho Chehab static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
35*238c84f7SMauro Carvalho Chehab {
36*238c84f7SMauro Carvalho Chehab .fourcc = V4L2_PIX_FMT_SGRBG8,
37*238c84f7SMauro Carvalho Chehab .depth = { 8 },
38*238c84f7SMauro Carvalho Chehab .color = FIMC_FMT_RAW8,
39*238c84f7SMauro Carvalho Chehab .memplanes = 1,
40*238c84f7SMauro Carvalho Chehab .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
41*238c84f7SMauro Carvalho Chehab }, {
42*238c84f7SMauro Carvalho Chehab .fourcc = V4L2_PIX_FMT_SGRBG10,
43*238c84f7SMauro Carvalho Chehab .depth = { 10 },
44*238c84f7SMauro Carvalho Chehab .color = FIMC_FMT_RAW10,
45*238c84f7SMauro Carvalho Chehab .memplanes = 1,
46*238c84f7SMauro Carvalho Chehab .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
47*238c84f7SMauro Carvalho Chehab }, {
48*238c84f7SMauro Carvalho Chehab .fourcc = V4L2_PIX_FMT_SGRBG12,
49*238c84f7SMauro Carvalho Chehab .depth = { 12 },
50*238c84f7SMauro Carvalho Chehab .color = FIMC_FMT_RAW12,
51*238c84f7SMauro Carvalho Chehab .memplanes = 1,
52*238c84f7SMauro Carvalho Chehab .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
53*238c84f7SMauro Carvalho Chehab },
54*238c84f7SMauro Carvalho Chehab };
55*238c84f7SMauro Carvalho Chehab
56*238c84f7SMauro Carvalho Chehab /**
57*238c84f7SMauro Carvalho Chehab * fimc_isp_find_format - lookup color format by fourcc or media bus code
58*238c84f7SMauro Carvalho Chehab * @pixelformat: fourcc to match, ignored if null
59*238c84f7SMauro Carvalho Chehab * @mbus_code: media bus code to match, ignored if null
60*238c84f7SMauro Carvalho Chehab * @index: index to the fimc_isp_formats array, ignored if negative
61*238c84f7SMauro Carvalho Chehab */
fimc_isp_find_format(const u32 * pixelformat,const u32 * mbus_code,int index)62*238c84f7SMauro Carvalho Chehab const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
63*238c84f7SMauro Carvalho Chehab const u32 *mbus_code, int index)
64*238c84f7SMauro Carvalho Chehab {
65*238c84f7SMauro Carvalho Chehab const struct fimc_fmt *fmt, *def_fmt = NULL;
66*238c84f7SMauro Carvalho Chehab unsigned int i;
67*238c84f7SMauro Carvalho Chehab int id = 0;
68*238c84f7SMauro Carvalho Chehab
69*238c84f7SMauro Carvalho Chehab if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
70*238c84f7SMauro Carvalho Chehab return NULL;
71*238c84f7SMauro Carvalho Chehab
72*238c84f7SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
73*238c84f7SMauro Carvalho Chehab fmt = &fimc_isp_formats[i];
74*238c84f7SMauro Carvalho Chehab if (pixelformat && fmt->fourcc == *pixelformat)
75*238c84f7SMauro Carvalho Chehab return fmt;
76*238c84f7SMauro Carvalho Chehab if (mbus_code && fmt->mbus_code == *mbus_code)
77*238c84f7SMauro Carvalho Chehab return fmt;
78*238c84f7SMauro Carvalho Chehab if (index == id)
79*238c84f7SMauro Carvalho Chehab def_fmt = fmt;
80*238c84f7SMauro Carvalho Chehab id++;
81*238c84f7SMauro Carvalho Chehab }
82*238c84f7SMauro Carvalho Chehab return def_fmt;
83*238c84f7SMauro Carvalho Chehab }
84*238c84f7SMauro Carvalho Chehab
fimc_isp_irq_handler(struct fimc_is * is)85*238c84f7SMauro Carvalho Chehab void fimc_isp_irq_handler(struct fimc_is *is)
86*238c84f7SMauro Carvalho Chehab {
87*238c84f7SMauro Carvalho Chehab is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
88*238c84f7SMauro Carvalho Chehab is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
89*238c84f7SMauro Carvalho Chehab
90*238c84f7SMauro Carvalho Chehab fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
91*238c84f7SMauro Carvalho Chehab fimc_isp_video_irq_handler(is);
92*238c84f7SMauro Carvalho Chehab
93*238c84f7SMauro Carvalho Chehab wake_up(&is->irq_queue);
94*238c84f7SMauro Carvalho Chehab }
95*238c84f7SMauro Carvalho Chehab
96*238c84f7SMauro Carvalho Chehab /* Capture subdev media entity operations */
fimc_is_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)97*238c84f7SMauro Carvalho Chehab static int fimc_is_link_setup(struct media_entity *entity,
98*238c84f7SMauro Carvalho Chehab const struct media_pad *local,
99*238c84f7SMauro Carvalho Chehab const struct media_pad *remote, u32 flags)
100*238c84f7SMauro Carvalho Chehab {
101*238c84f7SMauro Carvalho Chehab return 0;
102*238c84f7SMauro Carvalho Chehab }
103*238c84f7SMauro Carvalho Chehab
104*238c84f7SMauro Carvalho Chehab static const struct media_entity_operations fimc_is_subdev_media_ops = {
105*238c84f7SMauro Carvalho Chehab .link_setup = fimc_is_link_setup,
106*238c84f7SMauro Carvalho Chehab };
107*238c84f7SMauro Carvalho Chehab
fimc_is_subdev_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)108*238c84f7SMauro Carvalho Chehab static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
109*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_state *sd_state,
110*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_mbus_code_enum *code)
111*238c84f7SMauro Carvalho Chehab {
112*238c84f7SMauro Carvalho Chehab const struct fimc_fmt *fmt;
113*238c84f7SMauro Carvalho Chehab
114*238c84f7SMauro Carvalho Chehab fmt = fimc_isp_find_format(NULL, NULL, code->index);
115*238c84f7SMauro Carvalho Chehab if (!fmt)
116*238c84f7SMauro Carvalho Chehab return -EINVAL;
117*238c84f7SMauro Carvalho Chehab code->code = fmt->mbus_code;
118*238c84f7SMauro Carvalho Chehab return 0;
119*238c84f7SMauro Carvalho Chehab }
120*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)121*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
122*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_state *sd_state,
123*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_format *fmt)
124*238c84f7SMauro Carvalho Chehab {
125*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
126*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt *mf = &fmt->format;
127*238c84f7SMauro Carvalho Chehab
128*238c84f7SMauro Carvalho Chehab if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
129*238c84f7SMauro Carvalho Chehab *mf = *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
130*238c84f7SMauro Carvalho Chehab return 0;
131*238c84f7SMauro Carvalho Chehab }
132*238c84f7SMauro Carvalho Chehab
133*238c84f7SMauro Carvalho Chehab mf->colorspace = V4L2_COLORSPACE_SRGB;
134*238c84f7SMauro Carvalho Chehab
135*238c84f7SMauro Carvalho Chehab mutex_lock(&isp->subdev_lock);
136*238c84f7SMauro Carvalho Chehab
137*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
138*238c84f7SMauro Carvalho Chehab /* ISP OTF input image format */
139*238c84f7SMauro Carvalho Chehab *mf = isp->sink_fmt;
140*238c84f7SMauro Carvalho Chehab } else {
141*238c84f7SMauro Carvalho Chehab /* ISP OTF output image format */
142*238c84f7SMauro Carvalho Chehab *mf = isp->src_fmt;
143*238c84f7SMauro Carvalho Chehab
144*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
145*238c84f7SMauro Carvalho Chehab mf->colorspace = V4L2_COLORSPACE_JPEG;
146*238c84f7SMauro Carvalho Chehab mf->code = MEDIA_BUS_FMT_YUV10_1X30;
147*238c84f7SMauro Carvalho Chehab }
148*238c84f7SMauro Carvalho Chehab }
149*238c84f7SMauro Carvalho Chehab
150*238c84f7SMauro Carvalho Chehab mutex_unlock(&isp->subdev_lock);
151*238c84f7SMauro Carvalho Chehab
152*238c84f7SMauro Carvalho Chehab isp_dbg(1, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", __func__,
153*238c84f7SMauro Carvalho Chehab fmt->pad, mf->code, mf->width, mf->height);
154*238c84f7SMauro Carvalho Chehab
155*238c84f7SMauro Carvalho Chehab return 0;
156*238c84f7SMauro Carvalho Chehab }
157*238c84f7SMauro Carvalho Chehab
__isp_subdev_try_format(struct fimc_isp * isp,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)158*238c84f7SMauro Carvalho Chehab static void __isp_subdev_try_format(struct fimc_isp *isp,
159*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_state *sd_state,
160*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_format *fmt)
161*238c84f7SMauro Carvalho Chehab {
162*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt *mf = &fmt->format;
163*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt *format;
164*238c84f7SMauro Carvalho Chehab
165*238c84f7SMauro Carvalho Chehab mf->colorspace = V4L2_COLORSPACE_SRGB;
166*238c84f7SMauro Carvalho Chehab
167*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
168*238c84f7SMauro Carvalho Chehab v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
169*238c84f7SMauro Carvalho Chehab FIMC_ISP_SINK_WIDTH_MAX, 0,
170*238c84f7SMauro Carvalho Chehab &mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
171*238c84f7SMauro Carvalho Chehab FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
172*238c84f7SMauro Carvalho Chehab mf->code = MEDIA_BUS_FMT_SGRBG10_1X10;
173*238c84f7SMauro Carvalho Chehab } else {
174*238c84f7SMauro Carvalho Chehab if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
175*238c84f7SMauro Carvalho Chehab format = v4l2_subdev_get_try_format(&isp->subdev,
176*238c84f7SMauro Carvalho Chehab sd_state,
177*238c84f7SMauro Carvalho Chehab FIMC_ISP_SD_PAD_SINK);
178*238c84f7SMauro Carvalho Chehab else
179*238c84f7SMauro Carvalho Chehab format = &isp->sink_fmt;
180*238c84f7SMauro Carvalho Chehab
181*238c84f7SMauro Carvalho Chehab /* Allow changing format only on sink pad */
182*238c84f7SMauro Carvalho Chehab mf->width = format->width - FIMC_ISP_CAC_MARGIN_WIDTH;
183*238c84f7SMauro Carvalho Chehab mf->height = format->height - FIMC_ISP_CAC_MARGIN_HEIGHT;
184*238c84f7SMauro Carvalho Chehab
185*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
186*238c84f7SMauro Carvalho Chehab mf->code = MEDIA_BUS_FMT_YUV10_1X30;
187*238c84f7SMauro Carvalho Chehab mf->colorspace = V4L2_COLORSPACE_JPEG;
188*238c84f7SMauro Carvalho Chehab } else {
189*238c84f7SMauro Carvalho Chehab mf->code = format->code;
190*238c84f7SMauro Carvalho Chehab }
191*238c84f7SMauro Carvalho Chehab }
192*238c84f7SMauro Carvalho Chehab }
193*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)194*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
195*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_state *sd_state,
196*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_format *fmt)
197*238c84f7SMauro Carvalho Chehab {
198*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
199*238c84f7SMauro Carvalho Chehab struct fimc_is *is = fimc_isp_to_is(isp);
200*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt *mf = &fmt->format;
201*238c84f7SMauro Carvalho Chehab int ret = 0;
202*238c84f7SMauro Carvalho Chehab
203*238c84f7SMauro Carvalho Chehab isp_dbg(1, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
204*238c84f7SMauro Carvalho Chehab __func__, fmt->pad, mf->code, mf->width, mf->height);
205*238c84f7SMauro Carvalho Chehab
206*238c84f7SMauro Carvalho Chehab mutex_lock(&isp->subdev_lock);
207*238c84f7SMauro Carvalho Chehab __isp_subdev_try_format(isp, sd_state, fmt);
208*238c84f7SMauro Carvalho Chehab
209*238c84f7SMauro Carvalho Chehab if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
210*238c84f7SMauro Carvalho Chehab mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
211*238c84f7SMauro Carvalho Chehab *mf = fmt->format;
212*238c84f7SMauro Carvalho Chehab
213*238c84f7SMauro Carvalho Chehab /* Propagate format to the source pads */
214*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
215*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_format format = *fmt;
216*238c84f7SMauro Carvalho Chehab unsigned int pad;
217*238c84f7SMauro Carvalho Chehab
218*238c84f7SMauro Carvalho Chehab for (pad = FIMC_ISP_SD_PAD_SRC_FIFO;
219*238c84f7SMauro Carvalho Chehab pad < FIMC_ISP_SD_PADS_NUM; pad++) {
220*238c84f7SMauro Carvalho Chehab format.pad = pad;
221*238c84f7SMauro Carvalho Chehab __isp_subdev_try_format(isp, sd_state,
222*238c84f7SMauro Carvalho Chehab &format);
223*238c84f7SMauro Carvalho Chehab mf = v4l2_subdev_get_try_format(sd, sd_state,
224*238c84f7SMauro Carvalho Chehab pad);
225*238c84f7SMauro Carvalho Chehab *mf = format.format;
226*238c84f7SMauro Carvalho Chehab }
227*238c84f7SMauro Carvalho Chehab }
228*238c84f7SMauro Carvalho Chehab } else {
229*238c84f7SMauro Carvalho Chehab if (!media_entity_is_streaming(&sd->entity)) {
230*238c84f7SMauro Carvalho Chehab if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
231*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_format format = *fmt;
232*238c84f7SMauro Carvalho Chehab
233*238c84f7SMauro Carvalho Chehab isp->sink_fmt = *mf;
234*238c84f7SMauro Carvalho Chehab
235*238c84f7SMauro Carvalho Chehab format.pad = FIMC_ISP_SD_PAD_SRC_DMA;
236*238c84f7SMauro Carvalho Chehab __isp_subdev_try_format(isp, sd_state,
237*238c84f7SMauro Carvalho Chehab &format);
238*238c84f7SMauro Carvalho Chehab
239*238c84f7SMauro Carvalho Chehab isp->src_fmt = format.format;
240*238c84f7SMauro Carvalho Chehab __is_set_frame_size(is, &isp->src_fmt);
241*238c84f7SMauro Carvalho Chehab } else {
242*238c84f7SMauro Carvalho Chehab isp->src_fmt = *mf;
243*238c84f7SMauro Carvalho Chehab }
244*238c84f7SMauro Carvalho Chehab } else {
245*238c84f7SMauro Carvalho Chehab ret = -EBUSY;
246*238c84f7SMauro Carvalho Chehab }
247*238c84f7SMauro Carvalho Chehab }
248*238c84f7SMauro Carvalho Chehab
249*238c84f7SMauro Carvalho Chehab mutex_unlock(&isp->subdev_lock);
250*238c84f7SMauro Carvalho Chehab return ret;
251*238c84f7SMauro Carvalho Chehab }
252*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_s_stream(struct v4l2_subdev * sd,int on)253*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
254*238c84f7SMauro Carvalho Chehab {
255*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
256*238c84f7SMauro Carvalho Chehab struct fimc_is *is = fimc_isp_to_is(isp);
257*238c84f7SMauro Carvalho Chehab int ret;
258*238c84f7SMauro Carvalho Chehab
259*238c84f7SMauro Carvalho Chehab isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
260*238c84f7SMauro Carvalho Chehab
261*238c84f7SMauro Carvalho Chehab if (!test_bit(IS_ST_INIT_DONE, &is->state))
262*238c84f7SMauro Carvalho Chehab return -EBUSY;
263*238c84f7SMauro Carvalho Chehab
264*238c84f7SMauro Carvalho Chehab fimc_is_mem_barrier();
265*238c84f7SMauro Carvalho Chehab
266*238c84f7SMauro Carvalho Chehab if (on) {
267*238c84f7SMauro Carvalho Chehab if (__get_pending_param_count(is)) {
268*238c84f7SMauro Carvalho Chehab ret = fimc_is_itf_s_param(is, true);
269*238c84f7SMauro Carvalho Chehab if (ret < 0)
270*238c84f7SMauro Carvalho Chehab return ret;
271*238c84f7SMauro Carvalho Chehab }
272*238c84f7SMauro Carvalho Chehab
273*238c84f7SMauro Carvalho Chehab isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
274*238c84f7SMauro Carvalho Chehab
275*238c84f7SMauro Carvalho Chehab ret = fimc_is_itf_mode_change(is);
276*238c84f7SMauro Carvalho Chehab if (ret)
277*238c84f7SMauro Carvalho Chehab return -EINVAL;
278*238c84f7SMauro Carvalho Chehab
279*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_STREAM_ON, &is->state);
280*238c84f7SMauro Carvalho Chehab fimc_is_hw_stream_on(is);
281*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
282*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT);
283*238c84f7SMauro Carvalho Chehab if (ret < 0) {
284*238c84f7SMauro Carvalho Chehab v4l2_err(sd, "stream on timeout\n");
285*238c84f7SMauro Carvalho Chehab return ret;
286*238c84f7SMauro Carvalho Chehab }
287*238c84f7SMauro Carvalho Chehab } else {
288*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_STREAM_OFF, &is->state);
289*238c84f7SMauro Carvalho Chehab fimc_is_hw_stream_off(is);
290*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
291*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT);
292*238c84f7SMauro Carvalho Chehab if (ret < 0) {
293*238c84f7SMauro Carvalho Chehab v4l2_err(sd, "stream off timeout\n");
294*238c84f7SMauro Carvalho Chehab return ret;
295*238c84f7SMauro Carvalho Chehab }
296*238c84f7SMauro Carvalho Chehab is->setfile.sub_index = 0;
297*238c84f7SMauro Carvalho Chehab }
298*238c84f7SMauro Carvalho Chehab
299*238c84f7SMauro Carvalho Chehab return 0;
300*238c84f7SMauro Carvalho Chehab }
301*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_s_power(struct v4l2_subdev * sd,int on)302*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
303*238c84f7SMauro Carvalho Chehab {
304*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
305*238c84f7SMauro Carvalho Chehab struct fimc_is *is = fimc_isp_to_is(isp);
306*238c84f7SMauro Carvalho Chehab int ret = 0;
307*238c84f7SMauro Carvalho Chehab
308*238c84f7SMauro Carvalho Chehab pr_debug("on: %d\n", on);
309*238c84f7SMauro Carvalho Chehab
310*238c84f7SMauro Carvalho Chehab if (on) {
311*238c84f7SMauro Carvalho Chehab ret = pm_runtime_resume_and_get(&is->pdev->dev);
312*238c84f7SMauro Carvalho Chehab if (ret < 0)
313*238c84f7SMauro Carvalho Chehab return ret;
314*238c84f7SMauro Carvalho Chehab
315*238c84f7SMauro Carvalho Chehab set_bit(IS_ST_PWR_ON, &is->state);
316*238c84f7SMauro Carvalho Chehab
317*238c84f7SMauro Carvalho Chehab ret = fimc_is_start_firmware(is);
318*238c84f7SMauro Carvalho Chehab if (ret < 0) {
319*238c84f7SMauro Carvalho Chehab v4l2_err(sd, "firmware booting failed\n");
320*238c84f7SMauro Carvalho Chehab pm_runtime_put(&is->pdev->dev);
321*238c84f7SMauro Carvalho Chehab return ret;
322*238c84f7SMauro Carvalho Chehab }
323*238c84f7SMauro Carvalho Chehab set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
324*238c84f7SMauro Carvalho Chehab
325*238c84f7SMauro Carvalho Chehab ret = fimc_is_hw_initialize(is);
326*238c84f7SMauro Carvalho Chehab } else {
327*238c84f7SMauro Carvalho Chehab /* Close sensor */
328*238c84f7SMauro Carvalho Chehab if (!test_bit(IS_ST_PWR_ON, &is->state)) {
329*238c84f7SMauro Carvalho Chehab fimc_is_hw_close_sensor(is, 0);
330*238c84f7SMauro Carvalho Chehab
331*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
332*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT);
333*238c84f7SMauro Carvalho Chehab if (ret < 0) {
334*238c84f7SMauro Carvalho Chehab v4l2_err(sd, "sensor close timeout\n");
335*238c84f7SMauro Carvalho Chehab return ret;
336*238c84f7SMauro Carvalho Chehab }
337*238c84f7SMauro Carvalho Chehab }
338*238c84f7SMauro Carvalho Chehab
339*238c84f7SMauro Carvalho Chehab /* SUB IP power off */
340*238c84f7SMauro Carvalho Chehab if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
341*238c84f7SMauro Carvalho Chehab fimc_is_hw_subip_power_off(is);
342*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
343*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT);
344*238c84f7SMauro Carvalho Chehab if (ret < 0) {
345*238c84f7SMauro Carvalho Chehab v4l2_err(sd, "sub-IP power off timeout\n");
346*238c84f7SMauro Carvalho Chehab return ret;
347*238c84f7SMauro Carvalho Chehab }
348*238c84f7SMauro Carvalho Chehab }
349*238c84f7SMauro Carvalho Chehab
350*238c84f7SMauro Carvalho Chehab fimc_is_cpu_set_power(is, 0);
351*238c84f7SMauro Carvalho Chehab pm_runtime_put_sync(&is->pdev->dev);
352*238c84f7SMauro Carvalho Chehab
353*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_PWR_ON, &is->state);
354*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_INIT_DONE, &is->state);
355*238c84f7SMauro Carvalho Chehab is->state = 0;
356*238c84f7SMauro Carvalho Chehab is->config[is->config_index].p_region_index[0] = 0;
357*238c84f7SMauro Carvalho Chehab is->config[is->config_index].p_region_index[1] = 0;
358*238c84f7SMauro Carvalho Chehab set_bit(IS_ST_IDLE, &is->state);
359*238c84f7SMauro Carvalho Chehab wmb();
360*238c84f7SMauro Carvalho Chehab }
361*238c84f7SMauro Carvalho Chehab
362*238c84f7SMauro Carvalho Chehab return ret;
363*238c84f7SMauro Carvalho Chehab }
364*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)365*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
366*238c84f7SMauro Carvalho Chehab struct v4l2_subdev_fh *fh)
367*238c84f7SMauro Carvalho Chehab {
368*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt *format;
369*238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt fmt = {
370*238c84f7SMauro Carvalho Chehab .colorspace = V4L2_COLORSPACE_SRGB,
371*238c84f7SMauro Carvalho Chehab .code = fimc_isp_formats[0].mbus_code,
372*238c84f7SMauro Carvalho Chehab .width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH,
373*238c84f7SMauro Carvalho Chehab .height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT,
374*238c84f7SMauro Carvalho Chehab .field = V4L2_FIELD_NONE,
375*238c84f7SMauro Carvalho Chehab };
376*238c84f7SMauro Carvalho Chehab
377*238c84f7SMauro Carvalho Chehab format = v4l2_subdev_get_try_format(sd, fh->state,
378*238c84f7SMauro Carvalho Chehab FIMC_ISP_SD_PAD_SINK);
379*238c84f7SMauro Carvalho Chehab *format = fmt;
380*238c84f7SMauro Carvalho Chehab
381*238c84f7SMauro Carvalho Chehab format = v4l2_subdev_get_try_format(sd, fh->state,
382*238c84f7SMauro Carvalho Chehab FIMC_ISP_SD_PAD_SRC_FIFO);
383*238c84f7SMauro Carvalho Chehab fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
384*238c84f7SMauro Carvalho Chehab fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
385*238c84f7SMauro Carvalho Chehab *format = fmt;
386*238c84f7SMauro Carvalho Chehab
387*238c84f7SMauro Carvalho Chehab format = v4l2_subdev_get_try_format(sd, fh->state,
388*238c84f7SMauro Carvalho Chehab FIMC_ISP_SD_PAD_SRC_DMA);
389*238c84f7SMauro Carvalho Chehab *format = fmt;
390*238c84f7SMauro Carvalho Chehab
391*238c84f7SMauro Carvalho Chehab return 0;
392*238c84f7SMauro Carvalho Chehab }
393*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_registered(struct v4l2_subdev * sd)394*238c84f7SMauro Carvalho Chehab static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
395*238c84f7SMauro Carvalho Chehab {
396*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
397*238c84f7SMauro Carvalho Chehab int ret;
398*238c84f7SMauro Carvalho Chehab
399*238c84f7SMauro Carvalho Chehab /* Use pipeline object allocated by the media device. */
400*238c84f7SMauro Carvalho Chehab isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
401*238c84f7SMauro Carvalho Chehab
402*238c84f7SMauro Carvalho Chehab ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
403*238c84f7SMauro Carvalho Chehab V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
404*238c84f7SMauro Carvalho Chehab if (ret < 0)
405*238c84f7SMauro Carvalho Chehab isp->video_capture.ve.pipe = NULL;
406*238c84f7SMauro Carvalho Chehab
407*238c84f7SMauro Carvalho Chehab return ret;
408*238c84f7SMauro Carvalho Chehab }
409*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_unregistered(struct v4l2_subdev * sd)410*238c84f7SMauro Carvalho Chehab static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
411*238c84f7SMauro Carvalho Chehab {
412*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = v4l2_get_subdevdata(sd);
413*238c84f7SMauro Carvalho Chehab
414*238c84f7SMauro Carvalho Chehab fimc_isp_video_device_unregister(isp,
415*238c84f7SMauro Carvalho Chehab V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
416*238c84f7SMauro Carvalho Chehab }
417*238c84f7SMauro Carvalho Chehab
418*238c84f7SMauro Carvalho Chehab static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
419*238c84f7SMauro Carvalho Chehab .registered = fimc_isp_subdev_registered,
420*238c84f7SMauro Carvalho Chehab .unregistered = fimc_isp_subdev_unregistered,
421*238c84f7SMauro Carvalho Chehab .open = fimc_isp_subdev_open,
422*238c84f7SMauro Carvalho Chehab };
423*238c84f7SMauro Carvalho Chehab
424*238c84f7SMauro Carvalho Chehab static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
425*238c84f7SMauro Carvalho Chehab .enum_mbus_code = fimc_is_subdev_enum_mbus_code,
426*238c84f7SMauro Carvalho Chehab .get_fmt = fimc_isp_subdev_get_fmt,
427*238c84f7SMauro Carvalho Chehab .set_fmt = fimc_isp_subdev_set_fmt,
428*238c84f7SMauro Carvalho Chehab };
429*238c84f7SMauro Carvalho Chehab
430*238c84f7SMauro Carvalho Chehab static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
431*238c84f7SMauro Carvalho Chehab .s_stream = fimc_isp_subdev_s_stream,
432*238c84f7SMauro Carvalho Chehab };
433*238c84f7SMauro Carvalho Chehab
434*238c84f7SMauro Carvalho Chehab static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
435*238c84f7SMauro Carvalho Chehab .s_power = fimc_isp_subdev_s_power,
436*238c84f7SMauro Carvalho Chehab };
437*238c84f7SMauro Carvalho Chehab
438*238c84f7SMauro Carvalho Chehab static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
439*238c84f7SMauro Carvalho Chehab .core = &fimc_is_core_ops,
440*238c84f7SMauro Carvalho Chehab .video = &fimc_is_subdev_video_ops,
441*238c84f7SMauro Carvalho Chehab .pad = &fimc_is_subdev_pad_ops,
442*238c84f7SMauro Carvalho Chehab };
443*238c84f7SMauro Carvalho Chehab
__ctrl_set_white_balance(struct fimc_is * is,int value)444*238c84f7SMauro Carvalho Chehab static int __ctrl_set_white_balance(struct fimc_is *is, int value)
445*238c84f7SMauro Carvalho Chehab {
446*238c84f7SMauro Carvalho Chehab switch (value) {
447*238c84f7SMauro Carvalho Chehab case V4L2_WHITE_BALANCE_AUTO:
448*238c84f7SMauro Carvalho Chehab __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
449*238c84f7SMauro Carvalho Chehab break;
450*238c84f7SMauro Carvalho Chehab case V4L2_WHITE_BALANCE_DAYLIGHT:
451*238c84f7SMauro Carvalho Chehab __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
452*238c84f7SMauro Carvalho Chehab ISP_AWB_ILLUMINATION_DAYLIGHT);
453*238c84f7SMauro Carvalho Chehab break;
454*238c84f7SMauro Carvalho Chehab case V4L2_WHITE_BALANCE_CLOUDY:
455*238c84f7SMauro Carvalho Chehab __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
456*238c84f7SMauro Carvalho Chehab ISP_AWB_ILLUMINATION_CLOUDY);
457*238c84f7SMauro Carvalho Chehab break;
458*238c84f7SMauro Carvalho Chehab case V4L2_WHITE_BALANCE_INCANDESCENT:
459*238c84f7SMauro Carvalho Chehab __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
460*238c84f7SMauro Carvalho Chehab ISP_AWB_ILLUMINATION_TUNGSTEN);
461*238c84f7SMauro Carvalho Chehab break;
462*238c84f7SMauro Carvalho Chehab case V4L2_WHITE_BALANCE_FLUORESCENT:
463*238c84f7SMauro Carvalho Chehab __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
464*238c84f7SMauro Carvalho Chehab ISP_AWB_ILLUMINATION_FLUORESCENT);
465*238c84f7SMauro Carvalho Chehab break;
466*238c84f7SMauro Carvalho Chehab default:
467*238c84f7SMauro Carvalho Chehab return -EINVAL;
468*238c84f7SMauro Carvalho Chehab }
469*238c84f7SMauro Carvalho Chehab
470*238c84f7SMauro Carvalho Chehab return 0;
471*238c84f7SMauro Carvalho Chehab }
472*238c84f7SMauro Carvalho Chehab
__ctrl_set_aewb_lock(struct fimc_is * is,struct v4l2_ctrl * ctrl)473*238c84f7SMauro Carvalho Chehab static int __ctrl_set_aewb_lock(struct fimc_is *is,
474*238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *ctrl)
475*238c84f7SMauro Carvalho Chehab {
476*238c84f7SMauro Carvalho Chehab bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
477*238c84f7SMauro Carvalho Chehab bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
478*238c84f7SMauro Carvalho Chehab struct isp_param *isp = &is->is_p_region->parameter.isp;
479*238c84f7SMauro Carvalho Chehab int cmd, ret;
480*238c84f7SMauro Carvalho Chehab
481*238c84f7SMauro Carvalho Chehab cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
482*238c84f7SMauro Carvalho Chehab isp->aa.cmd = cmd;
483*238c84f7SMauro Carvalho Chehab isp->aa.target = ISP_AA_TARGET_AE;
484*238c84f7SMauro Carvalho Chehab fimc_is_set_param_bit(is, PARAM_ISP_AA);
485*238c84f7SMauro Carvalho Chehab is->af.ae_lock_state = ae_lock;
486*238c84f7SMauro Carvalho Chehab wmb();
487*238c84f7SMauro Carvalho Chehab
488*238c84f7SMauro Carvalho Chehab ret = fimc_is_itf_s_param(is, false);
489*238c84f7SMauro Carvalho Chehab if (ret < 0)
490*238c84f7SMauro Carvalho Chehab return ret;
491*238c84f7SMauro Carvalho Chehab
492*238c84f7SMauro Carvalho Chehab cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
493*238c84f7SMauro Carvalho Chehab isp->aa.cmd = cmd;
494*238c84f7SMauro Carvalho Chehab isp->aa.target = ISP_AA_TARGET_AE;
495*238c84f7SMauro Carvalho Chehab fimc_is_set_param_bit(is, PARAM_ISP_AA);
496*238c84f7SMauro Carvalho Chehab is->af.awb_lock_state = awb_lock;
497*238c84f7SMauro Carvalho Chehab wmb();
498*238c84f7SMauro Carvalho Chehab
499*238c84f7SMauro Carvalho Chehab return fimc_is_itf_s_param(is, false);
500*238c84f7SMauro Carvalho Chehab }
501*238c84f7SMauro Carvalho Chehab
502*238c84f7SMauro Carvalho Chehab /* Supported manual ISO values */
503*238c84f7SMauro Carvalho Chehab static const s64 iso_qmenu[] = {
504*238c84f7SMauro Carvalho Chehab 50, 100, 200, 400, 800,
505*238c84f7SMauro Carvalho Chehab };
506*238c84f7SMauro Carvalho Chehab
__ctrl_set_iso(struct fimc_is * is,int value)507*238c84f7SMauro Carvalho Chehab static int __ctrl_set_iso(struct fimc_is *is, int value)
508*238c84f7SMauro Carvalho Chehab {
509*238c84f7SMauro Carvalho Chehab unsigned int idx, iso;
510*238c84f7SMauro Carvalho Chehab
511*238c84f7SMauro Carvalho Chehab if (value == V4L2_ISO_SENSITIVITY_AUTO) {
512*238c84f7SMauro Carvalho Chehab __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
513*238c84f7SMauro Carvalho Chehab return 0;
514*238c84f7SMauro Carvalho Chehab }
515*238c84f7SMauro Carvalho Chehab idx = is->isp.ctrls.iso->val;
516*238c84f7SMauro Carvalho Chehab if (idx >= ARRAY_SIZE(iso_qmenu))
517*238c84f7SMauro Carvalho Chehab return -EINVAL;
518*238c84f7SMauro Carvalho Chehab
519*238c84f7SMauro Carvalho Chehab iso = iso_qmenu[idx];
520*238c84f7SMauro Carvalho Chehab __is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
521*238c84f7SMauro Carvalho Chehab return 0;
522*238c84f7SMauro Carvalho Chehab }
523*238c84f7SMauro Carvalho Chehab
__ctrl_set_metering(struct fimc_is * is,unsigned int value)524*238c84f7SMauro Carvalho Chehab static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
525*238c84f7SMauro Carvalho Chehab {
526*238c84f7SMauro Carvalho Chehab unsigned int val;
527*238c84f7SMauro Carvalho Chehab
528*238c84f7SMauro Carvalho Chehab switch (value) {
529*238c84f7SMauro Carvalho Chehab case V4L2_EXPOSURE_METERING_AVERAGE:
530*238c84f7SMauro Carvalho Chehab val = ISP_METERING_COMMAND_AVERAGE;
531*238c84f7SMauro Carvalho Chehab break;
532*238c84f7SMauro Carvalho Chehab case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
533*238c84f7SMauro Carvalho Chehab val = ISP_METERING_COMMAND_CENTER;
534*238c84f7SMauro Carvalho Chehab break;
535*238c84f7SMauro Carvalho Chehab case V4L2_EXPOSURE_METERING_SPOT:
536*238c84f7SMauro Carvalho Chehab val = ISP_METERING_COMMAND_SPOT;
537*238c84f7SMauro Carvalho Chehab break;
538*238c84f7SMauro Carvalho Chehab case V4L2_EXPOSURE_METERING_MATRIX:
539*238c84f7SMauro Carvalho Chehab val = ISP_METERING_COMMAND_MATRIX;
540*238c84f7SMauro Carvalho Chehab break;
541*238c84f7SMauro Carvalho Chehab default:
542*238c84f7SMauro Carvalho Chehab return -EINVAL;
543*238c84f7SMauro Carvalho Chehab }
544*238c84f7SMauro Carvalho Chehab
545*238c84f7SMauro Carvalho Chehab __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
546*238c84f7SMauro Carvalho Chehab return 0;
547*238c84f7SMauro Carvalho Chehab }
548*238c84f7SMauro Carvalho Chehab
__ctrl_set_afc(struct fimc_is * is,int value)549*238c84f7SMauro Carvalho Chehab static int __ctrl_set_afc(struct fimc_is *is, int value)
550*238c84f7SMauro Carvalho Chehab {
551*238c84f7SMauro Carvalho Chehab switch (value) {
552*238c84f7SMauro Carvalho Chehab case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
553*238c84f7SMauro Carvalho Chehab __is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
554*238c84f7SMauro Carvalho Chehab break;
555*238c84f7SMauro Carvalho Chehab case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
556*238c84f7SMauro Carvalho Chehab __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
557*238c84f7SMauro Carvalho Chehab break;
558*238c84f7SMauro Carvalho Chehab case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
559*238c84f7SMauro Carvalho Chehab __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
560*238c84f7SMauro Carvalho Chehab break;
561*238c84f7SMauro Carvalho Chehab case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
562*238c84f7SMauro Carvalho Chehab __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
563*238c84f7SMauro Carvalho Chehab break;
564*238c84f7SMauro Carvalho Chehab default:
565*238c84f7SMauro Carvalho Chehab return -EINVAL;
566*238c84f7SMauro Carvalho Chehab }
567*238c84f7SMauro Carvalho Chehab
568*238c84f7SMauro Carvalho Chehab return 0;
569*238c84f7SMauro Carvalho Chehab }
570*238c84f7SMauro Carvalho Chehab
__ctrl_set_image_effect(struct fimc_is * is,int value)571*238c84f7SMauro Carvalho Chehab static int __ctrl_set_image_effect(struct fimc_is *is, int value)
572*238c84f7SMauro Carvalho Chehab {
573*238c84f7SMauro Carvalho Chehab static const u8 effects[][2] = {
574*238c84f7SMauro Carvalho Chehab { V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE },
575*238c84f7SMauro Carvalho Chehab { V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME },
576*238c84f7SMauro Carvalho Chehab { V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA },
577*238c84f7SMauro Carvalho Chehab { V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
578*238c84f7SMauro Carvalho Chehab { 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
579*238c84f7SMauro Carvalho Chehab };
580*238c84f7SMauro Carvalho Chehab int i;
581*238c84f7SMauro Carvalho Chehab
582*238c84f7SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(effects); i++) {
583*238c84f7SMauro Carvalho Chehab if (effects[i][0] != value)
584*238c84f7SMauro Carvalho Chehab continue;
585*238c84f7SMauro Carvalho Chehab
586*238c84f7SMauro Carvalho Chehab __is_set_isp_effect(is, effects[i][1]);
587*238c84f7SMauro Carvalho Chehab return 0;
588*238c84f7SMauro Carvalho Chehab }
589*238c84f7SMauro Carvalho Chehab
590*238c84f7SMauro Carvalho Chehab return -EINVAL;
591*238c84f7SMauro Carvalho Chehab }
592*238c84f7SMauro Carvalho Chehab
fimc_is_s_ctrl(struct v4l2_ctrl * ctrl)593*238c84f7SMauro Carvalho Chehab static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
594*238c84f7SMauro Carvalho Chehab {
595*238c84f7SMauro Carvalho Chehab struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
596*238c84f7SMauro Carvalho Chehab struct fimc_is *is = fimc_isp_to_is(isp);
597*238c84f7SMauro Carvalho Chehab bool set_param = true;
598*238c84f7SMauro Carvalho Chehab int ret = 0;
599*238c84f7SMauro Carvalho Chehab
600*238c84f7SMauro Carvalho Chehab switch (ctrl->id) {
601*238c84f7SMauro Carvalho Chehab case V4L2_CID_CONTRAST:
602*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
603*238c84f7SMauro Carvalho Chehab ctrl->val);
604*238c84f7SMauro Carvalho Chehab break;
605*238c84f7SMauro Carvalho Chehab
606*238c84f7SMauro Carvalho Chehab case V4L2_CID_SATURATION:
607*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
608*238c84f7SMauro Carvalho Chehab ctrl->val);
609*238c84f7SMauro Carvalho Chehab break;
610*238c84f7SMauro Carvalho Chehab
611*238c84f7SMauro Carvalho Chehab case V4L2_CID_SHARPNESS:
612*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
613*238c84f7SMauro Carvalho Chehab ctrl->val);
614*238c84f7SMauro Carvalho Chehab break;
615*238c84f7SMauro Carvalho Chehab
616*238c84f7SMauro Carvalho Chehab case V4L2_CID_EXPOSURE_ABSOLUTE:
617*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
618*238c84f7SMauro Carvalho Chehab ctrl->val);
619*238c84f7SMauro Carvalho Chehab break;
620*238c84f7SMauro Carvalho Chehab
621*238c84f7SMauro Carvalho Chehab case V4L2_CID_BRIGHTNESS:
622*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
623*238c84f7SMauro Carvalho Chehab ctrl->val);
624*238c84f7SMauro Carvalho Chehab break;
625*238c84f7SMauro Carvalho Chehab
626*238c84f7SMauro Carvalho Chehab case V4L2_CID_HUE:
627*238c84f7SMauro Carvalho Chehab __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
628*238c84f7SMauro Carvalho Chehab ctrl->val);
629*238c84f7SMauro Carvalho Chehab break;
630*238c84f7SMauro Carvalho Chehab
631*238c84f7SMauro Carvalho Chehab case V4L2_CID_EXPOSURE_METERING:
632*238c84f7SMauro Carvalho Chehab ret = __ctrl_set_metering(is, ctrl->val);
633*238c84f7SMauro Carvalho Chehab break;
634*238c84f7SMauro Carvalho Chehab
635*238c84f7SMauro Carvalho Chehab case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
636*238c84f7SMauro Carvalho Chehab ret = __ctrl_set_white_balance(is, ctrl->val);
637*238c84f7SMauro Carvalho Chehab break;
638*238c84f7SMauro Carvalho Chehab
639*238c84f7SMauro Carvalho Chehab case V4L2_CID_3A_LOCK:
640*238c84f7SMauro Carvalho Chehab ret = __ctrl_set_aewb_lock(is, ctrl);
641*238c84f7SMauro Carvalho Chehab set_param = false;
642*238c84f7SMauro Carvalho Chehab break;
643*238c84f7SMauro Carvalho Chehab
644*238c84f7SMauro Carvalho Chehab case V4L2_CID_ISO_SENSITIVITY_AUTO:
645*238c84f7SMauro Carvalho Chehab ret = __ctrl_set_iso(is, ctrl->val);
646*238c84f7SMauro Carvalho Chehab break;
647*238c84f7SMauro Carvalho Chehab
648*238c84f7SMauro Carvalho Chehab case V4L2_CID_POWER_LINE_FREQUENCY:
649*238c84f7SMauro Carvalho Chehab ret = __ctrl_set_afc(is, ctrl->val);
650*238c84f7SMauro Carvalho Chehab break;
651*238c84f7SMauro Carvalho Chehab
652*238c84f7SMauro Carvalho Chehab case V4L2_CID_COLORFX:
653*238c84f7SMauro Carvalho Chehab __ctrl_set_image_effect(is, ctrl->val);
654*238c84f7SMauro Carvalho Chehab break;
655*238c84f7SMauro Carvalho Chehab
656*238c84f7SMauro Carvalho Chehab default:
657*238c84f7SMauro Carvalho Chehab ret = -EINVAL;
658*238c84f7SMauro Carvalho Chehab break;
659*238c84f7SMauro Carvalho Chehab }
660*238c84f7SMauro Carvalho Chehab
661*238c84f7SMauro Carvalho Chehab if (ret < 0) {
662*238c84f7SMauro Carvalho Chehab v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
663*238c84f7SMauro Carvalho Chehab ctrl->name, ctrl->val);
664*238c84f7SMauro Carvalho Chehab return ret;
665*238c84f7SMauro Carvalho Chehab }
666*238c84f7SMauro Carvalho Chehab
667*238c84f7SMauro Carvalho Chehab if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
668*238c84f7SMauro Carvalho Chehab return fimc_is_itf_s_param(is, true);
669*238c84f7SMauro Carvalho Chehab
670*238c84f7SMauro Carvalho Chehab return 0;
671*238c84f7SMauro Carvalho Chehab }
672*238c84f7SMauro Carvalho Chehab
673*238c84f7SMauro Carvalho Chehab static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
674*238c84f7SMauro Carvalho Chehab .s_ctrl = fimc_is_s_ctrl,
675*238c84f7SMauro Carvalho Chehab };
676*238c84f7SMauro Carvalho Chehab
__isp_subdev_set_default_format(struct fimc_isp * isp)677*238c84f7SMauro Carvalho Chehab static void __isp_subdev_set_default_format(struct fimc_isp *isp)
678*238c84f7SMauro Carvalho Chehab {
679*238c84f7SMauro Carvalho Chehab struct fimc_is *is = fimc_isp_to_is(isp);
680*238c84f7SMauro Carvalho Chehab
681*238c84f7SMauro Carvalho Chehab isp->sink_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH +
682*238c84f7SMauro Carvalho Chehab FIMC_ISP_CAC_MARGIN_WIDTH;
683*238c84f7SMauro Carvalho Chehab isp->sink_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT +
684*238c84f7SMauro Carvalho Chehab FIMC_ISP_CAC_MARGIN_HEIGHT;
685*238c84f7SMauro Carvalho Chehab isp->sink_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
686*238c84f7SMauro Carvalho Chehab
687*238c84f7SMauro Carvalho Chehab isp->src_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
688*238c84f7SMauro Carvalho Chehab isp->src_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
689*238c84f7SMauro Carvalho Chehab isp->src_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
690*238c84f7SMauro Carvalho Chehab __is_set_frame_size(is, &isp->src_fmt);
691*238c84f7SMauro Carvalho Chehab }
692*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_create(struct fimc_isp * isp)693*238c84f7SMauro Carvalho Chehab int fimc_isp_subdev_create(struct fimc_isp *isp)
694*238c84f7SMauro Carvalho Chehab {
695*238c84f7SMauro Carvalho Chehab const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
696*238c84f7SMauro Carvalho Chehab struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
697*238c84f7SMauro Carvalho Chehab struct v4l2_subdev *sd = &isp->subdev;
698*238c84f7SMauro Carvalho Chehab struct fimc_isp_ctrls *ctrls = &isp->ctrls;
699*238c84f7SMauro Carvalho Chehab int ret;
700*238c84f7SMauro Carvalho Chehab
701*238c84f7SMauro Carvalho Chehab mutex_init(&isp->subdev_lock);
702*238c84f7SMauro Carvalho Chehab
703*238c84f7SMauro Carvalho Chehab v4l2_subdev_init(sd, &fimc_is_subdev_ops);
704*238c84f7SMauro Carvalho Chehab
705*238c84f7SMauro Carvalho Chehab sd->owner = THIS_MODULE;
706*238c84f7SMauro Carvalho Chehab sd->grp_id = GRP_ID_FIMC_IS;
707*238c84f7SMauro Carvalho Chehab sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
708*238c84f7SMauro Carvalho Chehab snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
709*238c84f7SMauro Carvalho Chehab
710*238c84f7SMauro Carvalho Chehab sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
711*238c84f7SMauro Carvalho Chehab isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
712*238c84f7SMauro Carvalho Chehab isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
713*238c84f7SMauro Carvalho Chehab isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
714*238c84f7SMauro Carvalho Chehab ret = media_entity_pads_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
715*238c84f7SMauro Carvalho Chehab isp->subdev_pads);
716*238c84f7SMauro Carvalho Chehab if (ret)
717*238c84f7SMauro Carvalho Chehab return ret;
718*238c84f7SMauro Carvalho Chehab
719*238c84f7SMauro Carvalho Chehab v4l2_ctrl_handler_init(handler, 20);
720*238c84f7SMauro Carvalho Chehab
721*238c84f7SMauro Carvalho Chehab ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
722*238c84f7SMauro Carvalho Chehab -2, 2, 1, 0);
723*238c84f7SMauro Carvalho Chehab ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
724*238c84f7SMauro Carvalho Chehab -4, 4, 1, 0);
725*238c84f7SMauro Carvalho Chehab ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
726*238c84f7SMauro Carvalho Chehab -2, 2, 1, 0);
727*238c84f7SMauro Carvalho Chehab ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
728*238c84f7SMauro Carvalho Chehab -2, 2, 1, 0);
729*238c84f7SMauro Carvalho Chehab ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
730*238c84f7SMauro Carvalho Chehab -2, 2, 1, 0);
731*238c84f7SMauro Carvalho Chehab
732*238c84f7SMauro Carvalho Chehab ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
733*238c84f7SMauro Carvalho Chehab V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
734*238c84f7SMauro Carvalho Chehab 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
735*238c84f7SMauro Carvalho Chehab
736*238c84f7SMauro Carvalho Chehab ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
737*238c84f7SMauro Carvalho Chehab V4L2_CID_EXPOSURE_ABSOLUTE,
738*238c84f7SMauro Carvalho Chehab -4, 4, 1, 0);
739*238c84f7SMauro Carvalho Chehab
740*238c84f7SMauro Carvalho Chehab ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
741*238c84f7SMauro Carvalho Chehab V4L2_CID_EXPOSURE_METERING, 3,
742*238c84f7SMauro Carvalho Chehab ~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
743*238c84f7SMauro Carvalho Chehab
744*238c84f7SMauro Carvalho Chehab v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
745*238c84f7SMauro Carvalho Chehab V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
746*238c84f7SMauro Carvalho Chehab V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
747*238c84f7SMauro Carvalho Chehab /* ISO sensitivity */
748*238c84f7SMauro Carvalho Chehab ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
749*238c84f7SMauro Carvalho Chehab V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
750*238c84f7SMauro Carvalho Chehab V4L2_ISO_SENSITIVITY_AUTO);
751*238c84f7SMauro Carvalho Chehab
752*238c84f7SMauro Carvalho Chehab ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
753*238c84f7SMauro Carvalho Chehab V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
754*238c84f7SMauro Carvalho Chehab ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
755*238c84f7SMauro Carvalho Chehab
756*238c84f7SMauro Carvalho Chehab ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
757*238c84f7SMauro Carvalho Chehab V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
758*238c84f7SMauro Carvalho Chehab
759*238c84f7SMauro Carvalho Chehab /* TODO: Add support for NEGATIVE_COLOR option */
760*238c84f7SMauro Carvalho Chehab ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
761*238c84f7SMauro Carvalho Chehab V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
762*238c84f7SMauro Carvalho Chehab
763*238c84f7SMauro Carvalho Chehab if (handler->error) {
764*238c84f7SMauro Carvalho Chehab media_entity_cleanup(&sd->entity);
765*238c84f7SMauro Carvalho Chehab return handler->error;
766*238c84f7SMauro Carvalho Chehab }
767*238c84f7SMauro Carvalho Chehab
768*238c84f7SMauro Carvalho Chehab v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
769*238c84f7SMauro Carvalho Chehab V4L2_ISO_SENSITIVITY_MANUAL, false);
770*238c84f7SMauro Carvalho Chehab
771*238c84f7SMauro Carvalho Chehab sd->ctrl_handler = handler;
772*238c84f7SMauro Carvalho Chehab sd->internal_ops = &fimc_is_subdev_internal_ops;
773*238c84f7SMauro Carvalho Chehab sd->entity.ops = &fimc_is_subdev_media_ops;
774*238c84f7SMauro Carvalho Chehab v4l2_set_subdevdata(sd, isp);
775*238c84f7SMauro Carvalho Chehab
776*238c84f7SMauro Carvalho Chehab __isp_subdev_set_default_format(isp);
777*238c84f7SMauro Carvalho Chehab
778*238c84f7SMauro Carvalho Chehab return 0;
779*238c84f7SMauro Carvalho Chehab }
780*238c84f7SMauro Carvalho Chehab
fimc_isp_subdev_destroy(struct fimc_isp * isp)781*238c84f7SMauro Carvalho Chehab void fimc_isp_subdev_destroy(struct fimc_isp *isp)
782*238c84f7SMauro Carvalho Chehab {
783*238c84f7SMauro Carvalho Chehab struct v4l2_subdev *sd = &isp->subdev;
784*238c84f7SMauro Carvalho Chehab
785*238c84f7SMauro Carvalho Chehab v4l2_device_unregister_subdev(sd);
786*238c84f7SMauro Carvalho Chehab media_entity_cleanup(&sd->entity);
787*238c84f7SMauro Carvalho Chehab v4l2_ctrl_handler_free(&isp->ctrls.handler);
788*238c84f7SMauro Carvalho Chehab v4l2_set_subdevdata(sd, NULL);
789*238c84f7SMauro Carvalho Chehab }
790